JPS6144663A - Printing apparatus - Google Patents

Abstract

PURPOSE:To maintain the space between two data constant even though the letter row printed on the left side in the same line printing the left side data is variable in its length by establshing the prescribed space interval at the point of time when the printing of the data to be printed on the left side is accomplished. CONSTITUTION:The data of the letter, mark or the like to be printed on the left side of the same line are housed in a data buffer 2 from the front address continuously, and a content of a address counter 4 is increased by one by the clock signal CL1 when the AND gate 5 opend, and the position data corresponding to the content of the counter 4 is read out by the data buffer 2. The data to be printed on the right side of the same line is read out from the data buffer by the clock signal LC3 in the same manner, and being sent to a printer 9 through OR circuit 8. The space interval as same as the pre-established distance is established at the point of time when the printing of the data to be printed on the left side, then the right side data is printed.

Description

[Detailed description of the invention]

(a) Industrial application field The present invention is applicable to the case where two print data are printed on the same line.
This invention relates to a printing device f for making the printing easy to see by increasing the length of the print data on the left side and setting the printing start position of the print data on the right side at the maximum of 211rc. (B) Conventional technology A specific example of printing two types of data, at least one of which has a variable length, on the same line is mail merge printing (1932).
“New” published by Kyoikusha on May 20th,
t on Separate volume 1 All about word processors”
]. (c) Problems to be solved by the invention If two pieces of print data are both fixed lengths in hot FCl insert printing, it is easiest to print and Prints beautifully. Even if one of the data is variable length, if the data printed on the left side of the same line is fixed length, it can be printed easily if the printing start position is determined in advance. However, if the data printed on the left side is of variable length, if you try to print it in an easy-to-read manner,
If the print start position of the data printed on the right side is fixed, the space between the two print data may become clogged, spread out, or overlap, and in this case, the print result may be very difficult to see, or if it is severe, it may be difficult to check. Situations that cannot be done also occur]
Obtained. The above-mentioned disadvantages will be explained with reference to FIG. 2 as an example of actual printing. Figure 2 shows the conventional printing of names and titles; the data on the left (name) is of variable length, ranging from 1 to 3 characters.
The printing position of the data on the right (honorific title) is fixed at the 4th character.For this reason, in the case of ■, the data interval becomes wide.In the case of ■, the print position is fixed. In the case of ■, the fourth character is overwritten, making it impossible to confirm the character.・In this case, the printing was not easy to read. In view of the above, I decided to change the method of printing two pieces of data on the same line, and set a space interval of a preset distance when the data printed on the left side is finished printing. After that, it is intended to provide a printing device to print the data on the right side. (E) Function With such a printing device, the distance between two pieces of data can always be kept constant. (F) Embodiment Figure 1 is a block circuit showing an embodiment of the present invention, and (1) is a control section consisting of, for example, a microphone and a computer. 6゜(2), which controls the control, is set in the first data buffer, and the data buffer rc is one or more data such as characters and symbols to be printed on the left side of the same line consecutively from the first address. (3J is the first clock signal generator, +4) t: is the first address counter, (5) is the first AND gate, and the first address counter (4) is the 4JF
Stores the address for addressing the 11 data buffer (2), and the above! When the AND gate (5) of No. 1 is open, the clock signal CLi from the clock signal generator (3)
increases its contents by 1. Further, the clock signal CLf is input to 4!1 through the AND gate (5) of jlH.
When this signal is input, the first data buffer (2) reads the data at the position corresponding to the contents of the first address counter (4B). When it is, it always outputs %11t-, and when it is not, it outputs %Of.The 1M first gate circuit is open when the output of the first comparator (6) is 11'. None The data read from the first data buffer (2) is sent to the printer (9) via the OR circuit (8).The printer (9) receives input via the OR circuit (8). The output signal of the first comparator (6) is input to the first AND gate (5) to control opening/closing of the gate, and also to control the opening/closing of the first inverting gate. The inverted signal inverted by 3
It is input to one input terminal of the second AND gate σD of Jinrikiya. flat is a second clock signal generator, and the signal CL2 outputted from the generator is supplied to one input terminal of the $2 AND gate υ. (13Fi increment counter, I is the second gate circuit, +15 is a space register that always outputs the space code for printing, and the second AND gate aυ
When 11# is output, the increment counter (13Fi) counts up its contents by 1, and the gate circuit !2 (141 is open) outputs the space register C151;!:r space data. is sent to the printer (9) via the second gate circuit ri4 and the OR circuit (8). tte is an interval register, and this register contains the space register 15 and the printer (9). The number shift of the space code to be output is set in advance.C171 is determined by a second comparator, which compares the content IN of the increment counter port 3 with the content N of the interval register 161. ) IN, it outputs 11#, and when N<IN, it outputs 10#.The output of the comparator αD of 4!I2 is supplied to the 1 input terminal of the second AND gate υ, and The second inversion gate) is inverted at tI& and is supplied to one input terminal of the third AND gate 0 of the two-manpower type. Therefore, the above second game) (Ll) #ith, 10th inversion)
(The output from 1G and the output from the second comparator are both 1
11, the clock signal CL2 is supplied to the gate circuit (14rc) of the increment counter a3 and tJ2. 1
The above data is stored consecutively starting from the first address. CI! 1iti@3 clock signal generator, @ is a second address counter, and the second address counter is the same as the above 4! The third clock signal generator t2D stores an address for addressing the data buffer 1 of I2, and when the third AND gate 9 is open (when the output of the second inverting gate low a is 111), the third clock signal generator t2D clock signal CL from
: 51C counts up by the content t1. The clock signal CL3 is also sent to the second data buffer (2) via the third AND gate σ9, but when such a signal is input, the second data buffer (2) sends it to the second addonta (9). . Next, the operation of such a block circuit will be explained. First, control unit (1) Fi, first, @2 address counter (4) (23, first and second data buffers (2)
■, 1.4! The comparison circuit (6) αη of I2, the increment note counter α3, and the interval register 161 are initialized. Specifically, 1.4I! E2 address counter (
4) ■ and the contents of increment counter a3 to '01
and ff11, the output from the second comparator (6 η) is 1
When set to 1-, the rc first and second data buffers (2) (2G contain data such as characters and symbols printed on the left and right sides of the same line, respectively, at their respective starting addresses (
1 address), and is stored consecutively from address 1 to interval register (L address 1).
For example, 111 is set in G as N. Below, the above 1. Second data buffer (2) (21
) The operation after initialization will be explained for each specific example of the data stored in each. (1) The first data buffer (2) stores data of one character "Hara" starting from its leading address, and the second data buffer stores data of one character "Sama" starting from its leading address. When stored, the output of the first comparator (6) is 111 due to initialization, so @1
clock signal generator (signal CI from 3J, ↑ is ¥1
J1 address counter

(4) and is input to the first data buffer (2). As a result, the contents of the first address counter (4) are 25" 1 ', and the contents of the first data buffer (2) corresponding to the contents of the counter (4) are
), that is, the data corresponding to the character ``original'' stored at the first address is read out from the buffer (2). Since the read data is to be printed, the output of the first comparator (6) remains at 111.
Therefore, the data Fi corresponding to this character "hara" is pre/reacted (9) via the first gate circuit (7) and the OR circuit (8).
)K is sent out, and the character "Original" is printed by the printer (9). At the time the character "Hara" is printed, the above 1st
The output of the comparator (6) is 11', so. Again, the signal issued from the first clock signal generator (3) is sent out via the first AND gate (5) to the first address counter (4) and the data buffer (23K) of gIJl.Therefore, the first address Color/R+43 is counted up and its content becomes ri'2', and the data stored in the second address of the first data buffer (2) is read out.However, such data should not be printed. Since it is not a kimono, the output h 'o' of the first comparator (6)
Therefore, the first gate circuit (71 and gFll
Both AND gates [4] are closed, and reading of data from the data buffer (2) of il is completed. When the output of the first comparison f:D16) becomes 10', it is inverted by the first inverting gate aarc and becomes 1#, which is supplied to the second AND gate circle. At this time, the second comparator
Since the output of is also 11', the second AND gate a
υ is opened, and the clock signal CL2 generated from the second clock signal generator α2 is input to the increment counter a3 and the second gate circuit I. When this signal is input to the increment counter a3, the contents of the counter (13) are counted up by 11# and become 11#, and when the signal is input to the second gate circuit tlJ, the gate circuit α4 is opened. Therefore, the second space register l19
The space data is sent to the printer (9) through the gate circuit fi4 and the OR circuit (8) t-, and the printer (9) then prints a space for one character immediately after the already printed character "Original". Secure the area. At this time, the content of the increment counter α3 is IN
becomes 111, and since the value N stored in the interval register (tlK is also 11'), the second comparator α7)rc is found to satisfy IN)N. Therefore, the output of the second comparator αη becomes 10I. Along with this, the second AND gate αυ is closed, so that from now on, the space data is sent from the space register f15 to the printer (9) and the output of the increment counter second comparison port a becomes 10#. Then, such an output is inverted from the second inverting gate 18, and therefore 111 is input to one input terminal of the third AND gate 4, so the gate 19 becomes open. Therefore, from now on, the clock signal generator Qυ of path 3 will also generate the clock signal CL3F.
i is input to the second address counter 4 and the second data buffer (21). Based on the input of the clock signal CL3, what is the content of the $2 address counter? The count is increased by 1' and becomes 111, and 4! I2 data buffer c! G
The data at the first address corresponding to the content of the color/re@ is sent to the printer (93rc) via the OR circuit [81.Now, the data stored at the first address of the second data buffer ■ is a character. Since it corresponds to the character "sama", the above printer (9J) prints the character "sama" after the space area that has already been reserved.
The character ``sama'' is printed after the character ``hara'' with a space for one character. Although not shown in FIG. 1, the completion of reading data from the second data buffer (2) is determined by the first test for determining the completion of reading data from the first data buffer (2). This can be easily done by adding the same functions as the comparator (6) and the first gate circuit (7). (11) The first data buffer (2) rc stores four characters of data "Mushakoji" consecutively from its first address, and the second data buffer CIDrc stores one character "sama" at its first address. When data is stored, the output of the first comparator +6+ is 111 due to initialization.
Therefore, the signal CLI from the first clock signal generator f37 is applied to the first address counter (4) and the first clock signal generator f37.
data buffer (2). This allows the first
The content of the address counter (4) becomes 11', and the character "BU" stored at the storage position of the first data buffer (2) corresponding to the content of the counter (4), that is, the first address. The corresponding data is read out from the buffer (2). Since the read data is to be printed, the output of the comparator (6) of @1 remains 111, so The data corresponding to the character “bu” for the lever is the first
is sent to the printer (9) via the gate circuit (7) and the OR circuit (81), and the printer t93 outputs "Wu".
Tori characters are printed. At the time the character ``Take'' was printed. Since the output ri'i' of the first comparator (6) is the output ri'i' of the first comparator (6), the signal emitted from the first clock signal generator (3J) is passed through the first AND gate (5) to the first address counter [ 4] and is sent to the first data buffer (2). Therefore, the first address counter +4J counts up and its content becomes 12#, and accordingly @1
The data corresponding to the character "person" stored at address gIJ2 of the data buffer (2) is read out. Since such read data is to be printed, the output of the first comparator (6) remains 111, and therefore the data corresponding to this character "person" is sent to the first tart circuit ( 7) and the printer (93K) via the OR circuit (8).
The character ``Shi'' is sent out, and the character ``Shi'' is printed immediately after the character ``BU'' which has already been printed. By repeating the above operation, the contents of the first address counter [4] increase sequentially to 13# and %41, and accordingly, the third and fourth addresses of the first data buffer (2) The data corresponding to the character "small" and the data corresponding to the character "ro" stored in are also sequentially read out and sent to the printer (9), and in this way, the printer (9) reads the g! 51 comparator 1
6) is the output Fi'1'. Again, the signal issued from the first clock signal generator (3) is sent to the first address counter (4) and the first data buffer (2JK) via the first AND gate (5). The address counter (4) of yEl is counted up, and its content becomes Fi's'. The output of the comparator (6) of gi becomes t Oa, so the first gate circuit (7) and the first AND gate (4) are both closed.Reading data from the data buffer (2) of gi is as follows. When the output of the first comparator [6] becomes %0-, it is inverted by the first inverting gate aarc and becomes %11) and is supplied to the second AND gate 11). At this time, the second comparator α
Since the output of η is also 11'', the second ant game) (
11) Fi is opened and the clock signal CL2 generated from the 4×2 clock signal generator C2 is input to the increment counter α3 and the second gate circuit α4. When such a signal is input to an increment counter (13), the counter (13 contents t! is counted up by '1' and becomes 1).
11, and as soon as the second gate circuit r14rt is input, such gate circuit I becomes open, so the second gate circuit (141 and OR circuit (8)
The space data is sent to the printer (9) via
This printer (9J is a character that has already been printed.
〇At this time, the above increment counter (content I of 13) is secured.
Since N is 11# and the value N stored in the interval register cLe is also +111, the second comparator a'nr
c, it turns out that IN:>N is satisfied, so the output of the second comparator η should be llO#. Along with this, the second AND gate 111) is closed, so that the sending of space data from the space register lcJ to the printer (9) and the counting up of the increment counter u3 are also stopped. When the output of the second comparator (lη becomes '0-', the output Fi is inverted by the second inverting gate) 181 and therefore slt is input to the 1 input terminal of the third AND gate 19. Therefore, the gate α9ti is opened. Therefore, from now on, the clock signal CL3 generated from the third clock signal generator Qυ is inputted to the second address color /RI@ and the second data buffer (2). The above based on the input rc of the above clock signal CL, 3! 2
The address counter Q is incremented by i1t%12 and becomes 11', and the second data buffer c
! I sends the data at the first address corresponding to the contents of the counter (27J) to the printer (9) via the OR circuit (8). Since the data corresponds to the character "sama",
The printer (9) prints the character "Sama" after the space area that has already been reserved. Figure 2 shows the print state obtained by the above operation, and prints the characters "Mushakoji" after the four consecutive characters. The character ``sama'' is printed afterward with a space for one character. ()) Effect According to the printing device R of the present invention, even if the character string printed on the left side in the same line has a variable length, it is possible to always maintain a constant distance rcVi from the character string located on the right side. This makes it possible to print beautiful characters by applying it to mail-merge printing, etc.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention, 8
FIG. 2 is a schematic diagram showing the printing state obtained by the apparatus of this embodiment, and FIG. 3 is a schematic diagram showing the conventional printing state. (2)...First data buffer, (6) ...First
comparator (detection means), σto/interval register, ■...
Second data buffer.

Claims (1)

[Claims] (1) When printing two types of data, at least one of which is variable length, on the same line, a first data buffer into which one variable length data is introduced, and a second data buffer into which the other data is introduced. , an interval register for setting the printing interval between the one data and the other data, and a detection means for detecting the end of one data introduced into the first data buffer, the first data The data introduced into the buffer is output to the printer to print one of the variable length data, and when the detection means detects the end of one of the data, a space code corresponding to the printing interval set in the interval register is output. is output to the printer and a predetermined interval is provided after printing of the one variable length data, and then the other data of the second data buffer is output to the printer and printed. .