JPS6144466A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPS6144466A JPS6144466A JP16514385A JP16514385A JPS6144466A JP S6144466 A JPS6144466 A JP S6144466A JP 16514385 A JP16514385 A JP 16514385A JP 16514385 A JP16514385 A JP 16514385A JP S6144466 A JPS6144466 A JP S6144466A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- impurity concentration
- region
- substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000003990 capacitor Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 5
- 230000001419 dependent effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 235000021190 leftovers Nutrition 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はオフセットゲート構造のＭＯＳ型半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a MOS type semiconductor device with an offset gate structure.
従来の技術
ＭＯＳ型トランジスタは、周知のように、ドレイン・ソ
ース間電流（Ｉ ｏｎ ）のドレイン・ソース間電圧（
Ｖｏ＠）依存性をもっている。第４図は、ゲート電圧（
Ｖ、、）一定としたときのＶ□−工。。As is well known, in conventional MOS transistors, the drain-source voltage (I on ) of the drain-source current (I on ) is
Vo@) has dependence. Figure 4 shows the gate voltage (
V,,) V□-k when it is constant. .
特性図であり、特性曲線ムが従来例である。このような
ドレイン・ソース間電流のドレイン・ソース間電圧依存
性は、ドレイン電圧に依存して、ドレイン領域からチャ
ンネル領域へ拡がる空乏層幅が変化し、これによる実効
的チャンネル長の変動、いわゆる、チャンネル長変調に
起因するもので８る。そして、このドレイン・ソース間
電流のドレイン・ソース間電圧依存性は、ＭＯＳ型トラ
ンジスタを電荷転送用のスイッチング素子として利用す
るパケット・ブリゲート・デバイス（以下、ＢＢＤと略
す）の場合に、転送電荷の取り残しを生む要因、すなわ
ち、不完全転送効率（αＤ ）を太き（することになる
。This is a characteristic diagram, and the characteristic curve M is a conventional example. This dependence of the drain-source current on the drain-source voltage is caused by the fact that the width of the depletion layer extending from the drain region to the channel region changes depending on the drain voltage, resulting in a variation in the effective channel length, so-called. This is due to channel length modulation. The drain-source voltage dependence of this drain-source current can be seen in the case of a packet brigade device (hereinafter abbreviated as BBD) that uses a MOS transistor as a switching element for charge transfer. This increases the factor that causes leftovers, that is, the incomplete transfer efficiency (αD).
発明が解決しようとする問題点
ところで、ＭＯＳ型トランジスタにみられるチャンネル
長変調の現象は、チャンネル長が短くなるほど顕著にな
り、ＢＢＤでは、高密度化の障害になる。Problems to be Solved by the Invention Incidentally, the phenomenon of channel length modulation observed in MOS transistors becomes more pronounced as the channel length becomes shorter, and becomes an obstacle to high density in BBDs.
また、ＭＯＳ型トランジスタのチャンネル長変調は、オ
フセットゲート構造ＭＯＳ型トランジスタで、そのオフ
セットゲート部分のドレイン領域を低不純物濃度化する
ことによっても、付随的には抑制される。すなわち、ド
レイン領域の低不純物濃度化により、ドレイン電圧に依
存して拡がる空乏層が低濃度ドレイン領域にも分配され
て、チャンネル領域へ拡がる空乏層幅を抑える効果がる
る。しかしながら、ドレイン領域の不純物濃度を低減し
ても、接合域での空乏層幅がチャンネル領域側で大きく
、かつ、支配的である限り、チャンネル長変調の抑制効
果にも限界があり、大きな効果は期待できない。In addition, the channel length modulation of a MOS transistor is also suppressed by lowering the impurity concentration in the drain region of the offset gate portion of the MOS transistor with an offset gate structure. That is, by lowering the impurity concentration in the drain region, the depletion layer that expands depending on the drain voltage is distributed to the lightly doped drain region, which has the effect of suppressing the width of the depletion layer expanding toward the channel region. However, even if the impurity concentration in the drain region is reduced, as long as the depletion layer width in the junction region is large and dominant on the channel region side, there is a limit to the effect of suppressing channel length modulation. I can't wait.
問題点を解決するだめの手段
本発明は、ゲート電極とドレイン領域との間にオフセッ
トゲート構造部をそなえ、前記オフセットゲート構造部
の基板不純物濃度を前記ゲート電極下の反対導電型基板
領域の不純物濃度と同等、もしくはそれより低濃度にな
したＭＯ３型半導体装置であり、これによって、上述の
問題点を解決するものである。Means for Solving the Problems The present invention provides an offset gate structure between a gate electrode and a drain region, and adjusts the substrate impurity concentration of the offset gate structure to that of an opposite conductivity type substrate region under the gate electrode. This is an MO3 type semiconductor device with a concentration equal to or lower than that of the present invention, and thereby solves the above-mentioned problems.
作用
本発明によると、オフセットゲート構造部に延在する実
効ドレイン領域の不純物濃度を、ゲート電極下の反対導
電型基板領域の不純物濃度と同等、もしくはそれより低
濃度になしたことによって、ドレイン電圧に依存して拡
がる空乏層が、チャンネル領域側よりも、低濃度の実効
ドレイン領域内に大きくなり、したがって、ドレイン電
圧依存のチャンネル長変調を格段に抑制することができ
る。According to the present invention, by making the impurity concentration of the effective drain region extending in the offset gate structure equal to or lower than the impurity concentration of the opposite conductivity type substrate region under the gate electrode, the drain voltage can be increased. The depletion layer, which expands depending on the voltage, becomes larger in the low-concentration effective drain region than in the channel region side, and therefore, drain voltage-dependent channel length modulation can be significantly suppressed.
実施例
第１図は、本発明実施例のオフセットゲート構造Ｍ Ｏ
Ｓｆｉ トランジスタを電荷転送用スイッチング素子と
するＢＢＤの断面構造およびその駆動方式を概説するた
めの駆動結線図である。Embodiment FIG. 1 shows an offset gate structure M O of an embodiment of the present invention.
FIG. 2 is a drive connection diagram outlining the cross-sectional structure and drive method of a BBD using an Sfi transistor as a charge transfer switching element.
ＢＢＤは周知のように、同一基板上に配置はれたＭＯＳ
型トランジスタのゲートとドレイン間に１！荷蓄積容量
を形成し、そｎぞれのＭＯＳ型トランジスタのソースと
ドレインを順次直列縦続接続し、一つおきのＭＯＳ型ト
ランジスタのゲートをそれぞれ連結した構造を有してお
り、二相の互いに逆位相のクロックによって連続的に電
荷転送を行なう。As is well-known, BBD is a MOS transistor arranged on the same substrate.
1 between the gate and drain of the type transistor! It has a structure in which the sources and drains of each MOS transistor are successively connected in series to form a load storage capacitor, and the gates of every other MOS transistor are connected to each other. Charge transfer is performed continuously using clocks with opposite phases.
この図で、単位のＭＯＳ型トランジスタは、第１ゲート
電極１＆と第２ゲート電極２＆とを持っニゲート電極構
造、いわゆる、四極構造であり、ＭＯＳ型電荷蓄積容量
が第１ゲート電極１＆と第２ゲート電極２龜との間に配
置され、その一方の電極３ａが第１ゲート電極１亀に接
続されている。In this figure, the unit MOS type transistor has a two-gate electrode structure, a so-called quadrupole structure, having a first gate electrode 1& and a second gate electrode 2&, and a MOS type charge storage capacitor has a first gate electrode 1& and a second gate electrode 2&. One of the electrodes 3a is connected to the first gate electrode 1.
また、基板側の各領域は、アクセプタ不純物濃度が約１
０１”〜１０１６原子／ＣノのＰ−基板４０表面部分に
、ドナー不純物濃度か約１０１４〜１０１６原子／ｄの
第１Ｎ−領域６＆、第２「領域６＆および第３Ｎ−領域
７１Ｌを配設し、ＭＯＳ型電荷蓄積容量部分には高濃度
Ｎ１域８亀を設け、さらに、基板表面には絶縁膜（通常
、５ｉ（ｈ）９をそなえている。なお、図中の各構成部
分の符号１〜８に付した添字ａ、ｌ）は、それぞれ、各
単位の電荷転送素子を区分するためのものである。In addition, each region on the substrate side has an acceptor impurity concentration of about 1
A first N-region 6&, a second N-region 6&, and a third N-region 71L having a donor impurity concentration of approximately 1014 to 1016 atoms/d are provided on the surface portion of the P-substrate 40 having a donor impurity concentration of approximately 1014 to 1016 atoms/d. , a high concentration N1 region 8 is provided in the MOS type charge storage capacitor part, and an insulating film (usually 5i(h) 9) is provided on the substrate surface. The subscripts a and l) attached to 8 are for classifying each unit of charge transfer element.
このＢＢＤの駆動方式は、第１のクロック信号ｇ９に−
の単位の第１ゲート電極１１ＬおよびＭＯ３Ｏ３型電荷
蓄積容量極３＆を接続し、第２のクロック信号源１０に
次の単位の第１ゲート電極１ｂおよびＭＯ３型電荷蓄積
容量の電極３ｂを接続し、さらに直流電＃Ｘ１１を各単
位の第２ゲート電極２＆、・・・２ｎに接続して、順次
、電荷転送動作を行うものである。This BBD driving method is based on the first clock signal g9.
The first gate electrode 11L of the next unit and the MO3O3 type charge storage capacitor electrode 3& are connected, the first gate electrode 1b of the next unit and the MO3 type charge storage capacitor electrode 3b are connected to the second clock signal source 10, Further, a DC current #X11 is connected to the second gate electrodes 2&, . . . 2n of each unit, and a charge transfer operation is performed sequentially.
ここで、チャンネル長変調の程度について説明する。ま
ず、チャンネル基板部分のＰ形不純物（アクセプタ）ｍ
度をＮム、ドレイン拡散領域のＮ形不純物（ドナー）′
ａ度をＮＤ、 Ｐ形基板に拡がる空乏層幅をＷｐ、 Ｎ
形拡散領域内に拡がる空乏層幅をＷｎとし、Ｎ、をろる
一定値とした場合の、Ｗ、、Ｗ。Here, the degree of channel length modulation will be explained. First, P-type impurity (acceptor) m in the channel substrate part
N type impurity (donor) in the drain diffusion region
The degree a is ND, the width of the depletion layer spreading in the P type substrate is Wp, N
W, , W, where Wn is the width of the depletion layer extending within the shaped diffusion region, and N is a constant value.
のＮＤ／Ｎ、依存性は第８図のようになる。同図による
と Ｎ６ ／”Ａ≧１０’Ｃ１時１７）上記空乏層［Ｗ
ｐ＝ ”＋を基準とした場合、ＮＤ／Ｎ、＝ １０では
Ｎｐ−０９４、Ｎ、／Ｎ、＝ １ではＷ ｐ 鴇ｏ−７
、ＮＤ／Ｎ−０，１ではＷｐ亀０．３ 、Ｎｏ ／Ｎム
＝ｏ、ｏｉではＷｐ；０．１となる。したかって、Ｎゎ
がＮえの１０倍以上の高い不純物濃度の場合は、Ｗｐの
減少の度合が非常に小さく、ＨＤをＮ。The ND/N dependence of is shown in FIG. According to the same figure, when N6/”A≧10’C1 17) The above depletion layer [W
When p = ``+'' is the standard, ND/N, = 10 is Np-094, N, /N, = 1 is W p o-7
, ND/N-0,1, Wp=0.3, and No/N=o, oi, Wp;0.1. Therefore, when the impurity concentration of N is 10 times higher than that of N, the degree of decrease in Wp is very small, and HD is reduced to N.
と同程度もしくはそれ以下にした場合は、Ｎｐは著しく
減少される。すなわち、ＮＤをＮ、と同程度もしくはそ
れ以下にすれば、チャンネル部に拡がる空乏層幅が抑制
され、チャンネル長変調が著しく減少し、かくして、α
Ｄが大幅に改善されることを意味し、ている。If the value is equal to or lower than , Np will be significantly reduced. In other words, if ND is made equal to or less than N, the width of the depletion layer expanding in the channel region is suppressed, and the channel length modulation is significantly reduced.
This means that D is significantly improved.
第３図は、Ｐ形高抵抗の基板として、アクセプタ不純物
濃度が１０Ｉｓ原子／ｉ未満の、いわゆる、（Ｐ−）基
板４′を用いて、これに、第１図と同様の各Ｎ−領域Ｓ
Ｌ、８１Ｌ、Ｔ＆Ｉ７ｂ 、ＢＬ、８ｂを形成するとと
もに、第１ゲート電極および第２ゲート電極のそれぞれ
の直下の基板表面には、Ｐ形不純物を約１０１’〜１０
１６原子／ｄの範囲で導入量を制御したＰ−領域１３を
設けたものである。In FIG. 3, a so-called (P-) substrate 4' with an acceptor impurity concentration of less than 10 Is atoms/i is used as a P-type high-resistance substrate, and each N- region similar to that in FIG. S
L, 81L, T&I7b, BL, 8b are formed, and P-type impurities are added to the substrate surface directly under each of the first gate electrode and the second gate electrode at approximately 101' to 10.
A P- region 13 is provided, the amount of which is introduced is controlled within the range of 16 atoms/d.
各電極構成ならびに駆動方式は、第１図示の実施例装置
と同じである。この構造によると、Ｐ形基板に一段と高
抵抗の（Ｐ−）基板４′を用いているために、各Ｈ−領
域形成のだめのＮ形不純物低濃度拡散工程で、同不純物
濃度を精度よく制御して導入することができ、したがっ
て、Ｎ、／Ｎムを第１図に示すものの場合より、ざらに
精度よく、安定して、一段と好ましい小さな値にするこ
とができる。The configuration of each electrode and the driving method are the same as those of the embodiment shown in the first figure. According to this structure, since the (P-) substrate 4', which has a higher resistance than the P-type substrate, is used, the impurity concentration can be precisely controlled in the low-concentration N-type impurity diffusion step before forming each H- region. Therefore, N,/N can be set to a more preferable small value with greater precision and stability than in the case shown in FIG.
なお、第４図のＶＤ、−Ｘ。、特性図中の特性曲線Ｂは
、本発明の実施例装置の場合の典型的特性を示し、従来
例の特性曲線人とくらべて明らかなように、ドレイン・
ソース間電流（ＩＤＩＩ ）のドレイン・ソース間電圧
（Ｖｏｗ）に対する依存性が小さく、したがって、本発
明実施例のＭＯＳ型トランジスタはチャンネル長変調の
微小なものが実現される。In addition, VD, -X in FIG. , Characteristic curve B in the characteristic diagram shows the typical characteristics of the device according to the embodiment of the present invention, and as is clear from the characteristic curve of the conventional example, the drain
The dependence of the source-to-source current (IDII) on the drain-to-source voltage (Vow) is small, so that the MOS transistor of the embodiment of the present invention can achieve minute channel length modulation.
以上の実施例では、ＮチャンネルＭＯＳ型トランジスタ
を用いたＢＢＤについて説明を行なったが、Ｐチャンネ
ルＭＯＳトランジスタを用いたＢＢＤでも同様な効果が
得られること社明らかである。In the above embodiments, a BBD using an N-channel MOS transistor has been described, but it is obvious that a similar effect can be obtained with a BBD using a P-channel MOS transistor.
また、三極構造ＢＢＤや四極構造ＢＢＤのみならず、そ
の他のαＤを改善する方法といっしょに用いることによ
り、いっそう効果を発揮する。Further, the effect can be further exhibited by using not only the triode structure BBD and the quadrupole structure BBD but also other methods for improving αD.
発明の効果
本発明によると、ゲート電極とドレイン領域との間のオ
フセットゲート構造部における基板領域、すなわち、同
オフセットゲート構造部下に延在する低濃度ドレイン領
域の不純物濃度を、ゲート電極下の反対導電型基板領域
、すなわち、チャンネル領域の不純物濃度と同等、もし
くはそれより低濃度になしたことによって、ＭＯＳ型半
導体装置のドレイン電圧に依存して生じるドレイン領域
・チャンネル領域間接合の空乏層幅が、チャンネル領域
側よりも、ドレイン領域内で大きくなり、また、ドレイ
ン電圧の変動に応じて、同空乏層幅が変動する場合も、
チャンネル領域内での空乏層幅の変動がきわめて小さく
抑えられるという格別や効果を奏し、ＭＯ３型半導体装
置の動作安定化に大きく寄与することができる。Effects of the Invention According to the present invention, the impurity concentration of the substrate region in the offset gate structure between the gate electrode and the drain region, that is, the low concentration drain region extending under the offset gate structure, is reduced to By making the impurity concentration equal to or lower than that of the conductive substrate region, that is, the channel region, the width of the depletion layer at the junction between the drain region and the channel region, which occurs depending on the drain voltage of the MOS semiconductor device, can be reduced. , is larger in the drain region than in the channel region, and the width of the depletion layer changes depending on the fluctuation of the drain voltage.
This has the special effect of suppressing fluctuations in the width of the depletion layer within the channel region to an extremely small level, and can greatly contribute to stabilizing the operation of the MO3 type semiconductor device.
第１図は本発明適用の実施例ＢＥＤの断面図壱４０口菰
客；、第２図は接合空乏層幅のドナー（ＮＯ）／アクセ
プタ（Ｎ＾）比に対する依存性特性図、第３図は本発明
適用の他の実施例ＢＢＤの断面図す駆増＃＃；、第４図
はドレイン・ソース間電流（工ゎＳ）−ドレイン・ソー
ス間電圧（Ｖ□）特性図で８る。
１ａ、１ｂ・・・・・・第１ゲート電極、２＆ ｌ ２
ｎ・・・・第２ゲート電極、３ａ、３ｂ・・・・・・Ｍ
Ｏ３型電荷蓄積用容量電極、４・・・・・・Ｐ−基板、
１５１Ｌ 、 ８＆ １γ＆、７ｂ・・・・・・Ｎ−領
域、ａａ 、 ａｂ・・・・・・Ｎ＋領領域９・・・・
・・絶縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
第 ３ 図
第 ４ 図
ｏｓFig. 1 is a cross-sectional view of a BED according to an embodiment of the present invention; Fig. 2 is a characteristic diagram of the dependence of the junction depletion layer width on the donor (NO)/acceptor (N^) ratio; Fig. 3 4 is a cross-sectional view of a BBD according to another embodiment of the present invention, and FIG. 4 is a drain-source current (S) vs. drain-source voltage (V□) characteristic diagram. 1a, 1b...first gate electrode, 2 & l 2
n...Second gate electrode, 3a, 3b...M
O3 type charge storage capacitor electrode, 4...P-substrate,
151L, 8&1γ&, 7b...N- region, aa, ab...N+ region 9...
...Insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 Figure os
Claims (2)
ート構造部をそなえ、前記オフセットゲート構造部の基
板領域不純物濃度を前記ゲート電極下の反対導電型基板
領域の不純物濃度と同等、もしくはそれより低濃度にな
したＭＯＳ型半導体装置。(1) An offset gate structure is provided between the gate electrode and the drain region, and the impurity concentration of the substrate region of the offset gate structure is equal to or lower than the impurity concentration of the substrate region of the opposite conductivity type under the gate electrode. MOS type semiconductor device with high concentration.
１０＾１＾４〜１０＾１＾６原子／ｃｍ＾３およびゲー
ト電極下の反対導電型基板領域の不純物濃度が１０＾１
＾５〜１０＾１＾６原子／ｃｍ＾３に、それぞれ、選定
された特許請求の範囲第１項記載のＭＯＳ型半導体装置
。(2) The impurity concentration in the substrate region of the offset gate structure is 10^1^4 to 10^1^6 atoms/cm^3 and the impurity concentration in the substrate region of the opposite conductivity type under the gate electrode is 10^1.
The MOS type semiconductor device according to claim 1, in which the atoms are selected to be ^5 to 10^1^6 atoms/cm^3, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16514385A JPS6144466A (en) | 1985-07-26 | 1985-07-26 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16514385A JPS6144466A (en) | 1985-07-26 | 1985-07-26 | Mos type semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18089181A Division JPS5882567A (en) | 1981-11-10 | 1981-11-10 | Charge transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6144466A true JPS6144466A (en) | 1986-03-04 |
Family
ID=15806705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16514385A Pending JPS6144466A (en) | 1985-07-26 | 1985-07-26 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6144466A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917978A (en) * | 1972-04-10 | 1974-02-16 | ||
| JPS5289475A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Four electrodes fet transistor |
| JPS5882567A (en) * | 1981-11-10 | 1983-05-18 | Matsushita Electronics Corp | Charge transfer device |
-
1985
- 1985-07-26 JP JP16514385A patent/JPS6144466A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917978A (en) * | 1972-04-10 | 1974-02-16 | ||
| JPS5289475A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Four electrodes fet transistor |
| JPS5882567A (en) * | 1981-11-10 | 1983-05-18 | Matsushita Electronics Corp | Charge transfer device |
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