JPS6144338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information classification system, and more particularly to an information classification system that uses an associative memory to classify a plurality of records according to the size of the contents of designated data portions.

Many information classification methods have been proposed in the past, and the address calculation method is known as a method that allows high-speed processing on a memory such as a main memory to which fixed addresses are allocated. Literature (1 Flores, translated by Tomoaki Sekine, “Computer Sorting,” Science Publishing, 1972,
As detailed in PP89-101), this classification method stores records to be classified in memory addresses that correspond one-to-one to the pattern of the data part of interest (hereinafter referred to as key). It is characterized by being classified by

For example, as the simplest example, the principle will be explained using a method in which a key pattern is directly interpreted as a memory address. When the key pattern of record A is "10101", the corresponding memory address is set to "10101" and record A is stored at that address. Next, when the key pattern of record B is set to "10110", record B is stored at address "10110" in the same manner as above. As a result, record B is stored at a memory address older than record A, and the records are sorted in ascending order with respect to the key of interest.

Above, we have explained the principle of the classification method shown in the above literature, but the size of the key pattern is usually large and there are many
It is not uncommon for it to be 10 bytes. Therefore, if a key pattern is interpreted as a memory address as it is, an extremely large amount of memory must be prepared, which is impractical. Therefore, several address calculation methods have been considered that enable processing similar to the above using a practical-scale memory.

For example, a method of using the upper m bytes (l>m) of an l-byte key pattern as an address is also an example of the above calculation method.

Since these address calculation methods convert a key pattern into an address pattern of relatively small size, a so-called collision phenomenon occurs in which a plurality of different key patterns are associated with the same address. When a collision occurs, it is necessary to carry out rearrangement operations while considering the free space before and after the address and comparing the key values of the multiple records that have collided with each other. FIG. 6 shows an example of rearrangement due to collision when the key value is used as the dividend and the quotient obtained by division is used as the address.

Although the operating procedure is detailed in the above-mentioned document, since the operation requires a large amount of time, the use of an address translation method with fewer collision phenomena is an important condition for improving the efficiency of the classification method.

On the other hand, the characteristics of the key pattern to be classified are:
This differs depending on the case, and an efficient address translation method with fewer collisions has not yet been discovered in all cases, which is the reason why the above-mentioned classification method is not so popular.

By the way, conventionally, all elements in a storage device are queried by giving specific information.
An associative memory device is used that finds a location where there is a certain relationship (for example, match, large, small, etc.) between stored content and query information and reads out the stored content. The basic 1-bit operation of an associative memory device is as shown in FIG. , the location of the memory M storing the same information is detected by providing search information from the outside. As shown in Figure 1b, for example, if there is a memory of 5 words x n digits, when search SK is performed on 4 bits of the n digits, the 5 words of memory will simultaneously detect matches and mismatches. I do. In this case, all of the four bits of address AD4 match, so a match signal C is output, and the address position is sent to the outside as information, or as shown in Figure 1b, there is a match signal C. The information f _d is extracted as output. In this way, in an associative memory device, multiple word memories can perform search operations in parallel.

The purpose of the invention is to eliminate the drawbacks of the prior art:
To provide an information classification method that can perform record arrangement operations at high speed when a plurality of key patterns are assigned to the same address when converting a record key pattern into a small-sized address pattern.

Hereinafter, the principle and embodiments of the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing the principle of the information classification method according to the present invention.

FIG. 2a shows the principle of memory address calculation, and FIG. 2b explains the method of storing records in memory.

Key pattern of record RCD to be classified
KY is sent as the dividend A to the division circuit DVD, divided by a certain divisor to obtain a quotient, and the obtained quotient is used as a memory address, and the target record is stored at that address. For example, the key pattern for record 1 is 260, and the key pattern for record k is 280.
If the divisor of the division circuit DVD is 50, then the memory address of record 1 and the memory address of record k will both be address 5.

The memory that stores records can store multiple records per address, and the area that stores records is called the entry area EA.
First entry area from left to right in the diagram
Numbers are assigned as NO.1EA, second entry area NO.2EA, and third entry area NO.3EA. Due to the above-mentioned collision phenomenon, the same memory address
When multiple records are associated with the address (HSHAD) (in the example in Figure 2, recordl and recordk
are associated with the same address "5"),
Rearrange the record so that the record with the smaller key pattern is in the smaller entry area. Unlike the prior art example shown in FIG. 6, the purpose of making it possible to store multiple records at one address is that if multiple records with the same address occur due to a collision,
This is to limit the rearrangement operation to the range of the entry area of the address in question and to prevent wide-ranging rearrangement as shown in FIG. If the number of collisions is large and the entry area is insufficient, allocate one address for overflow from the overflow area OVFA prepared in advance, and perform the same rearrangement operation as above for the expanded entry area as shown by the arrow OVF. do. Note that the overflow pointer OVFP indicates whether the overflow area is used or not, and the entry counter ECT indicates the number of records entered at that address.

When all the target records are stored in the memory in the format shown in Figure 2 by the above procedure, the records for the key of interest are moved from the lowest numbered address to the highest numbered address, and within the same address, from the lowest numbered entry area to the oldest numbered address. They are sorted in ascending order in the direction of the number entry area. After the series of operations described above, the focus is automatically read from the memory from the lowest address to the highest address, or within the same address from the lowest entry area to the highest entry area. You can obtain a sequence of records sorted in ascending order with respect to the key.

In FIG. 2, the principle of the present invention was explained using the division method as a method of converting a key pattern into an address pattern. It is also possible to use any conversion method that allows correspondence to a predetermined address order without at least reversing the magnitude relationship between them.

Next, FIG. 3 shows the configuration of an embodiment of an associative memory device which forms the core of the present invention. Reference numeral 1 denotes a memory unit that stores a hash table having the structure shown in FIG. A sequence control circuit decodes and transmits necessary control signals to the associative processing unit 2 via line 5; 8 is a data register for temporarily storing data sent by the processor or data read from memory 1; 12 is a data register sent by the processor; This is an address register that holds address data of memory 1.

Memory 1 address is page PAD, row
RWAD and column CLMAD, the hash address HSHAD in FIG. 2b is associated with the page address PAD, and the entry area number EA within the hash address is associated with the row address RWAD. Also, in address register 12, register 1
2-1 is page address PAD, 12-2 is row address RWAD, 12-3 is column address
Set CLMAD.

One record RCD is stored in one row, and write and read operations for each row are sequential column-by-column operations. Also the page address
PAD and row address RWAD can be accessed randomly, and the page address space is usually area 1.
-1 and an overflow area 1-2. In the present invention, since processing related to storing one record is limited to a specific address,
It is sufficient to prepare a number corresponding to one page, that is, the number of row addresses per page.

Next, the operation of the present invention will be explained with reference to FIG.
Note that the page management function is located in the CPU, and it is assumed that the CPU knows how many records are stored in each page, which pages in the overflow area are empty, etc. After converting the focused key part of the record to be processed into a hash address HSHAD using the method described above, the processor CPU converts the focused key part of the record to be processed into a hash address HSHAD, and then converts the key part of the focused key part at the address in the associative memory to a value larger than that of the record to be processed. Executes a search operation to determine whether a record has already been stored. As a result of the search, if a record with a large value for the key of interest is not detected, the target record is stored at the lowest row address among the unused row addresses. If a record with a large value for the key of interest is detected, a row address at which the target record should be stored is automatically prepared by a parallel shift means, which will be described later.

Below, the search operation will be explained first.

The processor CPU sends a search command to the sequence control circuit 3 via line 4, and at the same time sends search data to the data register 8 via line 9.
, the address in memory 1 to be searched is written on line 1
1 to address register 12 via . Among the addresses set in address register 12, in this case page address 12-1
The column address CLMAD of PAD 12-3 is valid, and all rows are selected regardless of the contents of row address 12-2. The sequence control circuit 3 instructs all associative processing units 2 via line 5 to read out a predetermined column address CLMAD;
Instructs a comparison operation between the search data set in the data register 8 and the read data.

After reading data from a designated column, each associative processing unit 2 performs a comparison operation with the contents set in the data register 8 and holds the result. The above operation is repeatedly executed for all data of the target key section. the result,
The associative processing unit 2-i that has detected the search condition, ie, the condition that the stored value is large, sets the internal search condition detection flip-flop to "1" and at the same time outputs its state to the search condition 6-i. When the search condition is satisfied in any of the associative processing units 2, that state is notified to the processor via line 7.

The processor CPU checks the status of line 7 and
If the search condition is not met, it is determined that the target record has the largest key value at the relevant hash address HSHAD, and the record is stored in the row with the lowest address among the unused row addresses RWAD. do. That is, first, the processor CPU sends write command A/WTCMD to line 4.
At the same time, the data for the first column is sent to the data register 8 via line 9, and the page address PAD and row address where the data should be stored are sent to the sequence control circuit 3 via line 9.
RWAD, column address CLMAD on line 11
to the address register 12 via the address register 12.

The sequence control circuit 3 instructs each associative processing unit 2 to perform a write operation. The value of the corresponding row address RWAD is fixedly set in advance in each associative processing unit 2, and only the associative processing unit 2-i having the same address as the row address RWAD sent via line 14 actually writes. The operation is executed and the data set in data register 8 is transferred to the specified column address.
Stored in CLMAD. The above operations are repeated until all data of the target record is stored.

On the other hand, if the matching condition is detected via line 7, the processor CPU determines that it is necessary to insert the record of interest at an appropriate position, and assigns a row that satisfies the search condition to associative memory 1.
At the same time, the contents of RW are moved to the lower address, and an operation is executed to secure an area for storing a new record.

Next, the parallel shift function and automatic record storage position detection function, which are the features of this associative memory, will be explained.

That is, first, the processor sends a shift command to the sequence control circuit 3 via line 4, and at the same time sets the first column address CLMAD of the record to be shifted in the address register 12 via line 11. The sequence control circuit 3 instructs each associative processing unit 2 to perform a shift operation via a line 5. Each associative processing unit 2 reads data from a designated column address CLMAD and holds it in an internal buffer. Next, the associative processing unit 2-i, which has received via line 15-i that the higher-level associative processing unit 2-(i-1) has detected the search condition, sends the message via line 16-i. Upper associative processing unit 2-
The data held in the buffer in (i-1) is read and rewritten to the specified column address CLMAD. On the other hand, the upper associative processing unit 2-
The associative processing unit 2-j, which has received via line 15-j that (j-1) has not detected the search condition, transfers the data held in its own buffer to the specified column address CLMAD. Rewrite to. By repeating the above operations until the processing of all data constituting a record is completed, the contents of a plurality of rows in which search conditions have been detected can be transferred in parallel to the row one address lower.

After completing the above shift operation, the processor
The CPU inserts a new record into the reserved area. That is, the processor CPU sends a write command B/WTCMD to the sequence control circuit 3 via line 4 in order to write a record to the lowest numbered row whose search condition detection flip-flop is set to "1". . At this time, data is transferred to data register 8 via line 9, and the column address CLMAD where the data should be stored is line 1.
1 to address register 12.
The sequence control circuit 3 decodes the write command and sends a predetermined control signal to each associative processing unit 2 via the line 5. Then, the associative processing unit 2-i with the lowest number whose search condition detection flip-flop is set to "1", that is, its own search condition detection flip-flop, becomes "1".
and the associative processing unit 2-i receives via 15-i that the search condition detection flip-flop of the upper associative processing unit 2-(i-1) is "0". Write the data held in data register 8 to the column address.

The above operation is repeated while incrementing the column address CLMAD until all the data making up the record is written.

The above explanation is the focus address
Regarding the case where there is a free entry area EA in HSHAD, if records have already been stored in all entry areas EA, the processor CPU uses a search command to check if there is a record with a key greater than the value of the key of interest. If the overflow address OVFA does not exist, the above operation is performed for the overflow address OVFA. On the other hand, if the record exists, the record stored in the oldest row is read and saved prior to the shift operation, and then the series of operations necessary for inserting the new record described above are performed. Next, use the saved record as a new record to be processed.
The series of operations described above regarding the overflow page address is performed.

Next, the unit configuration and operation of the associative processing unit 2 will be explained with reference to FIG.

20 is an input/output switching circuit that controls data input/output to the data bus 10; 21 is a processor;
A search circuit 22 compares and determines the data transferred by the CPU and the data read from the row, a write data selection circuit 23 selects the data to be written to the row, and 23 the write data sent from the sequence control circuit 3. an access gate circuit 24 that controls whether the read control signal 5-5 is enabled or disabled;
25 is a buffer that temporarily holds the data read from the row, and 25 is the preset number of the associative processing unit (the connected row address RWAD).
) 26 and the row address sent via line 12-2 from sequence control circuit 3.
This is a match detection circuit that detects a match with RWAD.

5-1 to 5-6 are control signal lines sent from the sequence control circuit 3 to define the operation of the associative processing unit 2. 5-1 is a signal line that specifies whether to input data on the bus 10 or output data on the bus 10; 5-2 is an input/output switching circuit 20 or an access gate 23;
A signal line that specifies the conditions for the function to be enabled.

That is, depending on the state of the output 32 of the match detection circuit 25, or the state of the output 31 of the search condition detection flip-flop in the search circuit 21 and the output 15-i of the search condition detection flip-flop of the upper associative processing unit. Specify whether to apply the same or to make it unconditionally valid.

5-3 sets the data read from the low level into the buffer 24, and at the same time sets the data read from the data register 8.
This is a timing signal line that executes a comparison/judgment operation between the data set in the row and the data read from the row.

5-4 is a signal line that specifies the write operation mode; 5-5 is a write/read control signal line that instructs execution of write operation and read operation for low; and 5-6 is a search condition detection in the search circuit 21. This is the flip-flop reset signal line.

Next, the operation of each part in response to a command will be explained. First, in the case of a search command, the sequence control circuit 3 designates the input of data on the bus 10 through the signal line 5-1 to be unconditionally valid through the signal line 5-2. As a result, the search data transferred from the processor CPU is transferred to the bus 10 and the input/output switching circuit 2.
0 to bus 27. On the other hand, the read control signal designated by the signal line 5-5 is
Under the unconditionally valid condition of the signal line 5-2, data is sent to the memory via the access gate 23 and the line 17-3, and a read operation of data is executed from the specified column address CLMAD of the corresponding row. The read data is sent to the search circuit 21 via the line 17-1, and a comparison/judgment operation is executed by a timing signal sent at a predetermined time via the signal line 5-3. The above operations are repeated while incrementing the column address CLMAD until the last data of the key part of interest is reached, and it is detected that the key pattern has a value greater than the search condition, that is, the value of the key pattern specified by the processor. If so, the search condition detection flip-flop of the search circuit 21 is set to "1" and its output is output to line 6-i.

FIG. 5 shows the configuration of the search circuit 21.

The search data specified by the processor CPU is sent to the comparator 40 via the line 27, while the data read from the row is sent to the comparator 40 via the line 17-1.
When the value of the data sent via line 27 is large, line 41 becomes "1", line 17-1
4 if the value of the data sent via is large
2 becomes "1". Prior to executing the search operation, the processor CPU is instructed to perform a reset operation via line 4 in FIG. This causes the sequence control circuit 3 to send a reset signal via lines 5-6 to the two flip-flops 45 and 45 of FIG.
46. Flip-flop 46 is the aforementioned search condition detection flip-flop.

The search operation is based on the MSD (Most
Significant Digit) is performed on a column-by-column basis, so once a difference in size is detected, the size relationship between the two key patterns to be compared at that point is determined, regardless of the size relationship of the subsequent data. .

Therefore, in FIG. 5, when either flip-flop 45 or 46 is set, its output is connected to lines 47 or 4.
8 to gates 43 and 44, and the contents of flip-flops 45 and 46 are prohibited from being changed based on subsequent comparison results.

In FIG. 4, in the case of write command A/WTCMD, upon receiving the write command from the processor CPU, the sequence control circuit 3 instructs the input of data on the bus 10 through line 5-1 and the line 5-2 through line 5-2. It depends on the condition of 32.
Lines 5-4 respectively indicate writing of data on bus 10. As a result, the associative processing unit that has detected the matching condition by the matching detection circuit 25 transfers the write data to the bus 10, the switching circuit 20,
Line 28, outputs to write data line 17-2 via write data selection circuit 22, and at the same time outputs to line 5
-5 to access the write control signal sent via
It is output to line 17-3 through gate 23, and data is written to the designated address.

In addition, in the case of write command B/WTCMD (this command is issued after a shift command described later and is used to insert a new record into a predetermined row), the sequence control circuit 3 is sent to the bus 10 by line 5-1. The line 5-2 instructs to input the data, the line 5-4 instructs to select the data on the bus 10 depending on the states of the lines 31 and 33. As a result, the search command executed in advance causes the associative processing unit 2-i of the lowest number that detected the search condition, that is, the line 31
The associative processing unit 2-i that satisfies the conditions that the line 33 is "1" and the line 33 is "0" sends the write data to the bus 1.
0, switching circuit 20, line 28, write data selection circuit 22 to output to line 17-2, and at the same time the write control signal sent via line 5-5 is output to line 17 via access gate 23.
-3 and the specified column address
Write data to CLMAD.

Next, in the case of a shift command, the sequence control circuit 3 first instructs unconditional validity on line 5-2, reads it on line 5-5, and sends out a control signal. As a result, all associative processing units 2 output a read control signal to line 17-3 via access gate 23, and read the specified column address.
Data is read from CLMAD and set in buffer 24 by a timing signal sent at a predetermined time via line 5-3.

Next, the sequence control circuit 3 connects the line 3 by line 5-4 while maintaining the state of line 5-2.
The state of line 33 instructs to select the output of 0 or 34 as write data, and at the same time sends a write control signal via line 5-5. As a result, when line 33 is "1", line 34
When the output of line 33 is "0", line 3
Each output of 0 is written to line 1 as write data.
7-2 and is rewritten to the designated column address CLMAD by a write control signal outputted via access gate 23 to line 17-3. Through the series of read and write operations described above, the contents of all rows that satisfy the search conditions are simultaneously transferred to the row at the lowest address. Further, the above operation is repeatedly executed until all the data constituting the record has been transferred.

As explained above, according to the present invention, an associative function that has the function of executing parallel search operation, parallel shift operation, and automatic record storage position detection operation for a plurality of records registered at the same memory address is provided. Since memory is used, it is possible to speed up record rearrangement operations that occur due to collision phenomena when multiple different records are associated with the same address, compared to conventional methods that use memory with standard functions, making it more efficient. Can categorize information well.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the basic operation of an associative memory device, Figure 2
The figure is a conceptual diagram showing the principle of the present invention, Figure 3 is a block diagram of an information classification system showing an embodiment of the present invention, and Figure 4 is a conceptual diagram showing the principle of the present invention.
The figure is a block diagram of the associative processing unit in Figure 3, Figure 5 is a configuration diagram of the search circuit in Figure 4, and Figure 6 is a diagram showing an example of a record rearrangement operation in the event of a collision in the classification method using the number calculation method. It is. WT: Write line, REF: Verification line, WA: Write address, C/N: Match/mismatch signal line, SK: Search word, RCD: Record, KY: Key pattern, A:
Dividend, DVD: Division circuit, HSHAD: Hatsushi・
address, ECT: entry counter,
OVFP: Overflow pointer, OVFA: Overflow area, EA: Entry area, RWAD: Row address, CLMAD: Column address,
PAD: page address, 1: associative memory,
2: Associative processing unit, 3: Sequence control circuit, 8: Data register, 12: Address register, 20: Input/output switching circuit, 21: Search circuit, 22: Write data selection circuit, 23: Access gate circuit , 24: buffer, 25: match detection circuit, 26: associative processing unit number, 40: comparator, 43, 44: AND circuit, 45, 46: flip-flop.

Claims (1)

[Claims] 1. In an associative memory device comprising a memory having a numbered entry area and a parallel search means for simultaneously detecting the contents of a plurality of records stored in the memory, A parallel shift means for simultaneously shifting the record one address at a time, and a storage position detection means for automatically detecting the entry area into which the record is to be inserted are provided. When storing multiple records, including records that have already been stored, from the lowest number to the highest number area when storing at an address in an associative memory obtained using an arbitrary address conversion method that corresponds to a predetermined address order without reversing at least , the data portion is arranged in a predetermined order by the parallel shift means, storage position means, and parallel search means, and all records to be classified are classified in a predetermined order in a storage space of an associative memory. An information classification method characterized by