JPS6144240Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a pitch conversion circuit that changes the pitch of music.

As this type of device, the one shown in FIG. 1 is known. In other words, an analog signal (audio signal) whose band is limited through the low-pass filter 1.
is converted into a digital signal via the A/D converter 2, passed through the clock control circuit 4 to the D/A converter 3, where it is extracted again as an analog signal, and output via the low-pass filter 9. The clock control circuit 4 writes digital signals into the memory 5 at the timing given by the write clock circuit 6, and reads out the stored contents of the memory 5 as digital signals at the timing given by the read clock circuit 7. The low-pass filter 9 has almost removed the clock component. If the frequencies of the clock circuits 6 and 7 are made the same, the pitch of the output audio signal will be the same, but if the frequency of the clock circuit 7 is changed by the variable clock circuit 8, the pitch will change. The pitch P at this time is determined by the ratio of the frequency w of the clock circuit 6 and the frequency of the clock circuit 7, and P= _R /w The relationship between the write frequency, the read frequency, and the pitch P is expressed in a graph. is shown in Figure 2. Here, the input bandwidth is 20 KHz and the pitch variable range is ±1 octave (R = 1/2 to 2). Since the input bandwidth is 20KHz, the writing frequency will be 40KHz (or higher) according to the sampling theorem. Since P= _R /w, the read frequency when P=1/2 is 20 KHz, and the reproduction frequency bandwidth at this time is 10 KHz. When P=1, _R is 40KHz, and the reproduction frequency bandwidth is 20KHz, the same as the input bandwidth.
When P=2, _R is 80KHz and the reproduction frequency bandwidth is 40KHz. However, the human audible range is said to be 10 to 20KHz, so 20KHz
Even if the band ~40KHz can be played, it is meaningless. In other words, when P=2, the input bandwidth only needs to be 10KHz.

When lowering the pitch, the frequency of the read clock is lowered than the frequency of the write clock, so the read speed becomes slower than the write speed, resulting in excess data and is truncated. If you increase the pitch, the reading speed will be faster than the writing speed, so you will run out of data, so you will have to read the same data again to fill in the blanks.

Thus, in the conventional method, when the pitch is increased, the read frequency increases as the increase ratio increases, so the number of times the same data is read again increases, which has the disadvantage of increasing splicing noise (noise caused by mismatch at the joints of waveforms).

The present invention was developed based on the above circumstances, and aims to provide a pitch conversion circuit in which splicing noise is reduced by varying both the write clock and the read clock in opposite directions.

For this purpose, the present invention converts an analog signal into a digital signal, writes it to a memory, reads the signal from the memory, converts it to analog, and outputs it, in which the write clock and read clock to the memory are clocked. The invention is characterized in that it includes a variable clock circuit that varies the pitch of both clocks in opposite directions.

Hereinafter, one embodiment of the present invention will be explained in detail based on FIGS. 3 to 5. In the figure, reference numerals 1 to 9 indicate the same components as in the description of the conventional example, so the description thereof will be omitted. Among these, in the present invention, the pitch conversion circuit 8 also changes the pitch of the write clock circuit 6. A specific example of the variable pitch circuit 8 is shown in FIG. Here, two sets of volume PT and resistance
Rs, equipped with capacitor CT, clock circuit 6,
7's time constant, control voltage, etc.

In such a configuration, the pitch P is P=
As mentioned above, it is determined by _R /w. Therefore, in this embodiment the frequency of the clock circuit 6 is also controlled. At this time, w, and P
The relationship is as shown in Figure 4. As shown in Figure 5, the oscillation frequency of this circuit is determined by the variable volume RT and capacitor CT, and two series of opposite directions are used to conduct up to half the rotation angle of the volume. By using this, the characteristics shown in FIG. 4 are obtained. Now, in FIG. 4, when P=1/2, the input bandwidth is 20KHz and the reproduction frequency bandwidth is also 10KHz. Also, P
When P = 1, the input bandwidth is 20KHz, but the playback frequency bandwidth is also 20KHz, and when P = 2, the input bandwidth is 10KHz because the writing frequency w drops to 20KHz, and the playback frequency bandwidth is Since the pitch is doubled, it becomes 20KHz. In other words, whether the pitch characteristics of the write clock and read clock are as shown in FIG. 2 or as shown in FIG. 4, the reproduced frequency bands are audibly the same.

In the present invention, as detailed above, both the write and read clocks are variable in opposite directions, resulting in the characteristics shown in Figure 4. When increasing the pitch, the write clock is changed without increasing the read clock frequency. By lowering the frequency, even if the pitch increase ratio becomes high, the number of times the same data is read out again remains the same, and an increase in splicing noise can be suppressed. In addition, since the variable range of the clock can be narrowed, the circuit operation becomes more stable, and it is also possible to use a device with a relatively low upper limit of clock frequency, such as a BBD, for practical purposes. The above effect can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional pitch conversion circuit.
FIG. 2 is a clock characteristic diagram, FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a clock characteristic diagram, and FIG. 5 is a circuit configuration diagram of the main part. 1...Low pass filter, 2...A/D converter, 3...D/A converter, 4...Clock control circuit, 5...Memory, 6, 7...Clock circuit, 8
...Clock variable circuit, 9...Low pass filter, RT...Variable volume, CT...Capacitor,
Rs...Resistance.

Claims (1)

[Scope of utility model registration request] The analog periodic signal is sampled at the input sampling frequency, the data after A/D conversion is written into a storage means such as a memory, and the written data is sequentially read out at the output sampling frequency and D/A converted, and the data is converted to the input sampling frequency. A pitch conversion circuit that performs pitch conversion, compression/expansion of a periodic signal by changing the ratio of the input sampling frequency and the output sampling frequency is characterized in that the pitch conversion circuit is configured to change both the input sampling frequency and the output sampling frequency. pitch conversion circuit.