JPS6143848A - Multiplex signal receiver - Google Patents

Abstract

PURPOSE:To relieve the load to be inflicted on the device of the next order by constituting the titled device with a signal detection circuit, a buffer memory, an address pointer memory, a head address designation memory and a hard cue, receiving a signal string subject to time division multiplex and allowing the next order device to extract a reception signal in the unit of one signal block. CONSTITUTION:A signal detection circuit 12 detects an end signal, which is written in a buffer memory 16 to revise the content of an address pointer memory 17. Then end signal detection information 15 is outputted from the signal detection circuit 12 and the detected end signal and corresponding channel number information 20 are stacked to the hard cue 21. Further, the next order device reads periodically the hard cue 21 to read a channel number whose one signal block is finished, the head address corresponding to the said channel is read from the head address designation memory 19 to confirm the address of the buffer memory 16 in which the head signal of the signal block is stored and the signal block of the channel is read from the buffer memory 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a multiplexed signal receiving apparatus that receives time-division multiplexed signals.

[Prior art]

A conventional multiplexed signal receiving device receives a signal train in which signals of multiple channels are time-division multiplexed in units of significant signals, in which signals of multiple channels constitute a signal block of one channel, in which significant signals each having a meaning in units of one word are consecutive. , a device is known that extracts a significant signal from the signal sequence and notifies the next device. As shown in FIG. 2, this type of device includes a signal detection circuit 2 that detects a significant signal from a time-division multiplexed signal sequence 1, and a signal detection circuit 2 that receives significant signal detection information 3 from the signal detection circuit 2. Hard queue 5 for notifying the next device shown in the figure of the significant 4% in the signal sequence 1 and the corresponding channel number information 4
It was composed of.

However, this type of multiplexed signal receiving device notifies the next device of the received signal via the hard queue 5 not in units of one signal block but in units of one significant signal. In the receiving device, processing is required to edit signal blocks corresponding to channels from the received significant signals, which has the drawback of placing a large burden on the next device.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned drawbacks and to
To provide a multiplexed signal receiving device capable of extracting a received signal in units of signal blocks (one channel).

[Structure of the invention]

The present invention receives a signal train in which signals of a plurality of channels are time-division multiplexed in significant signal units, in which significant signals having meaning in one word unit consecutively constitute one channel signal block, and The device extracts a signal and notifies the next device of the significant signal, and its feature is that each signal block provided in the significant signal indicates the beginning and end of the signal block. A buffer memory that stores detected significant signals divided into areas for each channel, such as a signal detection circuit that detects a start signal, an end signal, and a channel number; and a buffer memory that stores detected significant signals in areas corresponding to the channel numbers. and an address pointer memory indicating an address to store in the channel, and upon receiving the detection information of the first signal from the signal detection circuit, store the address of the packer memory where the first signal is stored in correspondence with the corresponding channel. The device is equipped with a head address instruction memory, and a circuit that receives end signal detection information from the signal detection circuit and notifies the next device of the channel number of the channel whose reception has been completed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multiplexed signal receiving apparatus of the present invention. In this embodiment, the signal detection circuit 12,
It is composed of a buffer memory 16, an address pointer memory 17, a head address instruction memory 19, and a hard queue 21, and receives the time-division multiplexed signal train 11, and a next-order device (not shown) processes the received signal in units of signal blocks. It is designed so that it can be taken out.

Here, the signal detection circuit 12 detects a significant signal from a time-division multiplexed signal train 11 similar to the signal train 1 shown in FIG.
Detecting a start signal indicating the start of the signal block and an end signal indicating the end of the signal block among the significant signals,
Significant signal detection information 16 and leading signal detection information 1, respectively.
4 and end signal detection information 15, and further outputs channel number information 20 indicating which channel. The address pointer memory 17 detects the significant signal detection information 16 and sends the significant signal to the buffer memory 1 in correspondence with the channel.
6 (2) Outputs the address information 18 for storage. The buffer memo! 116 receives the significant signal detection information 16, divides the significant signals in the signal train 11 into areas for each channel according to the address information 18, and stores them. The start address instruction memory 19 receives the start signal detection information 14 and stores address information 18 corresponding to the start signal stored in the buffer memory 16 in correspondence with the channel.The hard queue 21 receives the end signal detection information 15, the channel number information 20 of one signal block (one channel) for which reception has been completed is loaded.

Next (2) The overall operation of this embodiment (2) will be specifically explained.

In FIG. 1, the signal detection circuit 12 (-) detects the leading signal, and by outputting the leading signal detection information 14, the leading address instruction memory 19 stores the output of the address pointer memory 17, that is, the detected leading signal. Address information 18 for writing into the buffer memory 16 is written.At the same time, significant signal detection information 13 is also output from the signal detection circuit 12, and the buffer memory 16 receives the address information 18 based on the address information 18. The contents of the address pointer memory 17 are written to the address pointer memory 17 after the buffer memory 16 is heated.
is updated to the value of the address to fold into. Thereafter, every time the significant signal detection information 16 is output on the same channel (2), the significant signal is written to the buffer memory 16 and the contents of the address pointer memory 17 are updated in the same procedure.Finally, The signal detection circuit 12 detects the end signal (secondly, the end signal is sent to the buffer memory 1
6 to update the contents of the address pointer memory 17. At the same time, (2) the end im number detection information 15 is output from the signal detection circuit 12, and the channel number information 20 corresponding to the detected end signal is loaded into the hard key 21.

Thereafter, in the next-level device (not shown), the 8-docu 21
By periodically reading , the channel number where the l signal block has ended is read, and by reading the start address corresponding to that channel from the start address instruction memory 19, the buffer in which the start signal of the signal block is stored is read. After confirming the address of the memory 16, the signal block of that channel/channel can be successively output from the buffer memory 16.

〔Effect of the invention〕

According to the present invention, as explained above, it is possible to notify the next device (2) of the received signal in units of channel correspondence (2 signal blocks) from the time-division multiplexed signal stream, so that the next device C2, This eliminates the need for processing to edit a signal block from the basic signal of the unit that constitutes the signal block, and therefore has the effect of reducing the burden placed on the next device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiplexed signal receiving apparatus according to the present invention, and FIG. 2 is a block diagram showing a conventional multiplexed signal receiving apparatus. 12...Signal detection circuit, 16...Buffer memory, 17...Address pointer memory, 19...Start address instruction memory, 21...Hard queue. Patent applicant NEC Corporation Representative Patent attorney Uchihara No. 1, Figure 2

Claims (1)

[Claims] Receive a signal train in which signals of a plurality of channels are time-division multiplexed in significant signal units, in which significant signals having meaning in units of one word consecutively constitute one channel signal block, and the signal train In a multiplexing signal receiving device that extracts a significant signal from and notifies a subsequent device of the significant signal, a signal block provided in the significant signal indicates the beginning and end of the signal block for each of the signal blocks. A signal detection circuit that detects a start signal, an end signal, and a channel number; a buffer memory that divides the detected significant signals into areas for each channel and stores them; and a buffer memory that stores the detected significant signals in correspondence with the channel numbers. an address pointer memory indicating an address to store in the first signal;
a start address instruction memory for storing the address of the buffer memory in which the start signal is stored in correspondence with the channel; and receiving end signal detection information from the signal detection circuit;
1. A multiplexed signal receiving device, comprising: a circuit for notifying a next device of the channel number of the channel for which reception has been completed.