JPH04102120A - Demodulator - Google Patents

Abstract

PURPOSE:To segment a variable length code at high speed in a fixed cycle without exerting the influence of time for demodulation upon the code length of the variable length code by providing four storing means. CONSTITUTION:A FIFO 17 inputs the first word of a variable length code data, which is a first data (f) inputted from an input terminal 18, to storing means 11a, 11b, 11c and 11d. In a ring buffer 19, a data including one variable length code at least is extracted by a selecting means 12 from a position shown by a read pointer in the ringularly continued outputs of the four storing means 11a, 11b, 11c and 11d and by detecting the code length at a detecting means 13, the units of the variable length code can be separated by a code separating means 16. At such a time, the selecting means 12 can select the data including the undetected variable length code according to a read pointer (k) even in any cases. Therefore, decoding outputs outputted from a decoding output terminal 20 can be continuously decoded without being interrupted. Thus, the variable length code can be segmented without exerting the influence of time for demodulation upon the code length of the variable length code.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a demodulation device for variable length coding.

Prior Art FIG. 4 shows a block diagram of a conventional demodulator. In FIG. 4, 41 is a shift register that inputs variable length code data one bit at a time using a shift clock and shifts it toward the higher bits, and 42 is a variable length code starting from the most significant bit of the parallel data output from the shift register 41. 43 is a counter that outputs a shift clock corresponding to the code length of the variable length code detected by the detection means 42; 44 is a counter that detects from the most significant bit of the parallel data output from the shift register 41 by the detection means 42; This is a code separating means that separates and outputs data corresponding to the code length of the variable length code.

In the conventional demodulator configured as described above, the code length of the variable length code starting from the most significant bit of the parallel data output from the shift register 41 is detected by the detection means 42 and output to the counter 43 and the code separation means 44. be done.

The counter 43 outputs a shift clock corresponding to the code length detected by the detection means 42 to the shift register 41.

Subsequently, the shift register 41 shifts out the detected variable length code using the shift clock output from the counter 43, and positions the next variable length code from the most significant bit of the parallel data.

On the other hand, the code separation means 44 demodulates variable-length coded data to the coding unit by separating and outputting data corresponding to the code length detected from the parallel data output from the shift register 41. .

Problems to be Solved by the Invention However, in the above configuration, in order to detect a variable length code by shifting the data, it is necessary to shift the data by the number of bits, and all the data to be demodulated is The demodulation time is the number of bits times the shift clock period. Therefore, in order to shorten the demodulation time, it is necessary to increase the speed of the shift clock, but there is a limit to increasing the speed.
Since only a certain level of demodulation speed can be achieved and the demodulated output does not have a constant cycle, there is a problem that decoding of variable length codes, which will be performed at a later stage, cannot be performed efficiently.

In view of the above, an object of the present invention is to provide a demodulation device that is not affected by the code length of the variable-length code and is capable of cutting out the variable-length code at a high speed at a constant period.

Means for Solving the Problems In order to solve the above problems, the demodulator of the present invention converts first data that has been subjected to variable length encoding with a maximum bit length of m (m is a positive integer) into n ( A first-in, first-out memory (hereinafter referred to as FIFO) that inputs a bit width (n is a positive integer), stores it sequentially under the control of an external input instruction signal, and outputs it in the stored order according to a read instruction signal;
There are p (p is a positive integer) n-bit width storage means which receives output data from the input device and holds and outputs data controlled by a write instruction signal, and n×p bit width outputs of the p storage means. a ring buffer configured to select and output m bits consecutive from the bit at the position indicated by the read pointer in the direction of lower bits from the second data as third data; , the third
code length detecting means for outputting the code length of the variable length code starting from the most significant bit of the data as fourth data; code length integrating means for outputting the integrated value of the fourth data as fifth data; The remainder value obtained by dividing the fifth data by (H×p) is output as the read pointer, and the ring buffer does not include the third data currently being output and has already been treated as the third data. a control means for outputting the write instruction signal for instructing the corresponding storage means holding the output data to hold the new first data buffered in the FIFO; and the topmost part of the third data The present invention is characterized by comprising code separation means for selectively outputting the code length indicated by the fourth data as sixth data from bits to lower bits.

Effect of the Invention According to the above-described configuration, the first data, variable-length encoded data, is sequentially stored in the FIFO in units of n bits. Writing to the FIFO is controlled by an input instruction signal from the outside, and the first data is always stored in the FIFO without interruption, and is sequentially output in response to a read instruction signal. The first data sequentially output via the FIFO is sequentially held in p storage means. It is the write instruction signal that instructs the holding, which is a signal synchronized with the FIFO read instruction signal. That is, n×p bits from the beginning of the first data are divided and held and output by the pII storage means, and this H×p bit data is used as the second data. Thereafter, the first data is input in units of n bits, and the data held is updated by the write instruction signal.

Next, the selection means selects m consecutive bits in the lower bit direction from the bit position indicated by the read pointer and outputs them as third data.

Since the maximum bit length is m, the third data includes at least one variable length code. The code length detection means detects a variable length code starting from the most significant bit of the third data, and outputs the code length as fourth data.

The code separation means successively converts the code length indicated by the fourth data into the sixth data from the most significant bit to the least significant bit of the third data.
Selectively output as data.

On the other hand, the fourth data is accumulated by the code length accumulation means, and the fifth data is accumulated by the code length accumulation means.
is output as data.

The fifth data is input to the control means, which outputs the remainder after dividing by (n x p), that is, the offset from the beginning of the ring t<7 software, as a read pointer, and at the same time, the ring buffer currently outputs A write instruction signal is output to the storage means that does not include the third data and instructs the storage means that has already held the data that has been output as the third data to hold the new first data.

In this way, the value of the read pointer changes successively in units of variable length codes, starting with the variable length code at the beginning of the first data, the second variable length code, and the third variable length code, resulting in a ring tour. The third data output from the buffer always includes a variable length code starting from the most significant bit. Therefore, the variable length code is extracted by separating the third data using the fourth data value indicating the code length in the code separation means, and is output as the sixth data.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of a demodulation device in an embodiment of the present invention in which the maximum bit length of a variable length code is 21 bits, n is 16, and p is 4. FIG. 312 is a diagram showing an example of variable-length coded data, and FIG. 3 is a diagram showing the state of each part of this embodiment and explaining its operation.

In FIG. 1, 17 is a first-in first-out memory (hereinafter referred to as FI).
The first data f, which has been variable-length coded with a maximum bit length m of 21 bits, is input from the input terminal 18 with a width of n bits, that is, a width of 16 bits. It is controlled and stored sequentially. ll
A, in, tic, and lid are storage means into which the 16-bit output from the FIFO 17 is input and hold it, and have a width of n bits, that is, 16 bits, and consist of nine pieces, that is, four pieces. Reference numeral 12 denotes a selection means, which selects consecutive m bits, that is, 21 bits, as the third data h from the second data g of 4×16 bit width output from the four storage means 11a, llb, llc, and lid. Output. These FIFO 17 and storage means 11a.

11b, lie, and lid selection means 12 constitute a ring buffer 19.

Reference numeral 13 denotes a code length detection means, which detects the code length of the variable length code starting from the most significant bit of data h in section 3 and outputs it as fourth data i. 14 is a code length accumulating means, which outputs the accumulated value of the fourth data i as the fifth data j. 15 is a control means, which controls the fifth data j by (n×
p) That is, divide by (16 x 4), and send the remainder value to the selection means 12. As mentioned above, the selection means 12 selects the consecutive 21 bits from the data g in the box 2 as the third data and selects the lower bits. The storage means 11a, ll is output as a read pointer that determines the position when reading in the direction.
b.

write instruction signals a, b, for lie, lid;
e.

d and a read instruction signal e to the FIFO 17 in synchronization with each other. 16 is a code separation means;
The code length indicated by the fourth data i from the most significant bit to the least significant bit of the third data h is selected as the sixth data l, and is outputted to the decoding output terminal 2o.

The operation of the demodulator of this embodiment configured as described above will be described below with reference to FIGS. 2 and 3.

First, the control means 15 sends the read instruction signal e to PIFol.
The FIFO 17 outputs the first word (a word is 16 bits) of the variable length code data, which is the first data f input from the input terminal 111, to the storage means Ha,l.
Input to lb, llc, and lid. Next, control means 1
5 outputs a write instruction signal a to the storage means 11a to cause the storage means 11a to hold the variable length code data of the first word. Similarly, the control means 15 outputs a read instruction signal e'kF I FO17,
are storage means 11a, llb, llc, '11d1.
[Input the second word of variable length code data of data f of 1. Subsequently, the control means I5 outputs a write instruction signal S to the storage means 11b, and causes the storage means tlb to hold the second word variable length code data. Following the same procedure, write the third word to the storage means 11c and 1lcl, respectively.
The variable length code data of the fourth word is held.

As described above, the four storage means 11a and Ilb are stored.

tic and lid hold 64 bits from the beginning of variable length code data. These 64 bits are the second data g. At this time, each storage means 11a, llb, ll
c.

The lid is in a state of 5 tepl as shown in FIG.

Here, the most significant bit of the storage means 11a starts with bit 0, the least significant bit is bit 15, the most significant bit of the storage means 11b starts with bit I6, the least significant bit is bit 31, and the most significant bit of the storage means 11c is bit 32.
The least significant bit is bit 47, storage means 11
Let the most significant bit of d start with bit 48 and the least significant bit with bit 63.

Next, the control means 15 outputs the pointer value of the read pointer to O to the selection means 12, and the selection means I2 selects 2 from bit O to bit 20 as third data h.
Select one bit and make it appear. This situation is shown in 5je in Figure 3.
It is shown in pl.

The variable length code starting from the most significant bit of the 21 bits of the third data h output from the selection means 12 is detected by the detection means 13.
In Fig. 3, the code length of 4 bits is detected by
It appears as data 1.

The third data h output by the selection means 12 is also input to the code separation means 16, and the detection means 13 outputs the fourth data i, 4 bits corresponding to the code length, in the direction from bit 0 to bit 20. Separate and output the data.

This corresponds to the 4-bit code portion shown at 5jepl in FIG.

On the other hand, the code length, which is the fourth data i output by the detection means 13, is also input to the integration means 14, where it is integrated, and output as the fifth data j. Since this is the initial code length, the resulting cumulative code length is 4.

The control means 15 divides the accumulated code length by (n×p)64,
Use the remaining value as the next read pointer. At this point, the pointer value is 4. Therefore, the selection means 12 selects and outputs 21 consecutive bits in the lower bit direction from the 4-bit position indicated by the read pointer as the third data h. This situation is shown at 5tep2 in FIG.

゛In this way, 5jep4 shown in Figure 3
When the pointer value of the read pointer reaches 21, all the variable length codes in the data held in the storage means 11a are detected, and the control means 15 sends the read instruction signal e and the write instruction signal a. The data is sequentially output, and the fifth word of the variable length code data, which is the first data f, is newly held in the storage means 11a.

Similarly, when the process advances to s+ep7 shown in FIG. You get to choose. When the process roughly advances to ueplO, the pointer value of the read pointer h becomes 3, and the loopback process proceeds.

As described above, according to this embodiment, the ring buffer 19
Then, there are four storage means 11a, llb, llc.

The selection means 12 extracts the variable length code length (at least one data) from the position indicated by the read pointer from the circularly continuous output of the lid, and the detection means 13
By detecting the code length at , the code separation means 16 can separate variable length code units. At this time, the selection means 12 can select data including an undetected variable length code using the read pointer k in any case. Therefore, the eight decoded signals output from the a terminal 2a can be decoded continuously without interruption.

In the example, n was set to 16 and p was set to 4, but these are not particularly limited.

It goes without saying that a configuration may also be adopted in which the write instruction signal from the control means to each storage means is a common write instruction signal, and a write pointer is used to instruct the write storage means.

As described in detail, according to the present invention, the demodulation time is not affected by the code length of the variable-length code, and the variable-length code can be cut out at a constant period, and the variable-length code that will be cut out at a later stage can be cut out. Code decoding can be performed efficiently, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a demodulator in an embodiment of the present invention;
Figure 2 shows an example of variable-length encoded data;
The figure shows the state of each part of the embodiment and is a diagram for explaining the operation, and FIG. 4 is a block diagram of a conventional demodulator. 11a, Ilb, llc, l1d--storage means, 12--selection means, 13--detection means, 14-.
・Integration means, 15... Control means, 16... Code separation means, 17... First input first 8 memory (FIFO), 1
8...Input terminal, 19...Ring buffer, 20...
...Decoding output terminal. Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. First data that has been subjected to variable length encoding with a maximum bit length of m (m is a positive integer) is input with a width of n (n is a positive integer) bits, and a first-in, first-out memory that is controlled by an input instruction signal to sequentially store data and output data in the stored order in response to a read instruction signal; and an n-bit wide storage means that receives output data from the first-in, first-out memory and holds and outputs it in response to a write instruction signal. p (p is a positive integer) and n×p bit width outputs of the p storage means are used as second data, and from the second data, the lower bits are read from the bit at the position indicated by the read pointer. a ring buffer configured with a selection means for selectively outputting m bits consecutive in the bit direction as third data; and a code length of a variable length code starting from the most significant bit of the third data as fourth data. code length detecting means for outputting; code length integrating means for outputting an integrated value of the fourth data as fifth data; and a remainder value obtained by dividing the fifth data by (n×p) to the read pointer. buffered in the first-in, first-out memory in the corresponding storage means that does not include the third data currently being output by the ring buffer and holds data that has already been output as the third data. a control means for outputting the write instruction signal instructing to hold the new first data; 1. A demodulation device comprising code separation means for selectively outputting the data as data.