JPS614358A - Test pattern generator - Google Patents

Abstract

PURPOSE:To evaluate easily and quickly the performance of an image printer by adding an image generator, which can obtain dot patterns easily with a low cost, in parallel to a character generator of a conventional printer to generate varied image test patterns. CONSTITUTION:If a transmitted code signal indicates characters, a CPU2 outputs a transfer command signal of picture information of characters to a character generator 3; but if the transmitted code signal is images, the CPU2 outputs a transfer command signal of picture information of images to an image generator 4. The generator 3 or 4 sends picture information data corresponding to the command signal from the CPU2 to an image buffer 5. The buffer 5 receives picture information data from the generator 3 or 4 and stores these data as digital pattern information which correspond to pictures in 1:1. These stored pattern information are outputted to an external printing mechanism to obtain visible pictures. These visible pictures are checked visually to evaluate the performance of the printer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a test pattern generating device used when performing a printing test on a printer or the like.

(Prior art) Conventionally, in order to evaluate the performance of a printer, a test pattern generated from a built-in pattern generator was used to print the pattern2, and the results were used to judge whether the performance was good or bad. . By the way, most conventional printers were for printing characters.

Therefore, as a cheek pattern, printer performance can be evaluated by generating a character font pattern using a character generator, and an image pattern is not necessarily required. As a result, it can be said that very few conventional printers have the ability to generate a variety of image patterns.

In recent years, printers that handle image information have been commercialized. Therefore, it has become necessary to use not only character font patterns but also image patterns as test patterns for evaluating the performance of such printers. In this case, the following method has conventionally been used.

(2) As in the case of character font patterns, necessary image patterns are stored in the ROM in advance, and mesh patterns are created by repeatedly using these patterns.

■Mesh patterns are created using software algorithms.

(Problem to be solved by the invention) However, the method shown in (■) limits the number of mesh patterns that can be created, which limits the image patterns that can be created, and the method shown in (2) requires a complicated algorithm. Therefore, it has the disadvantage that it takes time to generate the mesh.

The present invention has been made in view of the above points, and its purpose is to add an image generator that can easily obtain mesh patterns at low cost in parallel to the character generator of conventional printers, and thereby to realize a wide variety of printers. An object of the present invention is to realize a test pattern generating device which generates a unique image test pattern and can easily and quickly evaluate the performance of an image printer.

(Means for Solving the Problems) The present invention achieves the above object by determining an input code signal and outputting data stored in a character generator or image generator to the outside via an image buffer. In the test pattern generation device configured to A counter that outputs a branch information signal for pulse on/off in addition to the pulse signal when a set value is reached, and a counter that receives the pulse signal and branch information signal from the counter and passes the pulse as it is when the branch information signal is on. The present invention is characterized by comprising a branch circuit that prevents the pulse from passing when the branch information signal is off, and a serial-parallel conversion circuit that receives the output of the branch circuit and converts it into parallel bit data.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a code buffer that receives a code signal and temporarily stores the signal, and 2 is the code buffer 1.
This is a CPU that receives the output of the CPU and performs various calculation controls. Said C
For example, a microcomputer is used as P'tJ2. A character generator 3 stores character font patterns, and outputs character font pattern data according to command information from the CPU 2. As the character generator 3, for example, a ROM is used. 4 is an image generator that outputs image pattern data according to command information from the CPU 2, and is a feature of the present invention. Reference numeral 5 denotes an image buffer 1 that receives pattern data sent from the character generator 3 or image generator 4 via the CPU 2 and temporarily stores the pattern data. The image buffer contains digital pattern information in one-to-one correspondence with the image, and a visible image can be obtained by outputting the information in the image buffer to an external printing mechanism, such as a dot printer or a laser printer.

The operation of the device configured as described above will be explained as follows. First, the code signal is a signal source (not shown).
When the code signal is sent from code buffer 1, the code signal is sent from code buffer 1.
is stored in The CPU 2 determines the code of the code signal sent from the code buffer 1. If the sent code signal is found to be a character, a command signal to transfer character image information is output to the character generator 3, and if the sent code signal is found to be an image, the image information of the image is sent to the character generator 3. A transfer command signal is output to the image generator 4.

The character generator 3 or the image generator 4 sends image information data to the image buffer 5 in accordance with a command signal from the CPU 2. Image buffer 5 is
Image information data from the character generator 3 or image generator 4 is received, and as described above, these data are stored as digital pattern information in one-to-one correspondence with the image. A visible image can be obtained by outputting the pattern information regarding the stored characters and/or images to an external printing mechanism, such as a laser printer or a wire dot printer. By visually inspecting this visible image, printer performance can be evaluated. That is, the apparatus shown in FIG. 1 can be used as a test pattern generating apparatus for evaluating the performance of a printer. Such a test pattern generation device can be built into the printer itself, or can be installed independently as a printer inspection device.

As mentioned above, the feature of the present invention is the image generator. The image generator generates image pattern data, and this image pattern is created by combining halftone dots of various halftone colors (gray) and arbitrary shapes covered by the halftone dots. Therefore,
First, generating halftone dots is the basis for constructing an image pattern. As is well known, the halftone dot is “1”
It is created by repeatedly appearing the `` bit and the ``O'' bit. Therefore, in order to generate halftone dots, it is sufficient to generate a pattern in which a certain number of bits are repeated. The image generator 4 operates based on this principle.

Next, the configuration and operation of the image generator 4, which characterizes the present invention, will be explained in detail. FIG. 2 is a diagram showing a specific configuration of the image generator 4. As shown in FIG. In the figure, 41 is a pulse generator that generates pulses, 42 receives the output of the pulse generator 41, counts the pulses according to a set constant value, and when the count reaches the set value, adds the pulse signal to the pulse signal. This is a counter that outputs a branch information signal for pulse on/off. The counter 42 is
As shown in the figure, a pulse train signal and a branch information signal are output. 43 is a branch circuit that receives the pulse train signal and the branch information signal sent from the counter 42 and allows the pulse to pass through as is when the branch information signal is on, and blocks the passage of the pulse when the branch information signal is off. , 44 is a serial-to-parallel conversion circuit that receives the serial pulse output from the branch circuit 43 and converts it into parallel bit data.

The output of the serial-parallel conversion circuit 44 is output to the CPU 2 (FIG. 1) and processed. As the number of output bits of the serial-parallel conversion circuit 44, for example, an 8-bit configuration, that is, a 1-byte configuration is used. The operation of the circuit configured in this way will be explained with reference to the waveform diagram of each part in FIG. 3.

The pulse generator 41 generates a regular pulse train as shown in FIG. 3(A). This pulse train is controlled by counter 4
Enter 2. The counter 42 has a constant value set in advance, and performs a counting operation as shown in FIG. 3 (b). That is, each time the input pulse count reaches the constant value, a branch information signal for controlling pulse on/off is sent to the branch circuit 42. In addition to this branch information signal, the counter also outputs a pulse train passing through the counter 42. The constant value given to the counter 42 is
It can be changed as needed. In the embodiment shown in FIG. 2, the constant value is 3. That is, the counter 42 increases its count value by one each time a pulse is input, and when the count value reaches three, changes the branch information.

The counter 42 turns on the branch information for the first three shots. When the count value reaches 3, the counter 42 resets the value to 1 and simultaneously turns off the branch information. Further, count from 1 to 3 shots and turn on the branch information signal again. By repeating this operation, the branch information signal can be turned on and off every time three pulses arrive. FIG. 3(c) shows the branch information signal created in this way.

The branch circuit 43 receives the pulse train signal and the branch information signal from the counter 42, and when the branch information signal is on, allows the pulse to pass through as is, and when the branch information signal is off, blocks the pulse from passing. As a result, the pulse train passing through the 'Q circuit 43 consists of a repetition of a series of pulses of a given constant. FIG. 3(d) shows a pulse train modified by branch information in this way. In the circuit shown in the figure, the pulse train consists of repeating three pulses on and three pulses off. Serial parallel conversion circuit 44
receives the serial pulse train signal from the branch circuit 43, converts it into parallel 8-bit (1 byte) data, and outputs 1 byte parallel data as shown in FIG. 3(E). Any mesh pattern can be generated by arranging the output byte strings obtained in this manner two-dimensionally. This output data is stored as image data constituting halftone dots in an image buffer via the CPU 2 (see FIG. 1) in response to a command signal from the CPU 2 (see FIG. 1). A test pattern made of stored image data, or in some cases a test pattern made of a combination of this and character data, is recorded on a recording paper or the like by a printing mechanism such as a printer. Then, by observing the recorded visible image, the performance of the printer can be evaluated. According to the present invention, it is possible to generate a pattern of any shape at high speed by simply receiving a code signal without having to store the pattern in advance in a ROM as in conventional devices.

In the above description, the case where the constant value set in the counter 42 is 3 is taken as an example, but the constant value is not limited to this, and any value other than 3 may be used as necessary. This constant value is set to various values according to the code in code buffer 1. That is, when desired test pattern information is input from the outside, a code is stored in the code buffer 1 in accordance with this, a constant value of the counter 42 is set in accordance with this, and a pattern is output and printed in accordance with this. As a result, patterns with various shapes and densities can be obtained. Further, the number of output bits of the serial-parallel conversion circuit 44 does not necessarily have to be one byte, and may be any number of bits.

(Effects of the Invention) As described above in detail, according to the present invention, an image generator that can easily obtain a mesh pattern at low cost is added to the character generator of a conventional printer in parallel, and various It is possible to realize a test pattern generation device that generates an image test pattern and can easily and quickly check the performance of a printer.

[Brief explanation of drawings]

FIG. 1 is an electrical configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration of an image generator according to the present invention, and FIG. 3 is a waveform diagram of each part of the circuit shown in FIG. 2. It is a diagram. 1... Code buffer 2... CPU 3... Character generator 4... Image generator 5... Image buffer 41... Pulse generator 42... Counter 43...
・Branch circuit

Claims (1)

[Claims] In a test pattern generation device configured to distinguish an input code signal and output data stored in a character generator or an image generator to the outside via an image buffer, the image generator generates a pulse. A pulse generator receives the output of the pulse generator, counts pulses according to a set constant value, and when the count reaches the set value, sends a branch information signal for pulse on/off in addition to the pulse signal. a counter for outputting; a branching circuit that receives a pulse signal and a branch information signal from the counter and allows the pulse to pass through as is when the branch information signal is on; and blocks passage of the pulse when the branch information signal is off; and the branch circuit. A test pattern generation device comprising: a serial-to-parallel conversion circuit that receives the output of the circuit and converts it into parallel bit data.