JPS6143474A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6143474A JPS6143474A JP16483884A JP16483884A JPS6143474A JP S6143474 A JPS6143474 A JP S6143474A JP 16483884 A JP16483884 A JP 16483884A JP 16483884 A JP16483884 A JP 16483884A JP S6143474 A JPS6143474 A JP S6143474A
- Authority
- JP
- Japan
- Prior art keywords
- region
- current
- layer
- conductivity type
- lifetime
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims 3
- 230000001419 dependent effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 229910052697 platinum Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、電力スイッチング素子として用いられる電流
変調型の半６体装置に量子る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a current modulated half-six-body device used as a power switching element.
近年、電力用スイッチング素子としてパワーＭＯＳＦＥ
Ｔが市場に現われているが、これに変わりて導電変調型
の半導体装置（以下ＢＩＦ′ｋＪＴと呼ぶ）が提案され
ている。In recent years, power MOSFEs have been used as power switching elements.
T is now available on the market, but instead of this, a conductivity modulation type semiconductor device (hereinafter referred to as BIF'kJT) has been proposed.
コレハ、ＭＯＳＦＥＴ と比ＭＴると、１ ０ ０ ０
（Ｖ）を超えるような高電圧にする事が可能であり、
かつ電流密度を高くして用いてもオン威圧（ＶＦ’）は
ＭＯＳＦＥＴの約１／１０と低いのみならず、スイッチ
ング時間が紋（μｓｅｃ ）と高速度である等の利点を
有しているため、今後高層ａｌａｓの電力素子として注
目されている。Koreha, MOSFET and ratio MT is 1 0 0 0
It is possible to make a high voltage exceeding (V),
Moreover, even when using a high current density, the on-force (VF') is not only low at about 1/10 of that of MOSFET, but also has advantages such as a high switching time (μsec). , is attracting attention as a power device for high-rise ALA in the future.
第３図にオン電圧と一流密度の関係を示した。Figure 3 shows the relationship between on-voltage and current density.
点線の■は従来のＭＯＳＦＥＴの（ＶＦ）を示し、実＠
＠ ｅ Ｑ ハＢ Ｉ Ｆ Ｅ Ｔ ｃ７） （Ｖ
ｒ ） ヲ示Ｌ ティ６゜但し、耐圧及び素子のチップ
サイズは同じ条件で比較している。ところでこのＢＩＦ
ＥＴが制御可能な（最大）ターンオフ電流は、素子の接
合温度（Ｔｊ ）が上昇すると共に降が、す、ｍ度に対
して負の特性を示す為室＠動作（Ｔｊ−２５℃）と高温
動作（Ｔｊ−１２５℃）では、素子の（最大）ターンオ
フ電流は約１７２に低下してしまう。したがって扁周波
駆動等においては、素子からの放熱を十分考慮しなけれ
ばならなくなる。The dotted line ■ indicates (VF) of the conventional MOSFET, and the actual @
@ e Q Ha B I F E T c7) (V
r ) Shown L 6° However, the comparison was made under the same conditions with respect to breakdown voltage and chip size of the element. By the way, this BIF
The (maximum) turn-off current that can be controlled by ET decreases as the junction temperature (Tj) of the device increases. In operation (Tj - 125°C), the (maximum) turn-off current of the device drops to about 172. Therefore, in flat frequency drive, etc., sufficient consideration must be given to heat radiation from the element.
本発明は上記の点に鑑み、最大ターンオフ電流が温度に
よる影響を受けず、オン「４圧（ＶＦ）をあまり犠牲に
しないで、かつスイッチング時間を２５０（ｎｓｅｃ）
以下と短かくした半導体装置を提供する事を目的とする
。In view of the above points, the present invention has been developed so that the maximum turn-off current is not affected by temperature, the on-off voltage (VF) is not significantly sacrificed, and the switching time is reduced to 250 (ns).
The purpose of the present invention is to provide a semiconductor device that is shortened as follows.
本発明は、第１図に示す素子構造において、 ｎ一層
のライフタイムを１（μｓｅり以下にし、かつライフタ
イムキラーとして酸大ターンオフシ流の温度依存性が少
ない物質を使用した事をＦＪ徴とする。The present invention has an FJ characteristic in which, in the element structure shown in FIG. do.
本発明によれば、 ＢＩＦｇＴが制御可能な最大ターン
オフ電流が高温でも低下せず、かつオン゛シ圧はあまり
増大せずにスイッチング時間を従来の約１７１０にする
事が可能で、この結果ターンオフ時間の大幅な短縮が央
現できる。According to the present invention, the maximum turn-off current that can be controlled by the BIFgT does not decrease even at high temperatures, and the switching time can be reduced to approximately 1710°C compared to the conventional one without significantly increasing the on-off pressure. A significant reduction in the amount of time can be achieved.
以下本発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は素子構造図であり、これを製造工程に従って説
明と、まずＩ Ｘ １０” （ｃｍ−”）種変のｐ子基
板１１４こ一方の主表面に濃度が７Ｘ１０’フ（ｃｍ−
リ。FIG. 1 is a diagram of the device structure, which will be explained according to the manufacturing process.
Li.
５（μｍ）厚の１１ 十ｐ→」を気相成長法によって形
成し、次いで０度第３ Ｘ １０ ”（ｃｍ−’ ）、
４０（μｍ）厚のｎ一層１２をさらに積層する。A 5 (μm) thick layer of 11×10” (cm−′) was formed by vapor phase epitaxy, and then a 0° 3×10” (cm−′) layer was formed.
One layer 12 having a thickness of 40 (μm) is further laminated.
次に選択拡散法によりて約５（μｍ）の深さにｐ・固１
３を形成し、更にその表面にｎ十層−りを形成する。Next, by the selective diffusion method, p.
3 is formed, and further n0 layers are formed on the surface thereof.
そして、熱酸比によりゲート絶縁膜１５を１０００（λ
）の厚さで１杉１戊し、この上にゲート＋４極話として
ポリシリコン模を約５０００（λ）形成し、・櫂ターニ
ングを行なう。Then, the gate insulating film 15 is heated to 1000 (λ
), a polysilicon pattern with a thickness of approximately 5000 (λ) is formed as a gate + quadrupole on this, and paddle turning is performed.
ざらにｐ＋基板１１の他方の主・Ｔり而にライムタイム
キラー（！：Ｌ、て、最大ターンオフ−流の温吠依存性
が少ない、たとえば白金（Ｐｔ）を蒸看し、低濃度のｎ
−ｑ （１２）のキャリア寿命をｌμｓｅｃ以下にな
るようにたとえば８６０℃×３０分の条件で熱拡散を行
なった。Roughly speaking, the other main component of the p+ substrate 11 is a time-time killer (!: L, te, where the maximum turn-off flow has less thermal dependence, for example, platinum (Pt) is evaporated, and a low concentration n
-q (12) Thermal diffusion was performed under the conditions of 860° C. x 30 minutes so that the carrier life was 1 μsec or less.
最後にｎ＋啜りとｐ町（口にオーミック電極をとるため
にゲートｅ縁瞬１５に穴あけを行ない、アルミニウムを
数（μｍ）刺着し、通訳エツチングしてソース電嘱１ノ
を形成する。次いでＰ 基板１１の他方の主表面にＶ
−Ｎ ｉ −Ａｎ ！ＩＫｆ−蒸着してドレイン：ＶＱ
ｌ ８を形成して完成する。Finally, in order to attach an ohmic electrode to the n+p hole, a hole is made in the gate edge 15, a few (μm) of aluminum is stuck on, and the source electrode is formed by etching.Next, V on the other main surface of P substrate 11
-Ni-An! IKf-evaporate and drain: VQ
Form l 8 and complete.
この実施例による素子の動作はソース電極１７をアース
し、ゲート剋４・＠ １６及びドレイン電ｔｉ＠ １８
に正の電圧を与えると、ゲートｆマ極１６直下のｐ聯１
３表面デ】３反転して箪子のチャンネルができるために
この素子はオン状態になる。The operation of the device according to this embodiment is such that the source electrode 17 is grounded, the gate electrode 4@16 and the drain voltage ti@18 are connected to the ground.
When a positive voltage is applied to
3 surface de] 3 is inverted to form a diagonal channel, so this element is turned on.
次にゲート電圧を零バイアスによると、ｐ十層１３表面
のチャンネルが消え、このチャンネルを流れていた′成
子電流を零になるため、その分だけ瞬時にドレイン電流
が減少Ｔ６゜さらにｎ一層［２中に残留するキャリアは
、ロー啼中へ導入されたライフタイムキラーによってキ
ャリア溌命τで絖衰し、ダイオード降下法によって測定
するとτくｌ（μ５ｅｃ）となった。Next, when the gate voltage is set to zero bias, the channel on the surface of the p-layer 13 disappears, and the current flowing through this channel becomes zero, so that the drain current instantly decreases by that amount. The carriers remaining in 2 were attenuated by the carrier life τ due to the lifetime killer introduced during the low-temperature process, and as measured by the diode drop method, became τxl (μ5ec).
第２図は、このＢＩＦＥＴが制御可能な最大ターンオフ
電流と素子の接合温度の関係を求めた天測結果である。FIG. 2 shows the results of astronomical measurements of the relationship between the maximum turn-off current that can be controlled by this BIFET and the junction temperature of the element.
図から明らかのように従来例では、Ｔｊ＝２５℃に対し
Ｔｊ−１２５℃では最大ターンオフ＋に流が約し２まで
低下してしまうが、実施例では、Ｔｊ＝２５°Ｃと比較
してほとんど低下せず、又’ｒｊ−ｘ２ｓ℃で従来例と
実施例を比較すると、最大ターンオフ′；１を流の値は
ほぼ同じになる。As is clear from the figure, in the conventional example, when Tj = 25°C, at Tj - 125°C, the flow approaches the maximum turn-off + and decreases to 2, but in the embodiment, compared to Tj = 25°C, There is almost no decrease, and when comparing the conventional example and the example at 'rj-x2s DEG C., the values of the current at maximum turn-off'; 1 are almost the same.
第２図は本発明の一実施例の導゛屯変調型スイッチング
素子を示す図、第３図は本発明の効果を説明するための
図、第１図（ま、ＭＯＳＦＥＴと導電変調型スイッチン
グ素子のオン抗圧（ＶＦ）の関係を示す図である。
１１・・・ｐ＋甚板（癖ｌ領域）、１２・・・ｎ一層（
第２領域）、１３・・・ｐ＋＋−（第３領域）、１４・
・・ｎ“脣（第４９１域）、１５・・・ゲート絶縁模、
１６・・・ゲ−トＪＪ’ｍ、” ７・・・ソース“１ｉ
４ｔ４，１８・・・ドレイン電極、１９・・・ｎ＋層（
第２領域の一部）。
代理人弁理士 則 近 憲 佑（ほか１名）第１図
第２図
昌
θ ２ｊ ！ｌ） ７６ｉ ／１）ｌ） ｆ’
ｓＴ、（Ｃ）
第８図
／ ２ ：Ｉ ｔｔ
５ＶＥ（Ｖ＞FIG. 2 is a diagram showing a conductive modulation type switching element according to an embodiment of the present invention, FIG. 3 is a diagram for explaining the effects of the present invention, and FIG. It is a diagram showing the relationship of on resistance pressure (VF).
2nd region), 13...p++- (3rd region), 14.
・・n"脣(491st area), 15...Gate insulation model,
16... Gate JJ'm," 7... Source "1i
4t4, 18...Drain electrode, 19...n+ layer (
part of the second area). Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Chang θ 2j! l) 76i /1) l) f'
sT, (C) Figure 8/2: I tt
5VE(V>
Claims (2)
１領域に接する部分に第２導電型の第２領域を順次積層
し、この第２領域表面に選択的に形成された第１導電型
の第３領域と、この第３領域表面に選択的に形成された
高不純物濃度で第２導電型の第４領域とを有し、前記第
３領域表面の第２領域と第４領域で挟まれた部分をチャ
ンネル領域として、この上にゲート絶縁膜を介してゲー
ト電極が形成され、前記第３領域と第４領域表面に同時
にコンタクトするソース電極が形成され、かつ前記基板
第１領域の他方の表面にドレイン電極が形成された半導
体装置において、前記第２導電型の第２領域にライフタ
イムキラーとして最大ターンオフ電流の温度依存性が少
ない物質を使用した事を特徴とする半導体装置。(1) A second region of a second conductivity type is sequentially laminated on a first region of a first conductivity type with a high impurity concentration in a portion in contact with the first region, and a second region of a second conductivity type is selectively formed on the surface of the second region. a third region of the first conductivity type; and a fourth region of the second conductivity type with a high impurity concentration selectively formed on the surface of the third region; A portion sandwiched between the four regions is used as a channel region, a gate electrode is formed thereon via a gate insulating film, a source electrode is formed in contact with the surfaces of the third region and the fourth region at the same time, and A semiconductor device in which a drain electrode is formed on the other surface of one region, characterized in that a substance whose maximum turn-off current has little temperature dependence is used as a lifetime killer in the second region of the second conductivity type. Device.
イフタイムキラーを拡散によって高不純物濃度の第１領
域からを介してドープしたことを特徴とする前記特許請
求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the lifetime killer whose maximum turn-off current is less dependent on temperature is doped by diffusion from the first region having a high impurity concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16483884A JPS6143474A (en) | 1984-08-08 | 1984-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16483884A JPS6143474A (en) | 1984-08-08 | 1984-08-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6143474A true JPS6143474A (en) | 1986-03-03 |
Family
ID=15800881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16483884A Pending JPS6143474A (en) | 1984-08-08 | 1984-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6143474A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04286163A (en) * | 1991-03-14 | 1992-10-12 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor substrate |
| JPH07111329A (en) * | 1990-11-29 | 1995-04-25 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Introduction and diffusion of platinum ion inside silicon slice |
| JPH0864811A (en) * | 1994-08-02 | 1996-03-08 | Sgs Thomson Microelettronica Spa | Power device integrated structure |
| JP2011166034A (en) * | 2010-02-12 | 2011-08-25 | Fuji Electric Co Ltd | Method of manufacturing semiconductor device |
-
1984
- 1984-08-08 JP JP16483884A patent/JPS6143474A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07111329A (en) * | 1990-11-29 | 1995-04-25 | Consorzio Per La Ric Sulla Microelettronica Nel Mezzogiorno | Introduction and diffusion of platinum ion inside silicon slice |
| JPH04286163A (en) * | 1991-03-14 | 1992-10-12 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor substrate |
| JPH0864811A (en) * | 1994-08-02 | 1996-03-08 | Sgs Thomson Microelettronica Spa | Power device integrated structure |
| JP2011166034A (en) * | 2010-02-12 | 2011-08-25 | Fuji Electric Co Ltd | Method of manufacturing semiconductor device |
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