JPS6142918B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color demodulation circuit for a SECAM type color television receiver.

The carrier color signal in the SECAM color television system is the modulated color signal of the blue color difference signal which is FM modulated around _B = 4.25MHz, and _R =
The modulated color signals of red color difference signals that are FM modulated around 4.40625MHz are arranged alternately every horizontal period, and in the color demodulation circuit of the receiver,
The original carrier color signal and the carrier color signal delayed by one horizontal period are switched by a switching circuit every horizontal period, and the modulated color signals of one and the other color difference signals are sent to the first and second output terminals, respectively. This is supplied to the first and second FM demodulators for demodulation, respectively. In this case, the first FM demodulator of the switching circuit
Therefore, the blue color difference signal is output from the first demodulator so that a modulated color signal of the blue color difference signal is obtained at the output terminal of the first demodulator, and a modulated color signal of the red color difference signal is obtained at the second output terminal of the demodulator. The switching state of the switching circuit is controlled so that the demodulated output of the red color difference signal is obtained from the second demodulator.

The present invention relates to a specific method for controlling this switching state.

The above carrier color signal has _B = 4.25MHz in the horizontal period in which the modulated color signal of the blue color difference signal is inserted.
In the horizontal period in which the modulated color signal of the red color difference signal is inserted, an unmodulated carrier of _R = 4.40625 MHz is inserted.

The present invention utilizes this non-modulated carrier, and is particularly designed to provide reliable control and a simple configuration.

FIG. 1 shows an example of the present invention, in which an original carrier color signal DI passed through a bell filter 1 and a limiter 2 is supplied to a switching circuit 3. A in Figures 2 and 3
indicates the state of the original carrier color signal DI, and C _B indicates the state of the original carrier color signal DI.
_B is an unmodulated carrier of 4.25 MHz, D _B is a modulated color signal of the blue color difference signal, C _R is an unmodulated carrier of _R = 4.40625 MHz, and D _R is a modulated color signal of the red color difference signal. This original carrier color signal DI is supplied to the delay circuit 4, and as shown in B of FIGS. 2 and 3,
A carrier color signal DL delayed by one horizontal period is obtained. This delayed transport color signal DL is then supplied to the switching circuit 3.

On the other hand, the flyback pulse FP is supplied to the pulse shaping circuit 11 and sliced at a certain level, resulting in a horizontal period at which the trailing edge bisects the unmodulated carrier section, as shown in FIGS. 2 and 3. A pulse NH of Pulses of opposite polarity that reverse to
FO and are obtained, one of the pulses FO is supplied to the OR circuit 15, the above-mentioned pulse NH is supplied to the OR circuit 15, the output pulse SW of the OR circuit 15 is supplied as a switching pulse to the switching circuit 3, For example, when the switching pulse SW is "1", the switching circuit 3 is switched to the state shown in the figure, and when the switching pulse SW is "0", the switching circuit 3 is switched to the state opposite to the state shown in the figure.

The signal BI obtained at the first output terminal of the switching circuit 3 is supplied to the first FM demodulator 5 for the blue color difference signal, and the signal RI obtained at the second output terminal is supplied for the red color difference signal. is supplied to the second FM demodulator 6.

Therefore, one output pulse FO of the flip-flop circuit 14 has a second output pulse FO with respect to the original carrier color signal DI.
When reversed as shown in FIG. E, the switching circuit 3 is switched in the correct state. That is, at this time, since the switching pulse SW becomes as shown in Figure F, the input signal BI of the demodulator 5 is such that only the modulated color signal D _B of the blue color difference signal is continuous, as shown in Figure G. Therefore, the input signal RI of the demodulator 6 is such that only the modulated color signal D _R of the red color difference signal is continuous, as shown in H in the figure.
The blue color difference signal is the demodulated output BO of the demodulator 6.
A red color difference signal can now be obtained as the demodulated output RO.

The demodulated outputs BO and RO are supplied to color blanking circuits 7 and 8, while the flyback pulse FP is supplied to a pulse shaping circuit 12 and sliced at a level different from the slicing level in the pulse shaping circuit 11 described above. As a result, as shown in FIG. 2R, a pulse WH with a horizontal period somewhat wider than the above-mentioned pulse NH is obtained, which is supplied to color blanking circuits 7 and 8, and demodulated outputs BO and RO. The horizontal retrace period portion is cleaned, and the outputs of the color blanking circuits 7 and 8 are taken out as demodulated outputs of a blue color difference signal and a red color difference signal through gain control amplifiers 9 and 10.

On the other hand, the demodulated outputs BO and RO of demodulators 5 and 6 are supplied to an adder 16 and added, and the added output
MO is supplied to the sampling hold circuit 20.

The sampling and holding circuit 20 has transistors 21 and 22 that constitute a differential amplifier, an addition output MO is supplied to the base of the transistor 21, and a terminal voltage of a holding capacitor 23 is outputted as an output voltage SH through transistors 24 and 25. When the sampling pulse is taken out and supplied to the base of the transistor 22, and is given as a constant current to the emitter sides of the transistors 21 and 22, if the addition output MO is larger than the output voltage SH, the transistor 21 is on, the transistor 22 is off, The transistor 26 is turned on and the capacitor 23 is charged, making the output voltage SH equal to the addition output MO. Conversely, if the addition output MO is smaller than the output voltage SH, the transistor 21 is turned on and the capacitor 23 is charged.
is off, transistor 22 is on, transistor 26 is off, and capacitor 23 is discharged.
The output voltage SH is made equal to the summation output MO.

On the other hand, 30 is a sampling pulse generation circuit,
Transistor 2 of sampling hold circuit 20
The emitters of transistors 31 and 32 constituting a constant current source of the differential amplifier 1 and 22 are connected in common, and a constant current transistor 33 is connected to the connection point. Then, the pulse NH from the pulse shaping circuit 11 mentioned above is applied to the resistor 3.
5, 35, 36 and a diode 37,
A divided voltage pulse at the connection point between resistors 34 and 35 is supplied to the base of transistor 31 via transistor 38, a divided voltage pulse at the junction point between resistors 35 and 36 is supplied to the base of transistor 39, and resistor 36 and diode 37 are connected to each other. A divided voltage pulse at the connection point is supplied to the base of the transistor 33.

On the other hand, the horizontal synchronizing pulse HD is supplied to the resonant circuit 17 to obtain the resonant voltage SR. This resonant circuit 17 is connected to the emitter of a transistor 39 and the base of a transistor 32 via a clamping capacitor 18. In this case, as shown in FIG. 5, the first negative half cycle of the resonant voltage SR is made to fall on the first half of the unmodulated carrier section of the second half of the pulse NH, and therefore this unmodulated carrier In the first half of the carrier section, a current flows from the emitter of the transistor 39 to the capacitor 18, the transistor 32 is turned off, the transistor 31 is turned on, and a constant current SP flows to the collector of the transistor 31. Then, when current flows through the capacitor 18 in the first negative half cycle of the resonant voltage SR,
The capacitor 18 is charged to the polarity shown and the base potential of the transistor 32 is clamped to a positive potential, so that for the rest of the pulse NH, the transistor 32 is off and the transistor 31 is off.
is never turned on.

In this way, the sampling pulse SP is applied from the sampling pulse generation circuit 30 to the sampling hold circuit 20 in the first half of the unmodulated carrier section of the second half of the pulse NH.

Then, the sampling and holding voltage SH from the sampling and holding circuit 20 is supplied to the integrating circuit 40, and its average value voltage SHI is obtained.

Furthermore, 50 is a comparison circuit, and a transistor 51
and 52, and transistors 51 and 53,
Each constitutes a differential amplifier, and the transistor 52
Capacitors 62 and 63 are connected to the collectors of and 53. In this case, the capacitance of capacitor 63 is made sufficiently smaller than that of capacitor 62. And the sampling and hold voltage mentioned above
SH is supplied to the base of transistor 51, its average value voltage SHI is supplied to the bases of transistors 52 and 53, and the other output pulse of flip-flop circuit 14 is supplied to the base of transistor 54 forming a constant current source. , during the period when transistor 54 is on, if sampling hold voltage SH is larger than its average value voltage SHI, transistor 51 is on, transistors 52 and 53 are off, and transistors 55 and 56 are on.
is turned on, and the two output currents I _x and I _y in the figure
becomes positive, that is, a constant current flows to charge the capacitors 62 and 63, and conversely, if the sampling and holding voltage SH is smaller than the average voltage SHI, the transistor 51 is turned off and the transistors 55 and 53 are turned off. , two output currents
Ix and Iy become negative, ie a constant current flows which discharges capacitors 62 and 63.

During the period when the transistor 54 is off, the output current Ix
and Iy are zero.

On the other hand, the power supply voltage is divided by resistors 71, 72, and 73, and the voltage at the connection point of resistors 71 and 72 is supplied to the base of transistor 74, so that a constant voltage V _F is obtained at the connection point of diode 75 and resistor 76. This point is connected to the capacitor 62 via a resistor 77. Further, the voltage at the connection point of resistors 72 and 73 is supplied to the base of transistor 78, and the emitter of transistor 78 is connected to capacitor 63.

Furthermore, 80 is a correction pulse generation circuit having transistors 81, 82 and 83, and a capacitor 6.
The terminal voltage E _x of the capacitor 63 is supplied to the base of the transistor 81 through the resistor 84, the terminal voltage E _y of the capacitor 63 is supplied to the emitter of the transistor 81, and the base of the transistor 81 is connected to the collector of the transistor 82 through the resistor 85. The collector is grounded through resistors 86, 87 and 88, and the connection point between resistors 86 and 87 is connected to transistor 8.
The connection point of resistors 87 and 88 is connected to the base of transistor 82, the pulse WH from pulse shaping circuit 72 is supplied to the base of transistor 83, and the voltage E _I at the collector of transistor 83 is It is supplied to the circuit 13.

As mentioned above, one output pulse FO of the flip-flop circuit 14 is inverted with respect to the original carrier color signal DI as shown in FIG. 2E, and the switching pulse SW becomes as shown in FIG. 3 is switched in the correct state, the input signal of the demodulator 5
BI becomes as shown in G in the same figure, and the input signal RI of the demodulator 6 becomes as shown in H in the same figure.
The unmodulated carriers in BI and RI are replaced by unmodulated carriers CR _{and CB} in the first half of the unmodulated carrier section of the horizontal period of the modulated color signal D _R of the red color difference signal of the original carrier color signal DI, respectively. .
The demodulation characteristics of the demodulator 5 are shown by the line (100B) in FIG. 4, and the demodulation characteristics of the demodulator 6 are shown by the line (100R) in the same figure.
At this time, the demodulated output BO of the demodulator 5 becomes as shown in FIG. 2I, and the demodulated output RO of the demodulator 6 becomes as shown in FIG. 2J.

Therefore, at this time, the addition output of the adder 16
The MO becomes as shown in FIG.
SP, that is, the sampling pulse shown in L in the same figure
The first half of the unmodulated carrier section in each horizontal period of the addition output MO is sampled and held by SP, and the sampled and held voltage SH shown by the solid line in M in the figure is obtained. Therefore, from the integrating circuit 40, a constant voltage indicated by a broken line in M in the same figure is obtained as the average value voltage SHI.

At this time, the flip-flop circuit 14
The other output pulse becomes as shown in FIG. _x and I _y are as shown in O of the same figure. That is, at this time, the time during which the constant current -I _p that discharges the capacitors 62 and 63 flows is longer than the time during which the constant current + _{I p} that charges the capacitors 62 and 63 flows. however,
Current flows into the capacitor 62 through the resistor 77, so that the terminal voltage E _x of the capacitor 62 does not fall below a certain value, and the terminal voltage E _y of the capacitor 63 also becomes the voltage at the connection point between the resistors 72 and 73. Therefore, only the forward drop voltage between the base and emitter of transistor 78 does not fall below the dropped voltage.

Therefore, at this time, the constant voltage V _F at the connection point between the diode 75 and the resistor 76 and the capacitor 62
Terminal voltage E _x and terminal voltage E _y of capacitor 63
The relationship is as shown in Figure 2 P, and the voltage E
_x is always higher than voltage E _y .

Therefore, at this time, the correction pulse generation circuit 80
At , transistor 81 is off, so transistor 82 is also off, and resistors 86 and 8
The voltage E _I at the connection point 7 is always at the ground potential, as shown in Q in FIG. 2, regardless of the pulse WH shown in R in the figure from the pulse shaping circuit 12.

That is, when the switching circuit 3 is switched in the correct state, no correction pulse is obtained from the correction pulse generation circuit 80, and therefore the state of the output pulse FO of the flip-flop circuit 14 remains unchanged.
The state of the switching pulse SW does not change, and the switching circuit 3 can be switched in the correct state.

On the other hand, when one output pulse FO of the flip-flop circuit 14 is inverted with respect to the original carrier color signal DI as shown in FIG. 3E, the switching circuit 3 is switched in an incorrect state. That is, at this time, since the switching pulse SW becomes as shown in Figure F, the input signal BI of the demodulator 5 is such that only the modulated color signal _DR of the red color difference signal is continuous, as shown in Figure G. As shown in _FIG . A blue color difference signal is now obtained as the demodulated output RO of the demodulator 6.

At this time, the input signals of the demodulators 5 and 6
The unmodulated carriers in BI and RI are replaced by unmodulated carriers C _B and _CR in the first half of the unmodulated carrier section of the horizontal period of the modulated color signal D _B of the blue color difference signal of the original carrier color signal DI, respectively. .
Since the demodulation characteristic of the demodulator 5 is shown by the line (100B) in FIG. 4, and the demodulation characteristic of the demodulator 6 is shown by the line (100R) in the same figure, at this time, the demodulation The demodulated output BO of the demodulator 5 is as shown in FIG. 3I, and the demodulated output RO of the demodulator 6 is as shown in FIG. 3J.

Therefore, at this time, the addition output of the adder 16
The MO becomes as shown in FIG. 3K, and in the sampling hold circuit 20, the first half of the unmodulated carrier section in each horizontal period of this addition output MO is sampled by the sampling pulse SP shown in FIG. As a result, the sampling and holding voltage SH shown by the solid line in M in the figure is obtained. Therefore, a constant voltage indicated by a broken line in M in the figure is obtained as the average value voltage SHI. That is, the state of the sampling and hold voltage SH with respect to the original carrier color signal DI is the same as when the switching circuit 3 is switched in the correct state.

However, at this time, the state of the other output pulse of the flip-flop circuit 14 with respect to the original carrier color signal DI is reversed to that when the switching circuit 3 is switched in the correct state, as shown in FIG. 3N. Therefore, at this time, the output currents I _x and I _y of the comparator circuit 50 become as shown in O in the figure.
That is, at this time, the time during which the constant current +I _p that charges the capacitors 62 and 63 flows is longer than the time during which the constant current I _p that discharges the capacitors 62 and 63 flows. Therefore, at this time, both the terminal voltage E _x of the capacitor 62 and the terminal voltage E _y of the capacitor 63 increase. However, since the capacitance of the capacitor 63 is made sufficiently smaller than the capacitance of the capacitor 62 as described above, the degree of increase in the voltage E _y is greater than that of the voltage _Ex .

Therefore, at this time, the constant voltage V _F at the connection point between the diode 75 and the resistor 76 and the capacitor 62
Terminal voltage E _x and terminal voltage E _y of capacitor 63
The relationship becomes as shown in FIG _. 3P, that is _, voltage E _y becomes higher than voltage _E The emitter-base forward drop voltage V _BE increases.

In this way, when the voltage E _y becomes higher than the voltage E _x by V _BE , the transistor 81 is turned on in the correction pulse generation circuit 80, and the
As shown in FIG. 2, the voltage E _I at the connection point of resistors 86 and 87 becomes positive, that is, a correction pulse is obtained. This correction pulse is supplied to the OR circuit 13,
As shown in Figure D, the trigger pulse TR is obtained, the flip-flop circuit 14 is inverted, and its output pulse FO is brought into the correct state as shown in Figures E and N. Therefore, the switching pulse
SW is also brought into the correct state as shown in FIG.

Note that when the transistor 81 is turned on, the transistor 82 is also turned on at the same time, and this state is maintained by positive feedback. Then, when the transistor 83 is turned on by the pulse WH from the pulse shaping circuit 12 shown in FIG. 3R, the voltage E _I becomes the ground potential, and the transistor 82 is turned off.
Transistor 81 is also turned off. In this case, since the rising edge of the pulse WH is located before the rising edge of the pulse NH from the pulse shaping circuit 11, the voltage E _I will definitely reach the ground potential before the pulse NH, as shown in FIG. 3D. , the correction pulse does not overlap with the pulse NH.

In this way, if the switching circuit 3 is switched in an incorrect state, this will be corrected within a short time and the switching circuit 3 will be switched in the correct state.

Note that the terminal voltage E _x of the capacitor 62 and the constant voltage V _F at the connection point between the diode 75 and the resistor 76 are supplied to a comparison circuit 90 for color killer, and the output voltage of the comparison circuit 90 is applied to the gain control amplifiers 9 and 10.
is supplied to When a color television signal is received, regardless of whether the switching circuit 3 is switched in the correct state or in the incorrect state, the voltage _Ex is always lower than the voltage V _F by a certain value or more, so the comparator circuit 90 The output voltage of is in a negative state and amplifiers 9 and 10 are not cut off.
On the other hand, when receiving a black and white television signal, there is no carrier color signal and the above-mentioned non-modulated carriers C _B and C _R do not exist, so the sampling hold voltage SH is a constant value, and therefore the sampling Hold voltage SH and its average value voltage SHI
are always equal, and the output currents I _x and I _y of the comparison circuit 50 are always zero. Therefore, when a black and white television signal is received, the voltage _Ex becomes equal to the voltage _VF , the output voltage of the comparator circuit 90 goes to another state, the amplifiers 9 and 10 are cut off, and the color killer works.

In the example shown in the figure, the input signals BI and RI of demodulators 5 and 6 are divided into every other horizontal period by using a horizontal period pulse NH whose trailing edge comes at a time point where the period of the unmodulated carrier is divided into two. This is a case where there is an unmodulated carrier that does not correspond to the subsequent modulated color signal in the first half of the unmodulated carrier interval, but the pulse has a horizontal period whose trailing edge is at the end of the unmodulated carrier interval. may be used so that in the input signals BI and RI of the demodulators 5 and 6, all unmodulated carriers in every other horizontal period become unmodulated carriers that do not correspond to the subsequent modulated color signal. .

And in this case, the sampling position is
It may be anywhere in the unmodulated carrier section.

Furthermore, when sampling and holding the addition output MO of the demodulated outputs BO and RO of the demodulators 5 and 6 as in the example in the figure, there is an advantage that the S/N is improved, but the demodulated outputs BO and RO of the demodulators 5 and 6 are Either of the ROs may be sampled and held.

Furthermore, the transistor 54 of the comparison circuit 50 may be supplied with an inverted pulse of the switching pulse SW. In short, the sampling and holding voltage
It is sufficient to compare SH and its average voltage SHI during the negative state of the switching pulse.

As described above, according to the present invention, since the sampling and holding voltage of the demodulated output is compared with its average value voltage, the DC level of the sampling and holding voltage changes due to the influence of the DC transmission characteristics of the circuit. Reliable comparative detection is also carried out,
Reliable control is achieved. Furthermore, since the sampling and holding voltage has a duty of 50%, there is no need to pay attention to the input impedance of the comparator circuit. Furthermore, since there is no need to provide a special demodulator for non-modulated carriers, the configuration is simplified.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of an example of a color demodulation circuit according to the present invention, and FIGS. 2 to 5 are diagrams for explaining the same. 3 is a switching circuit, 4 is a delay circuit of 1 horizontal period, 5
and 6 are first and second demodulators, 11 and 12 are pulse shaping circuits, 14 is a flip-flop circuit,
16 is an adder, 20 is a sampling hold circuit, 30 is a sampling pulse generation circuit, 40 is an integration circuit, 50 is a comparison circuit, and 80 is a correction pulse generation circuit.

Claims (1)

[Claims] 1. In every other horizontal period, the unmodulated carrier of the first frequency and the following
There is a first modulated color signal that is FM modulated, followed by an unmodulated carrier of a second frequency and an FM signal centered around the second frequency in the remaining every other horizontal period.
The original carrier color signal containing the modulated second modulated color signal and the carrier color signal obtained by delaying the original carrier color signal by one horizontal period are supplied to a switching circuit, and the two horizontal periods are divided into two horizontal periods. The switching circuit is switched by a switching signal that is inverted in the middle or at the end of the section of the unmodulated carrier in the horizontal period in the latter half of the period, and the switching circuit is switched so that the first and second output terminals thereof are supplied with the first and second output terminals, respectively. A signal in which one and the other of the second modulated color signals are repeated is obtained,
The signals obtained at the first and second output terminals are the first
and a second FM demodulator to be demodulated, and the switching signal of the unmodulated carrier section in each horizontal period of the output of the first or second FM demodulator or the summed output of both. The portion before the point corresponding to the inversion point is sampled and held, and this sampled and held voltage and its average value voltage are compared during one state of the switching signal, and the comparison output causes the switching circuit to be in the correct switching state. A color demodulation circuit in which it is determined whether or not the signal is present in the original carrier color signal, and the phase of the switching signal with respect to the original carrier color signal is controlled based on the determined output.