JPS6139761B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a laser diode (hereinafter abbreviated as LD) drive circuit used in large-capacity optical digital communication devices and the like.

In conventional high-speed optical digital communication equipment,
First, the non-zero return signal, or NRZ (Non-
It should be sent by a circuit that converts the return to Zero signal into a return to zero signal (this conversion is hereinafter abbreviated as RZ conversion).
An RZ pulse is generated, and this RZ pulse output is waveform-shaped by a current switching logic circuit (hereinafter abbreviated as CML) at the final stage and then supplied to the LD.

FIG. 1 is a circuit diagram showing a conventional drive circuit.
In the figure, transistors 102, 103, and 104 are gate circuits that output a logical sum (OR) and a non-logical sum (NOR) of inputs, and transistors 108 and 109 constitute a waveform shaping circuit. Also, diodes 105, 106 and 10
7 is a level shift diode that shifts the DC potential. When the NRZ signal is applied to the input terminal a' and the clock signal is applied to the input terminal 6, the transistor 104
The logical sum of the respective signals input to terminals a' and b is output to the collector of , and an inverted signal for returning to zero is obtained. Furthermore, the waveform is shaped by transistors 108 and 109, and the shaped
An optical signal for transmission is obtained based on the principle that an RZ pulse current flows through the laser diode 101 and an RZ pulse of light is generated.

However, in such a conventional circuit, when used at a high bit rate of several 100 Mb/s (megabits/second) or more, the cut-off frequency _T of transistors 108 and 109 is
It is necessary to use a special ultra-high speed transistor of about 10 GHz or to apply a large amplitude input signal to the base of transistor 108. Furthermore, since the level shift diodes 105, 106 and 107 are present, there are drawbacks such as increased fluctuations in the LD pulse current waveform due to temperature changes. Another disadvantage is that the circuit scale is large.

The purpose of the present invention is to achieve a speed of several 100 Mb/s using a simple circuit configuration using commonly available high-speed transistors.
The object of the present invention is to provide an LD drive circuit that has high speed that can support the above bit rates and has excellent temperature stability.

In the LD driving circuit of the present invention, a first non-zero return unipolar input signal is applied to a base terminal of the first transistor and a first transistor having a polarity opposite to that of the first non-zero return unipolar input signal. an emitter-coupled logic circuit in which a second transistor to which a second non-zero return unipolar input signal is applied to its base terminal is emitter-coupled; and a laser connected to the collector terminal of the second transistor directly or via a resistor. It consists of a diode and a clock applying means for applying a clock signal to the base terminal of the second transistor.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention. In the figure, reference numeral 201 is the driven LD, transistors 210 and 211
and the resistor 213 constitute a CML. Reference numeral 212 is a transistor for transmitting a clock signal to the base of transistor 211;
14 is a resistor that provides the operating point of the transistor 212, 215 is a capacitor for AC grounding the emitter of the transistor 212, and 217 is a load resistor for generating a clock voltage at the terminal. A DC bias current for the LD is passed from terminal C, and the bias is set to just before optical oscillation.

Figures 3a, b, c, d and e show time charts of the waveforms at terminals a, a', b, g and respectively. Further, f in the figure shows the optical output waveform of the LD.

Since the collector current of the transistor 211 flows only when the potential of the terminal becomes higher than the potential of the terminal a', it becomes an RZ signal, and this circuit can convert the NRZ signal into an RZ signal.

Note that the terminal e has a reference potential (earth), and the terminal d
Apply a negative power supply voltage to . transistor 2
Since the collector load impedance of 12 is low,
The operating speed of this transistor is high. Therefore, the operation speed of the transistor 211 is also improved, and a high-speed LD drive current pulse can be obtained.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. Reference numeral 401 is the LD, numerals 410 and 411 are the transistors forming the CML, numeral 418 is the transistor for making the sum of the emitter currents of the transistors 410 and 411 a constant current, and numeral 419 is the transistor of the transistors 410 and 411. A gate or flip-flop with an emitter-coupled logic circuit for supplying mutually inverted NRZ signals to the base, and a diode 42
0, 421, 422 and 423 perform level shifting to lower the base potentials of transistors 410 and 411.

When a clock signal is applied to terminal b, transistor 412, resistors 414 and 417, and capacitor 415 add the clock voltage to the NRZ signal. Since the collector current of the transistor 411 flows only when the potential of the terminal is higher than the potential of the terminal', an RZ signal current flows through the LD 401, and a corresponding optical pulse is generated.

In addition, the collector load resistance 416 of the transistor
It also has the feature that an RZ signal voltage can be obtained at terminal g due to the presence of .

Further, a negative voltage is applied to the terminal d with respect to the terminal e, and a DC current having a value slightly smaller than the oscillation threshold current of the LD 401 is caused to flow from the terminal c.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In this embodiment, a fixed bias is applied to the base of the transistor 511 via resistors 524 and 525, and a fixed bias is applied to the base of the transistor 511.
A clock voltage is applied by. Transistors 512 and 526 shape the clock waveform.
It constitutes CML.

As in this embodiment, the emitter circuits of transistors 510 and 511 may be composed of only resistor 513. In addition, in this embodiment, a resistor 527 is connected between the LD 501 and the collector of the transistor 511.
is inserted to reduce vibration and overshoot of the drive current pulse.

As described above, the present invention has the advantage that it has both RZ conversion and LD driving functions, has excellent temperature stability, and can obtain high-speed pulse current with a simple circuit configuration without using special semiconductor components. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional LD driving circuit, FIG. 2 is a circuit diagram showing a first embodiment of the present invention, and FIG.
Figures a, b, c, d and e are waveform diagrams of terminals a, a', b, g and the third embodiment, respectively.
FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a circuit diagram showing a third embodiment of the present invention. In the figure, 101, 201, 401, 501
... Laser diode, 102, 103, 10
4,108,109,210,211,212,
410, 411, 412, 418, 510, 51
1,512,526...transistor, 105,
106, 107, 420, 421, 422, 42
3,522,523...Diode, 213,2
14,216,217,414,416,41
7,513,516,524,525,527...
...Resistor, 215,415...Capacitor, 41
9,519... Emitter coupling logic circuit, a...
NRZ signal input terminal, b...clock input terminal,
a'...Inverted NRZ signal input terminal, c...LD bias current supply terminal, d...Negative power supply terminal, e...Reference potential terminal, f...Base voltage observation terminal of transistor 11, g...RZ signal output terminal.

Claims (1)

[Claims] 1. A first transistor to which a first non-zero return unipolar input signal is applied to its base terminal, and a second non-zero return unipolar input signal having a polarity opposite to that of the first non-zero return unipolar input signal. an emitter-coupled logic circuit in which a second transistor is emitter-coupled to a base terminal to which an input signal is applied via a resistor; and a laser diode connected to a collector terminal of the second transistor directly or via a resistor. , and clock applying means for applying a clock signal to the base terminal of the second transistor. 2. An emitter-coupled logic circuit in which a first transistor to which a non-zero return unipolar input signal is applied to the base terminal and a second transistor to which a predetermined constant voltage is applied to the base terminal are emitter-coupled; A laser diode drive circuit comprising: a laser diode connected directly or via a resistor to the collector terminal of the second transistor; and clock applying means for applying a clock signal to the base terminal of the second transistor. .