JPS6139660A - Packet exchange system - Google Patents

Abstract

PURPOSE:To relay a large quantity of packets by a control part corresponding to a relay circuit only by controlling and transferring a frame level of a packet where the control part corresponding to the relay circuit comes in and goes out in the relay circuit. CONSTITUTION:When a calling packet received from a relay line 301 is inputted into a receiving buffer circuit 204, a processor 209 reads a called terminal address, gives to the first retrieval circuit 207, gets the number of a control part storing this terminal and re-writes an address field of the packet to the number of the control part. Further, the processor 209 reads a logical channel number from a receiving packet and gives to the second retrieval circuit 208 together with a called terminal number. The retrieval circuit 208 selects a logical channel number for transmitting with higher priority order and sends to the processor 209. The processor 209 writes in the obtained logical channel number into the receiving packet and sends to a system bus 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a packet conversion system, and in particular to a distributed control system that includes a control section that performs control corresponding to a terminal line and a control section that performs control corresponding to a relay line. relates to a packet switching system.

(Prior art) Generally, a packet switching system based on a distributed control method uses a system bus (SB) 1 g as shown in FIG.
Multiple line compatible control units (C
CPo, CCPI, COF2. COF2...)20.
21, 22, 23, etc., and among them, for example, the line corresponding control section 20 is used for the relay line, and the other line corresponding control sections are used for the terminal line. In addition, the trunk line (TRK) 30 is connected to the line correspondence control unit for the trunk line (hereinafter referred to as the second control unit), and the line correspondence control unit for the terminal line (hereinafter referred to as the second control unit)
Packet terminals (Pi, P
2. P3...) 31, 32°, 33..., etc. are arranged in such a way that they are connected. Here, the second control unit 20 controls all passing packets according to the protocol each time. On the other hand, both the system bus 10 and the relay curve 30 generally have a transmission speed much higher than that of the terminal line, and when trying to transfer packets to the full transmission capacity of the trunk line 30, the second control unit 20 1 control unit 21, 22, 23 is required. However, due to the hardware configuration, it is desirable to use the same processor for both line-compatible control units as described above, and the same processor is used to perform the same control as the relay exchange for all incoming and outgoing packets. In this case, the transmission efficiency of the trunk line 30 becomes low,
As a result, the number of trunk lines must be increased.

(Object of the Invention) An object of the present invention is to provide a packet switching system using a distributed control method that can eliminate the above-mentioned drawbacks and improve the transmission efficiency of trunk lines.

(Structure of the Invention) The packet switching system of the present invention is a packet switching system using a distributed control method, which has a first control section that performs control corresponding to a terminal line and a second control section that performs control corresponding to a relay line. the second control unit includes a first search means for obtaining information specifying a first control unit that accommodates the called terminal from the called terminal address specified in the called packet; transfer destination adding means for adding information specifying the first control unit obtained from the search means; a logical channel number specified by packets received after the incoming packet; and a logical channel number specified by the incoming packet. The second step is to obtain the called terminal address from the correspondence with
and a search means.

(Description of Embodiments) Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration diagram of a second control unit that performs control corresponding to the relay line of the present invention in the packet switching system having the configuration shown in FIG. Indicates when there is. A second control unit (CCPo) 20 is connected to a bus receiving circuit (BRIF) 201 connected to the system bus 10 and also to a system bus 1.
The bus transmitting circuit (BSIF) 202 connected to the bus receiving circuit 201 and the transmitting buffer circuit 4 (SBIF) connected to the bus receiving circuit 201
FM) 203 , a reception pan 7a circuit (RBlf) 204 connected to the bus transmission circuit 202 , and a transmission buffer 7
A packet transmitting circuit (SDR) 205 connected to the circuit 203 and the outgoing line 301 of the relay line (TRK) 30, and a packet receiving circuit (REC) that is overread by the incoming line 302 of the relay 1 30 and the receiving buffer circuit 204. 206, 1st detection J circuit (FRY) 207, 'i42 search D W1
5 (SRV) 208 and the processor (C
PU) 209.

Next, to explain the function of each of the above circuits,
The bus receiving circuit 201 takes in only the data addressed to the control unit for each packet out of the packets inputted from the system bus 10, and sends the other packets to the system bus 10 as they are. The bus transmission circuit 202 receives a transmission ready signal inputted from the system bus 10, and sends out a packet to which a destination designation is added.

The transmission buffer circuit 203 has a plurality of buffer memories each having a packet length, checks the packets inputted from the bus reception circuit 201 for frame errors, temporarily stores them, and stores the packets input from the bus reception circuit 201 according to link-level addresses and logic according to instructions from the processor 209. The channel number is changed and a frame check bit is added again at the time of transmission. Reception buffer circuit 20
4 has multiple buffer memories of the packet length,
Packets input from the packet receiving circuit 206 are checked for frame errors and temporarily stored, and sent to the processor 20.
9, the link level address and logical channel number are changed, and a frame check bit is added again at the time of transmission. The packet transmitting circuit 205 transmits the packet transmitted from the transmitting buffer circuit 203 to the trunk line 301 with a flag sequence added before and after the packet. The packet receiving circuit 206 receives the packet from the trunk line 302 and sends it to the receiving buffer circuit 204.

As shown in FIG. 3, the first search circuit 207 has a correspondence table between the addresses of terminals belonging to the exchange system and CCP numbers specifying the first control unit in which the terminals are accommodated, As shown in FIG. 4, a second search circuit 208 that searches for a CCP number from a terminal address under instructions from a processor 209 searches for logical channel numbers arranged in the use priority order added by this second control unit when transmitting a packet, as shown in FIG. (a logical channel number including a logical channel group number and a channel number of that group), it has a correspondence table in which the logical channel number of a received packet and the called terminal address are written in accordance with instructions from the processor 209. , reads the corresponding address or number according to instructions from the processor 209. Further, the processor 209 controls each of the above circuits.

Next, the operation of the second control section 20 will be explained.

The incoming call packet received from the trunk line 301 is shown in FIG.
As shown in a), the International Telegraph and Telephone Advisory Committee Recommendation CCI
Between the bit strings of the frame sequence (F), address field (A) and control field (C) specified at level 2 according to TTX.25 and the bit strings of the frame check sequence (Fe2) and frame sequence (F') There is an information field (INF) specified at level 3, and the information field contains the logical channel number (LCN), packet type identifier (TYP), and the called terminal at L/, X (Ca
lled DTE Add), calling terminal address (Ca
lling DTEAdd), etc.

Here, when a packet following the frame sequence is input to the reception buffer circuit 204, the processor 209 reads the called terminal address, for example P2, and sends it to the first search circuit 204.
7, obtains the number of the first control unit that accommodates this terminal, for example CCPI, and rewrites the address field of this packet to CCPI. Furthermore, the processor 209 extracts the logical channel number, for example β3, from the received packet and provides it to the second search circuit 208 together with the called terminal number P2. The second search circuit 208 selects an unused transmission channel number with the highest priority, for example α1, from the correspondence table and sends it to the processor, and also selects the M4%q channel number of the received packet corresponding to this number. β3
and writes the called terminal address P2. Next, processor 209 replaces the obtained logical channel number with the logical channel number of the received packet. In this way, the number of the destination first control unit is assigned in the reception buffer circuit 204 as shown in FIG. 5(b), and only the new logical channel number is assigned. When a transmission permission signal is obtained, a frame check sequence is added and the frame is sent from the bus transmission circuit 202 to the system bus. The first control unit CCP1 receives this packet. Next, in the data packet or recovery request packet received after the incoming call packet,
), when these packets are received and input into the receive buffer circuit 204, the processor 209 determines the packet type of the received packet. Knowing these packets from the child, logical channel number β
3 and gives this number β3 to the second search circuit 208 to obtain the called terminal address P2 and the previously used logical channel number α1 for transmission. Then processor 2
09 gives the called terminal address P2 to the @1 search circuit 207 and obtains the number CCPl of the first control unit. Next, as in the case of receiving a calling packet, the address field of the received packet in the receive buffer is set to the destination number CCpl of the first control unit (replaced with C, and the logical channel number is set to α1 for sending).
replace it with FIG. 5(d) shows a packet having the same shape as those shown in FIG. Thereafter, this packet is sent to the first control unit CCP1 in the same way as the incoming call packet.

Note that the incoming call acceptance packet or recovery confirmation packet sent from the first control unit to the second control unit after sending the incoming call packet to the first control unit has the same format as shown in FIG. Since the number of the second control unit is specified and the logical address number specified in the incoming call packet is specified, the processor 209 uses the second search circuit 208 to find the logical channel number previously obtained from the incoming call packet. is obtained and reassigned, the address field is also reassigned to be the same as that attached to the incoming call packet, and the packet is sent to the trunk line 302. In addition, when receiving and transmitting a recovery confirmation packet, the processor 209 sends the second search circuit 208 the channel number and called terminal address that were written at the time of receiving the incoming call packet after completing the necessary search at that time. to be erased.

Furthermore, the calling packet from the first control unit to the trunk line is input to the second control unit in the format shown in FIG. is assigned a number designated by the first control unit. In this case, the processor 209 knows from the packet type identifier that it is a calling packet, and instructs the second search circuit 208 to select the logical channel number for transmission with the lowest priority that is not in use from the correspondence table. The number is obtained, and the designated logical channel number is written in the received packet in correspondence with the number. Next, the processor 209 specifies the address for sending to the middle line (generally "1") in the address field of this calling packet stored in the sending buffer-1 circuit 203, and also obtains the logical channel number. The logical channel number for transmission is respecified and relayed via the packet transmission circuit 205.
Have it sent to 1J1301. Regarding subsequent transmitted and received packets, the same control unit as described above is performed in the incoming call packet reception [d, data packet reception, and recovery request packet reception].

In addition, since the second control circuit 20 checks all packets sent and received as described above to make sure there are no errors in the packets based on the frame check sequence bit, if an error is detected, CCITTX, 25 Recommendation is applied. Accordingly, retransmission, etc., is controlled at the frame level.

(Effects of the Invention) As described in detail above, according to the present invention, the second control unit corresponding to the trunk line is connected between the frame level control of packets entering and leaving the trunk line and the first control unit corresponding to the terminal line. The first control unit has functions for line-compatible protocol control, packetization control, and packet processing, so processing can be shared among the two. A second high-speed search circuit using a slow operating speed processor can be installed.
The control unit can also relay a large amount of packets and improve the transmission efficiency of the relay line.

[Brief explanation of the drawing]

The first night is a block diagram of an example of a packet switching system using the 5+ scattered control method, FIG. FIG. 4 is a diagram showing a correspondence table provided in the first search circuit in FIG. 2; FIG. 5 is a diagram showing a correspondence table provided in the second search circuit in FIG. 2; FIGS.
A(d) is a diagram showing each packet format. 10... System bus (SB8 20-23)
Old...Line compatible control unit (CCPo~3), 30...
...Relay eye end (TRK), 31-36...Terminal (P1-Pg), 201...Path reception port i4
(BRIF), 202...Bus transmission circuit (BS
IF), 203... Sending buffer circuit (SB
FM), 20.1... Receive buffer circuit (R
BF average, y'1.3- 205...Packet transmission circuit (SDR), 2
06...Packet receiving circuit (REC), 20
7...1st inspection M (FRY), 208...
...2nd examination 1st test t& (SRV), 209...
...Processor (CPU).

Claims (1)

[Claims] In a distributed control packet switching system that includes a first control unit that performs control corresponding to a terminal line and a second control unit that performs control corresponding to a relay line, a first search means for obtaining information specifying the first control unit that accommodates the terminal; and a transfer destination for adding to the incoming call packet the information specifying the first control unit obtained from the first search means. a second means for obtaining a called terminal address from a correspondence between a logical channel number specified by a packet received after the called packet and a logical channel number specified by the called packet;
A packet switching system comprising: the second control section comprising a search means.