JPS6139514A - Manufacture of gaalas semiconductor device - Google Patents

Manufacture of gaalas semiconductor device

Info

Publication number
JPS6139514A
JPS6139514A JP59160030A JP16003084A JPS6139514A JP S6139514 A JPS6139514 A JP S6139514A JP 59160030 A JP59160030 A JP 59160030A JP 16003084 A JP16003084 A JP 16003084A JP S6139514 A JPS6139514 A JP S6139514A
Authority
JP
Japan
Prior art keywords
layer
melt
added
gaalas
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59160030A
Other languages
Japanese (ja)
Inventor
Atsushi Matsuzaki
松崎 温
Shigetaka Murasato
村里 茂隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP59160030A priority Critical patent/JPS6139514A/en
Publication of JPS6139514A publication Critical patent/JPS6139514A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2907Materials being Group IIIA-VA materials
    • H10P14/2911Arsenides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/26Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition
    • H10P14/263Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition using melted materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421Arsenides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3438Doping during depositing
    • H10P14/3441Conductivity type
    • H10P14/3442N-type
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3438Doping during depositing
    • H10P14/3441Conductivity type
    • H10P14/3444P-type

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  • Led Devices (AREA)

Abstract

PURPOSE:To prevent an electrically connected part from making inroad into the region of an indirect transition as well as to enable to manufacture a GaAlAs light-emitting diode device of excellent light-emitting efficiency by a method wherein the second P- layer of low acceptor impurity density is provided between the first P-layer and an N- layer. CONSTITUTION:The first p-layer 11 is grown by contacting a Zn-added GaAlAs melt to a p-type GaAs substrate by performing a liquid phase epitaxial growing method, and then the second p-layer 12 is grown by contacting the GaAlAs melt, wherein Zn added in the quantity less than the above-mentioned added quantity of Zn, to the first P-layer 11. Moreover, an n-layer 3 is grown by contacting a Te added GaAlAs melt to said layer 12. Consequently, although the Te of the n-layer 3 is diffused in the second p- layer 12, it can be adjusted on the composition interface J, because the degree of the above-mentioned diffusion is lower than the diffusion of Zn. If the effect of compensation is taken into consideration on the composition interface J of the second p-layer 12, namely, the p-layer 13 and the n-layer 3, the density of carrier becomes NA=ND on the composition interface J, the electrically connected part J' and the composition interface J are coincided, and an excellently efficient light-emission can be performed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は液相エピタキシャル成長法によってG a A
 鳳A s発光ダイオードに用いるエピタキシャルウェ
ハーを製造する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides G a A by liquid phase epitaxial growth method.
The present invention relates to a method for manufacturing epitaxial wafers used in Otori As light-emitting diodes.

従来の技術 一般にGaAlAs発光ダイオード装置に製造する場合
には、第3図に示すよ5にG a A sを基板1とし
て多層スライドLPE成長装置等を用いてPメルト、次
いでnメルトを接触させ、エピタキシャル成長法によっ
てP−nf&合gJk得ている。通常、アクセプター不
純物としてはZnを使用して2層2を、ドナー不純物と
してはTe1に使用し″′Cn層3を順次点騙矢印4の
方向&CrIyt長させる。発1元の中心となる、0y
はP層2fn層3は窓効果を目的・としたもの〕である
。この際、出来上ったエビタ争りヤル成、多層の混晶比
とし【はP層がX=0..35.1層が3C=0.65
のAli添加しZ (J a 1.1− XA g N
 A−3にそれぞれZ n又はTe1に所定磯度麻加し
た結晶か得られるようにメルトに調整して用い1発光又
は窓効果を高めている。
2. Description of the Prior Art Generally, when manufacturing a GaAlAs light emitting diode device, as shown in FIG. P-nf & gJk were obtained by epitaxial growth. Usually, Zn is used as the acceptor impurity to form the second layer 2, and Te1 is used as the donor impurity, and the Cn layer 3 is sequentially lengthened in the direction of the dotted arrow 4 &CrIyt.
The P layer 2fn layer 3 is intended for window effect]. At this time, the composition of the completed Evita is determined, and the mixed crystal ratio of the multilayer is set as follows: .. 35.1 layer is 3C=0.65
Z (J a 1.1- XA g N
A-3 was adjusted to melt to obtain a crystal with a predetermined degree of roughness added to Zn or Te1, respectively, and was used to enhance the luminescence or window effect.

特に、P層は発光中心でそのZn濃度制岬は直装であ、
る。メルト中のZnは蒸発し易く、結晶のZn一度はメ
ルトのZn添加量の他に成長装置。
In particular, the P layer is the luminescent center and its Zn concentration cape is directly attached.
Ru. Zn in the melt evaporates easily, and the amount of Zn in the crystal depends on the amount of Zn added to the melt and the growth equipment.

成長過程等にも依存するが、−例を示せばメルトのZn
:0.+5mo1%に朽シ結晶のzn濃度は2 X l
’、 o 18   −3CIn    程度となる。
Although it depends on the growth process etc., for example, Zn in the melt
:0. +5mo1% and the Zn concentration of the rotten crystal is 2Xl
', o 18 -3CIn.

また、アクセプター不純物としてGaを便用することも
あるが、アクセプター濃度を高めるため、多層のLje
 &)’メルトに添加すると、格子欠陥が増大するとい
5ffi人7L欠点があり1通常Znが使用されている
In addition, Ga is sometimes used as an acceptor impurity, but in order to increase the acceptor concentration, multilayer Lje
&)' Zn is usually used because it has the drawback that lattice defects increase when added to the melt.

上記PH4,1層のドーパントの拡散および偏析係数の
温度変比¥:無祝し、P、1層の組成変化がlよいもの
と仮定丁れば、第4図に示すように成長方向4へのアク
セプター一度NA、およびドナーg度N、の分布は一定
とlよる筈である。
Temperature variation ratio of dopant diffusion and segregation coefficient in the above PH4, 1 layer: No congratulations, P, assuming that the composition change in the 1st layer is good, the growth direction is 4 as shown in Figure 4. The distribution of acceptor degree NA and donor degree N should be constant.

しかし、ZnはGeのように格子欠陥が増大する工’5
1に欠点はないが、拡散係数が大きくその拡F!!LJ
P組成の温度変化などがあるためNA、NDは成長方向
にgk度勾配を生じ、ZnがP−n接合部Ji越えて1
層に拡散した分布?とる。
However, like Ge, Zn is used in a process that increases lattice defects.
1 has no drawbacks, but its diffusion coefficient is large and its expansion F! ! L.J.
Due to temperature changes in the P composition, NA and ND produce a gk degree gradient in the growth direction, and Zn crosses the P-n junction Ji.
Diffused distribution in layers? Take.

Nh、N0c))t″比ヲにP−n接合部JK着目する
と第5図に模式的に示すようにZn濃度NNA拡散によ
り接合部Jを越えて0層3まで拡散し実線で示すよ5は
分布となり、またn Jt!IのTe鐘fgLNDは、
成長方向4に浴って破線で示す分−(+i ’atとる
。この2つの濃夏分布Nム、NDが重する部分は、補償
幼果でその差が天ぎい方がキャリアとなって観察され、
一点鎖線で示す見掛けのキャリア一度分布5となる。
Nh, N0c)) If we focus on the P-n junction JK at the t'' ratio, as schematically shown in Figure 5, the Zn concentration NNA diffuses beyond the junction J to the 0 layer 3, as shown by the solid line 5. is the distribution, and the Te bell fgLND of n Jt!I is
The part indicated by the dashed line in the growth direction 4 is taken as −(+i 'at.The part where these two dense summer distributions Nmu and ND overlap is a compensation young fruit, and the one with the largest difference becomes the carrier, and it is observed that is,
The apparent carrier distribution 5 is shown by the dashed line.

このため、直接遷移領域と間接遷移領域との組成境界J
′と実際の電気的接合部J′とはずれを生じ。
Therefore, the compositional boundary J between the direct transition region and the indirect transition region
' and the actual electrical connection J'.

−゛  電気的接合部J′ が間接遷移の領域に存在下ることKなり、極めて発光効
率の恋いものとなる。
-゛ Since the electrical junction J' exists in the region of indirect transition, the luminous efficiency is extremely low.

本発明が解決しようとする問題点は、@尤幼率のよいG
aAl As発光ダイオード装置を製造するため、電気
的接合部が間接遷移の領域に食込むのを防止することが
出来るようにする点にある。
The problem to be solved by the present invention is @G
In order to manufacture an aAlAs light emitting diode device, it is possible to prevent the electrical junction from digging into the region of indirect transition.

問題を解決する手段は、P型G a A s基板上に液
相エピタキシャル成長法によってアクセプター不純物と
してZoom加し之(jaAIAsメルl接触させて第
11’層を成長させ、rKいで第LP層上にZnを上記
Zn添加祉よりも少なく添加したG a A J A 
sメルト・を接触させてg2P/itを成長させ、さら
にその上にドナー不純物としてTeを添加したG a 
A I A sメルトを接触させて1層を成長させる方
云である。
A means to solve the problem is to grow the 11' layer by adding Zoom as an acceptor impurity on the P-type GaAs substrate by liquid phase epitaxial growth method and growing the 11' layer in contact with the LP layer using rK. G a A J A with less Zn added than the above Zn addition amount
G2P/it was grown by contacting S melt, and then Te was added as a donor impurity on top of it.
This is a method of growing one layer by bringing AIAs melt into contact.

このため、第1図に示すように%第tp層【l。Therefore, as shown in FIG. 1, % tp layer [l.

g2PJlj12お工び0層3のエピタキシャル成長に
当っては、それぞれ従来と同じ量のAIを添加シy3 
G a −G a A s −A 1メルトを用い、基
板上に第LP+!’abX長させメルトには、Znを添
加して成長させ1次いで、この第L)’/*の上に、前
記第tt’層成長時のメルトより少ない址のZny添加
したメルトによって、厚さ:L〜2μmの第2Plfi
lを成長させ、さらに42P)IIの上に従来と同じ1
層を成長させる。
g2PJlj12 When epitaxially growing layer 3, the same amount of AI as before was added to layer 3.
G a - G a As - A 1 melt was used to form the LP+! on the substrate. The 'abX lengthened melt is grown with Zn added thereto.Next, on top of this L)'/* layer, a Zny-added melt with a smaller amount than that of the melt used in growing the tt' layer is added to increase the thickness. :L~2μm second Plfi
1), and then grow the same 1 as before on 42P) II.
Grow layers.

この際、第t)’+nttのZnがm2PI曽L2へも
拡散してくるので、@2P層L2の成長相のメルトには
Znv少址しか含まないかあるいは全(合まなくてもP
IdL3が得られる。vclitとしては。
At this time, Zn at t)'+ntt also diffuses into m2PI so L2, so the melt in the growth phase of @2P layer L2 contains only a small amount of Znv, or all of it (even if it does not fit, P
IdL3 is obtained. As for vclit.

・公知の多層成長用スライドボート等が使用される。- A known slide boat for multilayer growth is used.

上記操作によって第LP層を成長させると、成長M後は
、    −゛   子吟忙第1P層jLのアクセプタ
ー濃度NAは高いレベルにあるが、第2P層12および
1層の成長過程で拡散し、次第に舎鹸→→−セ→低下し
てくる。第2P層12のアクセプター濃度は、第2P層
【2とnA13との界面でドナーa度と同じレベルニr
!レバよ(。
When the LP layer is grown by the above operation, after the growth M, the acceptor concentration NA of the first P layer jL is at a high level, but it is diffused during the growth process of the second P layer 12 and the first layer. The level gradually decreases. The acceptor concentration of the second P layer 12 is at the same level as the donor a degree at the interface between the second P layer [2 and nA13].
! Reba (.

第1P層11からのZnの拡散があるので、第2P層メ
ルト中のZnn変度極く少なくてよ(、全(Zn4含ま
ないメルトを使用してもよい。キャリア濃度につぎNA
、NJ)の好ヱし−・レベル化あ1 B     −3 げれば、NA : L〜3XLOcm   、ND:5
〜LOXIOcm    程度である。
Since Zn diffuses from the first P layer 11, the variation of Zn in the second P layer melt is extremely small (a melt containing no Zn4 may be used).
, NJ)'s preferred level A1 B-3, NA: L ~ 3XLOcm, ND: 5
~LOXIOcm.

上記のように成長を行なえば、n#3の“reも第2P
層【3に拡散するがZnの拡故に比較して小さいため、
組成界面JK、おいて調整でき、第2PjtjlL2、
つまりIP11P¥1!【3と0層3との組成界面Jに
おいて、補償効果?考vd丁れば、キリア濃度は組成界
面JにおいてNA:NDとなり、 iml気的接合部J
′と組成界面Jは一致し効率のよい発光が行なわれる。
If the growth is performed as described above, the “re” of n#3 will also become the second P.
Although it diffuses into layer [3], it is small compared to the diffusion of Zn, so
The composition interface JK, can be adjusted at the second PjtjlL2,
In other words, IP11P¥1! [Compensation effect at the composition interface J between 3 and 0 layer 3? Considering vd, the Kiria concentration becomes NA:ND at the compositional interface J, and the iml gas junction J
' and the compositional interface J coincide, and efficient light emission occurs.

実施例 〔実施例【〕 P型GaAs基板上に、第1表に示すメルトを用いて第
IP7d、第2P層およびn1舗を順次成長させた。
Example [Example] On a P-type GaAs substrate, the melt shown in Table 1 was used to sequentially grow the IP7d, the second P layer, and the layer n1.

第  1  表 操作条件は、多層スライドボートa相エビタキ7ヤル成
長fCmを用い、820°Cで60分保愕した後、P型
層 a A S基板に第【P層成長用メルト&11g1
iL、  0 、3 °C/ m i nの速度で降温
し、第LPJ!’v成長させ、7966CVC1K ’
)T: トCロで、上記第1P層の上に第2P層成畏用
メルトを載置して795°Cに降温して第2P層を成長
させ、795°Cにおいて上rid第2P虐上にn層成
兼用メルトv装置しn層を成長させた。エピタキシャル
°成長層の厚さは第Ll’層が25μm、第2P層が1
μm、n層が28μmであった。また。
Table 1 The operating conditions are as follows: Using a multilayer slide boat a-phase Ebitaki 7-yel growth fCm, after incubation at 820°C for 60 minutes, a P-type layer a
The temperature was lowered at a rate of iL, 0, 3 °C/min, and the second LPJ! 'v grow, 7966CVC1K'
)T: In ToC, the melt for forming the second P layer is placed on the first P layer, the temperature is lowered to 795°C to grow the second P layer, and the second P layer is grown at 795°C. An n-layer was grown on top using a melt V apparatus for n-layer formation. The thickness of the epitaxially grown layer is 25 μm for the Ll′ layer and 1 μm for the second P layer.
μm, and the n-layer was 28 μm. Also.

キャリア纜度vQIJ定したところ、P−n接合部近傍
においてNA冬2,0XLOcm   。
When the carrier hardness vQIJ was determined, the NA was 2.0XLOcm near the P-n junction.

(’JD冬5,6XLOCtn   でアッタ。('JD Winter 5, 6 XLOCtn Atta.

この半導体は、スキャンユングエレクトロンマイクロス
コープC8HM)におけるEBIC像(・電気的接合部
J’ )と組成界面が一致していることを確認しzo 〔実施例2〕 第2表に示すメルトヲ用いて第tt’層、第2P層Sよ
びnWIY順欠成長させ、贋の厚さ化、第1Plfl 
: 24 μm、 m2 PjvI: 2 μm、n層
:26μmとしたほかは、実施例【と向じとした。
It was confirmed that the compositional interface of this semiconductor matched the EBIC image (electrical junction J') in a Scan Jung Electron Microscope (C8HM). tt' layer, second P layer S and nWIY sequential growth, thickening of fake, first Plfl
: 24 μm, m2 PjvI: 2 μm, n-layer: 26 μm, but the same as Example [Example].

第  2  表 また、キャリア嬢度は、 P−n接合部近傍にお1g 
     −3− いてNAAl1.6X L g   cm   、Ni
’?lフー3 5.0XlOcm   であツタ。
Table 2 also shows that the carrier resistance is 1g near the P-n junction.
-3- NAAl1.6X L g cm, Ni
'? Ivy 3 5.0XlOcm.

この半導体も、実施例【りものと同t4EBIc像と組
成界面が一致していることを確認した。
It was confirmed that the compositional interface of this semiconductor also coincided with the same t4EBIc image as that of Example [Rimono].

上記実施例」、実施例20半尋体(発光ダイオード)と
、従来の方法でつくった第2P層を設げない発光ダイオ
ードと%:、穐常発光ダイオードの比較に用いられる4
度測定法によって比較したところ、不発明の方法によっ
てつくられたものが、明瞭に高い出刃を示すことが確認
された。
4 used for comparison of Example 20, a half-body (light-emitting diode), a light-emitting diode without a second P layer made by a conventional method, and a normal light-emitting diode.
When compared by a hardness measurement method, it was confirmed that the one made by the uninvented method clearly showed a higher cutting edge.

具体的に数値で示せばピーク波長:57Q、nmにおけ
る発光出力は、第2図に示すように、実施例1′Mよび
実MIA例2においては、それぞれ従来広のり、5倍、
1.37倍の発光出力を示しzoこ2tより、不発明の
方法によってつ(もれた発光ダイオードの組成界面にお
ける補償幼果を考慮しy5NA、N、Dは、N人=ND
であることがわかる。
Specifically, in numerical terms, the light emission output at the peak wavelength: 57Q, nm is as shown in FIG.
It shows 1.37 times the luminous output and is produced by an uninvented method (taking into account the compensation effect at the compositional interface of the leaked light emitting diode, y5NA, N, and D are N = ND).
It can be seen that it is.

不発明の効果 以上述べたように、不発明に係る(#a A J A 
s発光ダイオードは、4TLP屑とn層との間にアクセ
プター不純物供度の低い第2PI−が設けられているの
で、P型層のアクセプター不純物のn層に対する拡散が
抑制され、抽償幼釆?考1ばした1u気的朕合部がnJ
ψ内に食込むことなく、篩いS度のGaAlAs半導体
装置が得られる。
Effect of non-invention As mentioned above, regarding non-invention (#a A J A
In the S-light emitting diode, since the second PI with low acceptor impurity donation is provided between the 4TLP scrap and the n-layer, diffusion of the acceptor impurity of the P-type layer into the n-layer is suppressed, making it possible to reduce the possibility of an early stage. The 1U air conditioner that I considered was nJ.
A GaAlAs semiconductor device with S sieve degree can be obtained without encroaching into the ψ.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の詳細な説明図で、六←←÷゛、アクセ
プター不純 物が拡散し終りに後のキャリア旋層分布を示す図、第2
図は、fE米法と1本発明の方法によって造った半導体
の発光出力を比較した図、第3図ないし第5図は、従来
の方法によってつ(つた半4体の説明図で、第3図は半
導体の61析而図、第4図は理想的キャリア分布の仮想
図、第5図は、電気的接合部がn )dIc A−込む
状態のB!ll明図である。 【・・・・・・基板、3・・・・・・n増、4・・・・
・・電灯方向。 11・・・・・・第【P層、I2・・・・・・第2P盾
、【3・・・・・・P)dl、N人・・・・・・アクセ
グター不純物(Z n )濃度、ND・・・・・・ドナ
ー不純物(TeJ磯度、J・・・・・・p  n接合部
(組成界面)、J′・・・・・・電気的接合部。 7−戊辰、+5う頗 J′匁札的停4旬 第2図 第3図 第4図
Fig. 1 is a detailed explanatory diagram of the present invention;
The figure shows a comparison of the light emitting output of semiconductors produced by the fE method and the method of the present invention. The figure is a 61 analysis diagram of a semiconductor, Figure 4 is a virtual diagram of an ideal carrier distribution, and Figure 5 is a state in which the electrical junction is n ) dIc A - B! This is a clear diagram. [... board, 3... n increase, 4...
...Light direction. 11...th [P layer, I2...2nd P shield, [3...P) dl, N people...Accessor impurity (Z n ) concentration , ND... Donor impurity (TeJ Isodo, J... p-n junction (composition interface), J'... electrical junction. 7-Boshin, +5 Uguri J'Mome Fuda's Stop 4 Seasons Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims]  P型GaAs基板上に液相エピタキシャル成長法によ
つてアクセプター不純物としてZnを添加したGaAl
Asメルトを接触させて第1P層を成長させ、次いで第
1P層上にZnを上記Zn添加量よりも少なく添加した
GaAlAsメルトを接触させて第2P層を成長させ、
さらにその上にドナー不純物としてTeを添加したGa
AlAsメルトを接触させてn層を成長させることを特
徴とするGaAlAs半導体装置の製造方法。
GaAl with Zn added as an acceptor impurity by liquid phase epitaxial growth on a P-type GaAs substrate
A first P layer is grown by bringing an As melt into contact with the first P layer, and then a GaAlAs melt to which Zn is added in a smaller amount than the above Zn addition amount is brought into contact with the first P layer to grow a second P layer.
Furthermore, Ga is added with Te as a donor impurity.
A method for manufacturing a GaAlAs semiconductor device, characterized in that an n-layer is grown by contacting with an AlAs melt.
JP59160030A 1984-07-30 1984-07-30 Manufacture of gaalas semiconductor device Pending JPS6139514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59160030A JPS6139514A (en) 1984-07-30 1984-07-30 Manufacture of gaalas semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59160030A JPS6139514A (en) 1984-07-30 1984-07-30 Manufacture of gaalas semiconductor device

Publications (1)

Publication Number Publication Date
JPS6139514A true JPS6139514A (en) 1986-02-25

Family

ID=15706436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59160030A Pending JPS6139514A (en) 1984-07-30 1984-07-30 Manufacture of gaalas semiconductor device

Country Status (1)

Country Link
JP (1) JPS6139514A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348467A (en) * 1989-04-17 1991-03-01 Nec Corp Light emitting diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348467A (en) * 1989-04-17 1991-03-01 Nec Corp Light emitting diode

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