JPS6137814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal strength detection circuit that uses a multi-stage signal strength detector to detect the received signal strength of a receiver over a wide dynamic range and with good linearity. be.

Conventionally, in order to detect the received signal strength of a receiver, it has been known to use a signal strength detector with a multi-stage configuration that sequentially outputs detection signals from multiple stages according to the signal strength. When using a signal strength detector of The signal bends at the intensities of B and C, resulting in poor linearity, making it impossible to detect with good linearity a practical received signal range of about 90 dB from 10 dB to 100 dB.

The present invention provides a signal strength detection circuit that solves these conventional problems.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Figure 1 is the overall circuit diagram, where 1 is the antenna,
2 is a high frequency amplifier with variable gain; 3 is a mixer that mixes the output of high frequency amplifier 2 and the output of the local oscillator applied to terminal 4; 5 is an intermediate frequency amplifier that amplifies the output of mixer 3; 6 is a detector. The output of this detector 6 is supplied to the speaker from the low frequency stage. On the other hand, 7 is an attenuator that attenuates the output of the mixer 3, 8 is an intermediate frequency amplifier into which the output of the attenuator 7 is input via the ceramic filter _CF1 , 9
The output of the intermediate frequency amplifier 8 is a ceramic film.
A signal strength detector is inputted via CF ₂ , 10 is its signal strength output terminal, and 11 is a power supply terminal.

FIG. 2 shows a specific circuit of IC ₂ constituting the signal strength detector 9, and shows the circuit when it is constructed from μPC1167C.

In Fig. 2, the intermediate frequency amplifier applied to the terminal is amplified by the limiter amplifier 12, and its output
_O1 , _O2 , _{and O3} are applied to three detection stages comprised of _Q64 to _Q66 , _Q61 to _Q63 , and _Q59 to _Q60 , and the output signals of each stage are output from the terminals. As is clear from FIG. 1, the output appearing at the terminal drives the attenuator 7, and the output appearing at the terminal applies AGC to the high frequency amplifier 2.

In the above configuration _, when the output of the intermediate frequency amplifier 8 is applied to _the terminal 1 in _FIG .
O ₁ is applied, transistors Q ₉₃ , Q ₆₇ , Q ₆₈ ,
Current flows through Q ₆₉ and Q ₇₀ , and a signal corresponding to the signal strength is output to the terminal.

Next, when the input signal strength increases, the output O ₂ of the limiter amplifier 12 causes the transistors Q ₆₁ ,
The second stage consisting of Q ₆₂ and Q ₆₃ is driven, increasing the currents of transistors Q ₉₃ , Q ₆₇ and Q ₆₈ to output a larger signal from the terminals.

When the input signal becomes even larger, the output _O3 of the limiter amplifier 12 causes the transistor to
The third stage consisting of Q ₅₈ , Q ₅₉ , and Q ₆₀ is driven,
Outputs a signal even larger than the terminal.

In this way, the signal strength detector 9 outputs a detection signal that gradually increases in accordance with the input signal strength, and this is supplied to a predetermined circuit such as a meter from the terminal 10 in FIG. The signal intensity output that appears is the result of the addition of the slopes of each stage, resulting in an output with a slope and no linearity as shown in FIG.

Therefore, in the above embodiment, the resistors R ₁₀ and R ₁₁ are set so that current starts flowing through the pin diode D ₁ in FIG. 1 in response to the terminal output when the second stage starts operating.
By setting the value of , and setting the value of resistor R ₉ to suppress the signal strength output at the terminal, and further applying AGC to the high frequency amplifier 2 with the output appearing at the terminal when the third stage starts operating, Second
This is intended to suppress changes in the slope of the signal strength output of the terminal where the third stage and third stage operate. In this way, it is possible to suppress changes in the intensities B and C in FIG. 3 and improve linearity.

In addition, for large input signals, the input of the intermediate frequency amplifier 8 is attenuated by the attenuator 7, and the gain of the high frequency amplifier 2 is reduced to attenuate the signal input to the mixer 3. 3 and the intermediate frequency amplifier 8 can be prevented from saturating quickly, a wide dynamic range can be ensured, and A to D in FIG. 3 can be made into a practical range of about 90 dB.

As described above, according to the present invention, signal strength detection with a dynamic range and linearity that does not cause any practical problems can be realized using a multi-stage signal detector.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the signal strength detector used in FIG. 1, and FIG. 3 is an explanatory diagram of its operation. 2... High frequency amplifier, 3... Mixer, 4...
Input terminal for local oscillation output, 5... intermediate frequency amplifier, 6... detector, 7... attenuator, 8... intermediate frequency amplifier, 9... signal strength detector.

Claims (1)

[Claims] 1 a variable gain high frequency amplifier, a mixer that mixes the output of the high frequency amplifier and the output of the local oscillator, an attenuator that attenuates the output of the mixer, an intermediate frequency amplifier that amplifies the output of the attenuator, and the intermediate and a signal strength detector with a multi-stage configuration that detects signal strength using the output of the frequency amplifier and sequentially outputs detection signals from multiple stages according to the signal strength, and the final stage of the signal strength detector detects the signal strength. AGC is applied to the high frequency amplifier from the level, and the attenuator is driven from the detection level of one stage before the final stage of the signal strength detector to attenuate the input signal of the intermediate frequency amplifier. Signal strength detection circuit.