JPS613590A - Video encoding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal distribution apparatus and, more particularly, to a video signal distribution apparatus characterized by signal integrity to enable only subscribed recipients to receive encrypted television programs. Related to transmission/distribution equipment.

[Purpose to start]

It is an object of the present invention to provide an improved encrypted television signal distribution apparatus.

More particularly, it is an object of the present invention to provide a secure signal distribution system for restricting the reception of encrypted (scrambled) paid television programs for pay television recipients.

[Structure of the invention]

These and other objects of the present invention are realized in a particular encrypted video distribution apparatus having a signal generation head end that encrypts the output television zologram signal. In particular, the video content of nine selected lines is inverted with respect to the reference voltage level and the inverted reference level amplitude transmitted in a nocellus manner during the horizontal sync pulse interval. Line video anti-V non-inversion is controlled by a preset pseudo-random number generator that progresses at the line rate.

At each receiver, all inversion lines are returned to a unique format using the received inversion amplitude level in the horizontal synchronization interval as a reference. A pseudorandom number generator is included in the receiver signaling circuit and operates in the same order as a similar circuit at the head end that identifies lines requiring video inversion.

DESCRIPTION OF THE EMBODIMENTS Other features and advantages of the invention will become more apparent from the following detailed description of embodiments of the invention with reference to the accompanying drawings.

Referring first to FIG. 1A, a line of video information is shown included as one of a series of lines within a video field. The line begins with a horizontal sync telus during two periods 110-11'4.

The horizontal sync level is the lowest amplitude voltage point in the line. In the NTSC system, horizontal synchronization is -4°IRE
Although shown as units, the signal level varies from -40 amplitude up to +100 IRE units (corresponding to a pure white image) during the synchronization interval. Horizontal synchronization A' at time 114
Following the loop edge is a subcarrier 118 (color burst frequency 3.58 MHz). This was followed by period 11
At 7-125, a mother turn of video information - in the example shown, a 1.5 cycle sine wave 119 is superimposed on an internal slope 120 from black to white, peaking at white level 122 and ending in a straight line. There is a pattern ending in a slope 123 from white to black. The video content of each line is, of course, actually.

Varies depending on the unique image portion being represented.

In accordance with the principles of the invention described below, video encryption.

Black level (OIRE) and white level peak (+100
This is accomplished by selectively inverting the video information with respect to an intermediate level between IRE and +50 IRE. For purposes described below, a nominal pulse 116 is included during the horizontal synchronization period with an amplitude corresponding to the DC inversion level (for purposes of this discussion, only 9 + 50 IRE, as described above). .

Figure 1B shows that the video is not inverted and color burst 1
A video information line is shown in which the information content of the line following 18 substantially corresponds to the content of the normal conventional line shown in FIG. 1A. The lines of FIG. 1B according to the present invention are at times 112 and 113 within the horizontal synchronization period 110-114.
The only difference from a normal line is that an inverted reference pulse 116 is inserted between the lines.

FIG. 1C corresponds to the normal line in FIG. 1A, but
A video line is shown where the video information is inverted with respect to +50 IRE. The reversal line is a horizontal pulse pack pouch with color burst sine wave 118 (
Video information period 117-125. ) is the same as the non-reversal line throughout the horizontal period including However, following the horizontal pulse back porch, video information period 117-1
25. All of the video information is inverted regarding the +50 level. For example, at the beginning of the video information (the beginning of the sine wave 119).

It starts at +100 (white level) rather than at 0 (black level) in Figure 1B. Return by reversing.

The shape and level of the rest of the hiteo wave 7% + 50 (7)
It shows a mirror image of the normal video returned with respect to the selected inversion level. The corresponding video signal portions are shown in FIG. 1c with the same reference numerals used in FIG. 1A or FIG. 18, but with a "," prefix.

In conventional receivers without decoding equipment, the video information content of each line is not inverted or otherwise.

Therefore, the image cumulatively received by the eye over multiple frames is an entirely blank image. In fact, the cumulative image through 9 screens is a flat field of +50 IRE.

This reception suppression occurs when encryption is not used. However, according to one form of the invention, the above-mentioned inverted/non-inverted wave is suppressed in amplitude during the synchronization period, as is known per se, and further prevented from receiving the signal in non-subscriber equipment. There is. If such synchronization suppression is employed, the receiving device will of course be equipped with devices known per se for regenerating the synchronization information and reversing the synchronization period amplitude reduction made in the signal generating head end or transmitter. It is equipped with

Many ways to communicate line reversal information to the system receiver so that only the reversed lines are re-inverted and thereby in normal format will be obvious to the art technician. Such inversion is performed on a predetermined basis, for example by simply counting the lines within the field. However, according to other concepts of the present invention that will be apparent from the description below, similar repeating pseudo-random number generation is provided to control line video inversion/non-inversion/4' turns to increase video integrity. A device is provided on both the encryption side and the decryption side.

Referring to the above system operation overview, 1A to IC
Reference is now made to FIG. 2 in which a video encryption (selective line inversion) apparatus is shown implementing the encryption mode described with reference to the figures. Video source 10 is 2 normal ('NTSC standard)
The format video information is supplied to automatic gain control/DC regeneration circuit 12 and sync separator 33. Video source 10 may include any baseband video source 9 well known to those skilled in the art, such as a video camera, tape recorder, microwave demodulated to baseband, or satellite communications. The AGC/llc regenerator 12 is a well-known circuit in itself, although not necessary, commonly used to clean the video signal and ensure transmission accuracy and quality if the video level is not sufficient. .

The video information is supplied to an amplifier 11 with an amplification degree of "+1",
Non-inverted video (i.e. 9 normal NT as in Figure 1A)
SC signal) is available at output 15. Video information is also provided to an inverting amplifier 13 with an amplification of "-1" to provide an inverted video at output 16 (eg, the video portion during periods 117-125 of FIG. 1C). DC inversion reference level source 18 (
A DC level +50 IRE ) is connected as a second input to the inverting amplifier 13 . Many types of amplifiers that perform the functions described above will be obvious to those skilled in the art; for example, there are operational amplifiers, two of which are shown in the drawings, which are themselves well known. Amplifier 11 with amplification factor "1" is used to maintain the relative phases of the two inverting and non-inverting transmission channels substantially equal.

The non-inverted and inverted video signals from amplifiers 11 and 14 are provided as inputs to multiplexer 20 along with a DC inverted reference level from source 18. Furthermore, the multiplexer 20 is supplied with a signal at the color burst frequency (obtained by dividing the frequency of the oscillator 32, which is four times the color burst frequency, into 1/4 in the frequency divider 24). The color burst is transmitted in the modulator 20a during some predetermined period 1, for example line 17 during the vertical period.

As with NAND logic gate 21, it is amplitude modulated with the decoding shift key. The multiplexer 20 is.

Among its four inputs, a desired signal component is selected for supply to the video modulator 80, constituting an output wave according to the selection control obtained by the decoder 43. In this way, a multiplexer is operated under the control of a decoder to provide a line 2 that is coded but not inverted, for example in the form shown in FIG. 1B.
During the horizontal sync pulse period and the color burst back porch (periods 110-114), except for periods 112-113 during which the reference level is passed to the modulator 80, the amplifier output 1
The non-inverted output from 5 is passed by multiplexer 20 to video modulator 80. Since no inversion occurs, the video signal from non-inverted output 15 is transmitted during video information period 117-
124 interrogator 80. Reverse video line (eg.

1C) is the information content portion (114-, 1) of the video wave.
25), the output from the inverting output 16 is output to the video modulator 8.
is similarly configured, except that it is selected by multiplexer 20 to be fed to 0.

The video line train with inverted or non-inverted video content is boosted to the desired output radio frequency by a modulator 80 and then coupled to any distribution means 1 such as a radiating antenna or CAT.
It is supplied to V and MATV cables. Also, audio content for the television program provided by audio source 83 and processed by modulator 84 is generated. Second
Other configurations shown generate control information for multiplexer 20.

and involved in the encoding process. counters 35 and 44
A timing/logic circuit 3o having a counter output status decoder 4o and 47 is provided which subdivides the entire image period between vertical synchronization pulses into predetermined time slots and during each decoded period. Perform the necessary functions required. Cascaded counter 3
5 and 44 and decoders 40 and 47 are well known to those skilled in the art and are available as integrated circuits in practice. Similarly, the use of cascaded counters and decoders to subdivide two hours under the control of an input time base oscillator for signal subdivision and control is well known per se to those skilled in the art. All decoders of the present invention can be constructed from a combination of logic circuits or a memory storing the desired decoding pattern.

The sync separator 33 outputs one pulse (
H output) and one pulse during each vertical synchronization period (V output). Horizontal sync pulse is counter 3
5 and restarts the counter decoders 35-40 from an initial state at the beginning of each line. Therefore, counter 35 responds to one oscillator 32 supplying a pulse to counting power 37 of counter 35.

Rapidly increases at an integer multiple of the color burst. The output of counter 35 is passed to a decoder 40 which provides pulses at a number of outputs to indicate the occurrence of various time intervals during each line period as counter 35 is monotonically increased from its initial state.

Provided as input.

Line counter 44 is cleared manually 45 by each vertical sync i4 pulse, and then each video line (via line subdivision decoder 40G output 41d)
As it is counted, it is incremented by the count input 46. The decoder 47 is.

Provides output information indicating the range of a particular line during the period between vertical sync pulses where a certain system function is required. Output 48 from decoder 47 and output 4 from decoder 40
1a-41c are collectively provided as inputs to multiplexer 20 and control a decoder which controls the multiplexer so that it produces the desired output information. Specifically, the decoder 40 has an output terminal 41a
To.

Horizontal/Yorusu period (period 110 in Figures 1A to IC)
-114).

The inverter 42 is used to transmit the inversion of the signal at the output terminal 41a, ie, the portion of the line other than the horizontal synchronization pulse, to the decoder. The decoder 40 has, at its output end 41b,
Multiplexer 20 generates a signal indicating the presence of periods 112-113 in each line in which a DC inverted reference level (see FIGS. 1B and 10) must be selected.

The output end 41e of the decoder 40 has a color burst 118
is passed to the video modulator 80 by the decoder 43
to the multiplexer 20, which is controlled by .

Counting control inputs to multiplexer 20.

The output terminal 48a of the decoder 47 indicates the range of vertical period lines (for example, 1 to 22) in which no two-inversion occurs. The remaining output 48b shown shows line 17 with a higher order decoding key modulated onto the color burst output of frequency divider 24.

The decoder 43 selects a desired one of the four inputs from the video modulator 80 depending on the pool value of the plurality of signals at the input control end.
Any circuit configuration can be used to allow the circuit to pass through.

According to one idea of the present invention, the line reversal/non-reversal operation is
It is controlled by a pseudo-random number generator 50 of known construction, such as a shift register 52 having the output of the selected stage connected to a shift register clock input 54 by exclusive OR circuits 58 and 59. Such a shift register/exclusive-or circuit combination is a well-known arrangement in itself for generating a unique predetermined binary sequence. A preset input 55 of the pseudo-random number generator 50 is supplied with the binary word of the output of the second pseudo-random number generator 63 . in each vertical sync period.

A vertical synchronization pulse is provided to the serial reset load shift register end 53 such that the shift register 52 is initialized to a stage controlled by the output of the second pseudo-random number generator 63 following each vertical retrace interval. Therefore, the particular binary sequence output from the pseudo-random number generator 50 corresponding to the video line reversal pattern is
is generated depending on the output of the pseudo-random number generator 63 during the reception of the clock input in each line following the vertical synchronization norm. In this way, generator 63 changes the line inversion/non-inversion and controls the encoding and decoding of the system.

Therefore, a receiver with an unauthorized receiver of FIG. 3, but who does not access the ongoing change/f meta of pseudorandom number generator 63, will not be able to receive coded video information.

The pseudo-random number generator 63 performs counting by dividing the vertical synchronization/IP pulse so that the random number generation encryption gloss turns change every few fields (by changing the line inversion/mother turn). Other methods of varying the output of generator 63 can also be used. The pseudorandom number generator 63 has a known configuration.

For example, it can be constructed as shown in detail as generator 50.

The output state of generator 63 is operatively passed to an encryptor 66 (e.g., a combinatorial or serial logic circuit with a fixed or variable encryption (signal variation) algorithm), which further inputs an encryption key. Scramble and pass through parallel-to-serial converter 67 to color burst modulation NAND gate 2
1. The clock for the parallel-to-serial converter (e.g. shift register) is supplied from the 9 oscillator 32 by the frequency divider 65 and the output 4sb of the line decoder 47 by the matching circuit 68 which operates during the appropriate (e.g. line 17) period.
obtained through. In this way, the decryption key required for decoding at the receiver side is conveyed via amplitude modulation on the force-to-strike subcarrier during the predetermined line 17 period.

In this way, the encryption/encoding device shown in FIG. It has a hierarchy of encryption keys and selectively inverts video information line by line using pseudo-random numbers. Even the device of the present invention cannot reproduce the data unless it is subsequently reproduced by the encryptor 66.

Referring to FIG. 3, a receiving device is shown for receiving and reconstructing television information images provided by a video source 10 of a transmitter. The demodulator 1-30 regenerates the input radio frequency wave and demodulates it into pace nine waves. A subsequent audio trap 131 removes audio subcarriers in the audio detected by audio receiver 133 . The baseband video (inverting and non-inverting line arrays) is provided to one of the differential amplifiers 138. Amplifier 138 (one form of which is shown in FIG. 4 and described below) produces a non-inverted output "+" at output 139 which is the same as the received line. Amplifier 138 also. A receive line with video information inverted with respect to the apparent +50 IRE amplitude is generated and provided to the 1 inverted "-" output 140.

Since the actual amplitude level of the received wave deviates somewhat from the DC voltage level when encryption is actually accomplished, the necessary inversion is not performed with respect to a fixed +5 Q IRE value, but rather with respect to the corresponding horizontal synchronization period. The inverted level pulse that occurs during (
116) in Figures 1B and IC diagrams with respect to the received amplitude. The timing and logic decoding circuit 150, which is the same as the circuit 30 in the head end (FIG. 2), is
An output signal is generated at the output end 151a during a period corresponding to periods 112-113 in the B and IC diagrams.

Timing circuit output “A” is sample hold circuit 14
4, the reception level of the pulse 116 is set to the circuit 144.
The remaining portion of the line is stored at the output of the differential amplifier 138 and operates in sampling mode during that period. Therefore, the video information at the 9-inverting output 140 is:

The difference between the received video and the received amplitude of pulse 116, which causes a proportional signal change with the video information, if any, and the absolute +5 Q IRE level until the received pulse amplitude deviates from that level. It's not a strict contrast. Therefore, outputs 139 and 1 of amplifier 138
The signal at 40 represents the non-inverting and restoring-reinverting output which reduces the decoding error to a substantially perceptible level. The non-inverted and inverted video signals are provided to video switches 147 and 149, respectively.

The video switch can consist of elements 2 which are known per se, for example FET switches.

As in the transmitter, timing and logic decoding circuit 150 generates the timing necessary for system decoding. ) output at output 151b has a line-by-line inverted/non-inverted signal comparable to the output of pseudo-random number generator 50 as supplied to decoder 43 of FIG. 2 during the encoding process. Inverter 155 inverts the non-inverting output at output 151b and operates switch 149 when the line is actually inverted at the transmitter head end operatively selecting the re-inverting output 140 to RF modulator 158. Therefore, the non-inverted signal output at output 151b operates switch 147 through AND gate 156 to select the non-inverted output at output 139 of time differential amplifier 138 where the line was not inverted. switch 147 or 1
The selection output of 49 is.

This results in a video baseband modulation that corresponds to the signal in the original video source 10. This baseband signal is provided to a radio frequency modulator 158 to increase its frequency to a standard television channel and then provided to a standard television set 160 for reception.

Timing circuit output 151a is an inverted AND gate 156
is connected to the blocking input terminal of 5 periods 112-113.
An inverted level A? that blocks non-inverted signals during 9 and does not form part of the normal television signal and is not supplied to the modulator 158 or receiver 160. Luz 116” is suppressed.Furthermore,
The sample and hold circuit 146 is the timing logic circuit 1
50 is excited by the output 151C of 1 normal horizontal sync level, e.g. period 11 of FIG. 1A before pulse 116.
Sansol in 5-115a. This level is supplied to switch 148, which switches.

interval 112-113 of nosolus 116 such that RF modulator 158 receives the horizontal sync voltage (apparently -40, actual value corresponding to an IRE value of 5) during interval 112-113.
Excited for . Thus, the decoded video input to RF modulator 158 substantially corresponds to the fully reconstructed standard video signal of FIG. 1A. The RF modulator 158 is also supplied with an audio program from the audio receiver 133 .

As mentioned above, the timing logic decoding circuit 150 essentially corresponds to the circuit 30 of FIG. to generate the same inverted/non-inverted pattern for receiver decoding as was used for encryption at the transmitter.

For this reason, the preset manual 55 of the shift register 52 in the second circuit 150 includes a pseudo random number generator 63 at the head end.
The same digital A' turn at the output of is provided. Therefore, an AM detector 165 tuned to the amplitude modulated color burst provided by modulator 20 at the transmitter decodes the encrypted information superimposed on the color burst in line 17 at the transmitter. AM detector 16
5 is connected to output 151 of circuit 150 in line 17.
The signal is serial-to-parallel converted by a converter 166 excited via d.

The converter output is provided as an input to decoder 180.

The decoder 18 is required to perform the inversion of the encryption done by the transmitter head end encoder 66 and register 1
Other decryption keys stored in 68 are also provided. Register 168 may be loaded through manually operated memory (eg, a single turn thumb switch) or preferably via an in-band or out-of-band communication channel. Decoder 180 operates on the pooled inputs provided by circuit elements 166 and 168 and generates the same preset signal available at the output of pseudorandom number generator 63 on the transmitter side. Decoder 180 is simply a combination of logic circuits, RO
M or other memory.

The device of FIG. 3 includes a timing circuit 150.

This circuit produces at its output 151b the same inverted/non-inverted signal sequence as is available at the output of the pseudo-random number generator 50 of the transmitter. This control signal controls the received video information (
The re-inverted received signal (amplifier output 140) is used to select between the non-inverted video at amplifier output 139 and the re-inverted received signal (amplifier output 140) by energizing the appropriate switch 147 or 149.
used to select. The reference inversion pulse 116 blocks both switches 147 and 149 during one period 112-113, and uses sample-and-hold circuit 146 to perform its function at the receiver and output its pulse during one period 112-113. Switch 148 is energized and then suppressed to replace the horizontal sync/IP level voltage.

Finally, referring to FIG. 4, there is shown a differential amplifier that can be used for the amplifier 138 (FIG. 3) of the present invention. This circuit consists of resistors 196 and 1 connected across the emitters.
Transistors 194 and 195 with collector resistors 191 and 192 equal to 98 are used. Resistor 198 is a potentiometer whose center tap is connected to a negative voltage via a current source 2, such as a transistor with a fixed base voltage and a series emitter resistor. Video information is one transistor.

For example, the base of transistor 194 is supplied with a scale rotation voltage, and the scale rotation voltage is supplied with the base of the other transistor. The non-inverting voltage is generated by a transistor (1
The 9 inverted level obtained at the collector of 95) is obtained from a transistor whose base is supplied with line video information. Assuming we match the values of transistors 191 and 192 and that the transistors have very large gains.

The gain of the inverting and non-inverting output amplifiers is the quotient of the collector resistance divided by the line resistance of the three emitter-to-emitter series resistors 196-198. Two more outputs are DC
It can be obtained in a wide frequency band from to video band. The gain and phase matching of the re-inverting and non-inverting signal paths and the linearity of the transmission path of the present invention ensure that the reconstructed signal, which is inverted at the headend and re-inverted at the receiver, is non-inverting to avoid image distortion. Since it must be practically equivalent to the signal.

is important.

The device of the present invention can only be received by a recipient who has the means to reproduce the 2-invert/non-invert encryption pattern.

A security system is provided for transmitting video information having an arrangement for selectively reconfiguring scrambled lines into a format viewed by a standard television receiver in response to an invert/non-invert control command.

The above description is merely a detailed description of the invention. It will be apparent to those skilled in the art that various modifications can be made without departing from the scope and spirit of the invention.

[Brief explanation of the drawing]

1A is a waveform diagram illustrating a baseband television signal line in a conventional format; FIG. 1B is a waveform diagram illustrating the line shown in FIG. 1A non-inverting according to the principles of the present invention; and FIG. Figure 2 is a block diagram showing a head-end/transmission station equipment for signal coding (scrambling); Figure 3 is a waveform diagram showing a video inversion line using the principle of Fig. 4 is a block diagram showing a signal decoding/receiving device capable of reproducing encoded signals, and Fig. 4 is a circuit diagram showing another example of the differential amplifier for use in the present invention.Explanation of symbols 10: video source, 12: automatic Gain control (AGC)/l)
C regeneration circuit, 33: synchronous separator, 11: amplifier, 13:
Inverting amplifier, 18: DC inverting reference level source, 20: Multiplexer, 32: Oscillator, 24: Frequency divider. 20a: modulator, 21: logical group), 80: video modulator, 43: decoder, 83: audio source, 84: modulator, 3
5, 44: Counter, 40, 47: Counter output state decoder, 30: Timing/logic circuit, 58, 59: Exclusive OR circuit, 52: Shift register, 50: Pseudo-random number generation circuit, 63: Pseudo-random number generator , 66: Encryptor'
+ 67: Parallel-serial converter, 65: Frequency divider, 68 matching circuit. 130: Demodulator, 131: Audio trap, 133: Audio receiver, 138: Differential amplifier, 150: Timing/logic decoding circuit, 147, 149: Video switch, 1
5'5: Inverter, 158: RF modulator, 160: Standard television camera), 146: Sample and hold circuit, 148: Switch. 165: AM detector, 166: converter, 168: register, 180: de;-da. 1. Indication of the case 1982 Patent Application No. 118.364 2. Title of the invention Video encryption device 5. Relationship with the case of the person making the amendment Patent applicant name General Instrument Corporation/4. Agent 105 Address 1-4-10 Nishi-Shinbashi, Minato-ku, Tokyo (2 others) 6. Subject of amendment 1) Drawing 2) Power of attorney and translation 3), Priority certificate and translation 1 Contents of amendment

Claims (20)

[Claims] (1) A selective inverting means for selectively inverting the video information content of a certain video line with respect to an inversion reference level and not inverting the video information content of other lines, and a signal distribution for distributing the output signal produced by the selective inverting means. and means for distributing the magnitude of the inverted reference level along with the composite signal distributed by the signal distributing means; and signal recovery decoding means for receiving the composite signal from the distributing means. means, the decoding means comprising: an inversion reference means for recovering the received inversion reference level; and means for selectively re-inverting the video information content of the inversion video line with respect to the recovered inversion reference of the inversion reference means. An encrypted video distribution device comprising: (2) Claim 1, wherein the inversion reference distribution means includes means for inserting a pulse having an amplitude representing the inversion reference level into a video line horizontal synchronization pulse interval.
The encrypted video distribution device described in Section 1. (3) the signal generation/encryption means further comprises first binary string generation means for controlling the selection inversion means; second binary string generation means for the signal recovery/decoding means to control the selection re-inversion means; and means for forcing said second binary sequence means to supply a sequence corresponding to that generated by said first binary sequence generating means. The encrypted video distribution device according to item 2). (4) An encrypted video distribution apparatus according to claim (3), wherein said first and second binary sequence generation means include first and second pseudo-random number generator means, respectively. (5) said first random number generator means comprises a shift register having a clock input and a plurality of outputs, exclusive OR means for connecting a selection of said outputs to said clock input, and a plurality of preset inputs; Encrypted video distribution according to claim 4, further comprising third pseudo-random number generator means having a terminal and a plurality of outputs connected to the preset input terminal of the shift register. Device. (6) further comprising control means for supplying a cryptographic key digital word for controlling said first pseudo-random number generator means, wherein said signal distribution means receives the cryptographic key digital word supplied by said control means; An encrypted video distribution device according to claim 4, comprising distribution means. (7) The signal recovery decoding means further comprises means for receiving the distributed cryptographic key digital word so as to synchronize the second binary sequence means with the first binary sequence means. The encrypted video distribution device according to item (6). (8) The control means further comprises means for encrypting the cryptographic key digital word.
The encrypted video distribution device according to item 6). (9) said selective inversion means includes operational amplifier means for generating non-inverted and inverted video information for a video line array, said signal distribution means and information reference level distribution means being connected to a reference level source and to said reference level source; 3. An encrypted video distribution device as claimed in claim 2 or 3, further comprising multiplexer means connected to each other and having inputs connected to the inverting and non-inverting outputs of said operational amplifier means. (10) The encrypted video distribution apparatus according to claim (9), wherein said signal generation and encryption means further comprises timing means for controlling said multiplexer. (11) An encrypted video distribution apparatus according to claim (10), comprising color burst modulation means connected to said multiplexer and means for supplying audio signal means to said signal distribution means. (12) The selective re-inverting means comprises means for generating an inverted version of the video information received by the decoding means and switching means for passing one or the other of the inverted or non-inverted received programs. The encrypted video distribution device according to scope item (2) or (3). (13) The decoding means further comprises timing means for controlling the switch means.
The encrypted video distribution device described in ). (14) Further comprising means for sampling and storing received video information during a horizontal synchronization period and additional switch means for energizing said switch means to operatively block while said inverted reference pulse is present. An encrypted video distribution device according to claim (12). (15) The selective re-inversion means comprises first and second transistors each having a base, emitter and collector terminal, a first resistance means connected to the transistor emitter terminal, and the transistor collector terminal. and means for providing video and inverted reference signals to the transistor base terminal, respectively, and means for providing video and inverted reference signals to the transistor base terminal. The encrypted video distribution device described in ). (16) receiving an encrypted video signal comprising an inverted reference level signal pulse and video information transmitted non-inverted or inverted with respect to the inverted reference level contained therein, and the selected inversion is commanded by an operational inversion column; a receiver comprising: means for generating non-inverted and re-inverted reproductions of received video information, said means for generating re-inverted reproductions responsive to a difference between the received video and a received reference level signal pulse; first and second switch means having differential amplifier means and a composite output and an input provided with non-inverting and re-inverting video information reproduction, and said operation for controlling said first and second switches. and control means for generating an inversion sequence. (17) A receiver according to claim (16), wherein said control means comprises a pseudo-random number generator cycled by received horizontal synchronization pulses. (18) The receiver according to claim 16 or 17, further comprising means for removing the inverted reference level signal pulse from the outputs of the first and second switch means. (19) An apparatus for decoding an encrypted video signal encrypted by the inversion of a selected video line with respect to an inverted reference level and including a signal representing the inverted reference level, the apparatus being responsive to the video signal and being responsive to the received inverting reference level storage means for providing a signal output representative of the inverted reference level signal included in the video signal; inverting amplifier means for inverting the selected video line of the video signal; is connected to the output signal from the reference level storage means and for inverting the selected video line with respect to the stored inverted level reference signal. (20) The decoding device according to claim 19, wherein the storage device includes a sample and hold circuit, and the inverting amplifier means includes a differential amplifier.