JPS613477A - Manufacture of semiconductor photodetector - Google Patents
Manufacture of semiconductor photodetectorInfo
- Publication number
- JPS613477A JPS613477A JP59123170A JP12317084A JPS613477A JP S613477 A JPS613477 A JP S613477A JP 59123170 A JP59123170 A JP 59123170A JP 12317084 A JP12317084 A JP 12317084A JP S613477 A JPS613477 A JP S613477A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- mask
- region
- type
- inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000007791 liquid phase Substances 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 16
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004781 supercooling Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体受光装置の製造方法、特にガードリング
を備えるアバランシホトダイオードの製造5方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor light receiving device, and particularly to an improvement in a method for manufacturing an avalanche photodiode provided with a guard ring.
光を情報信号の媒体とする光通信その他のシステムにお
いて、光信号を電気信号に変換する半導体受光装置は基
本的な構成要素の一つである0半導体受光装置のうち、
光電流がなだれ降伏によって増倍されるアバランシホト
ダイオード(以下APDと略称する)は光検知器の信号
対雑音比を改善する効果が大きい。このなだれ降伏を安
定して発生させる目的でガードリングを設けることが多
いが、とのAPDの特性向上のために製造方法の改善が
要望されている。In optical communications and other systems that use light as a medium for information signals, a semiconductor photodetector that converts an optical signal into an electrical signal is one of the basic components.
An avalanche photodiode (hereinafter abbreviated as APD) whose photocurrent is multiplied by avalanche breakdown is highly effective in improving the signal-to-noise ratio of a photodetector. A guard ring is often provided for the purpose of stably generating this avalanche breakdown, but there is a demand for an improvement in the manufacturing method in order to improve the characteristics of the APD.
例えば光通信用の半導体受光装置としては、波長1.3
乃至1.65μm程度の帯域に適合することが必要であ
る。For example, as a semiconductor light receiving device for optical communication, the wavelength is 1.3.
It is necessary to adapt to a band of about 1.65 μm.
第2図(a)はこの波長帯域に適合するAPDの1従来
例を示す断面図である。FIG. 2(a) is a sectional view showing one conventional example of an APD suitable for this wavelength band.
図において、21はn+WInP基板、22はn型In
GaAs光吸収層、23はIl型InP凰 24はn型
InP#に形成されたp+型領領域25はp型ガードリ
ング領域、26は反射防止膜、27は保護絶縁膜、28
はp@J電極、29はnglQ電極を示す。In the figure, 21 is an n+WInP substrate, 22 is an n-type InP substrate, and 22 is an n-type InP substrate.
23 is a GaAs light absorption layer, 23 is an Il-type InP film, 24 is a p + type region 25 formed in n-type InP#, is a p-type guard ring region, 26 is an antireflection film, 27 is a protective insulating film, 28
indicates p@J electrode, and 29 indicates nglQ electrode.
このAPDKn側電極29を正、p側電極28を負の極
性とする高い逆バイアス電圧を印加して、光吸収層22
内で入力信号光によって励起された正孔を一次キャリア
とするなだれ降伏をn型InP層23のpn接合近傍で
発生させる。A high reverse bias voltage is applied to make the APDK n-side electrode 29 positive and the p-side electrode 28 negative.
Avalanche breakdown occurs in the vicinity of the pn junction of the n-type InP layer 23 using holes excited by the input signal light as primary carriers.
ガードリング領域25は、通常円形であるp+型領領域
24周囲にこれよりも深く形成されており、前記なだれ
降伏より低い電圧で発生するおそわが多いp+型領領域
24周辺での降伏を防止することを目的としている。The guard ring region 25 is formed deeper than this around the normally circular p+ type region 24, and prevents breakdown around the p+ type region 24, which is likely to occur at a voltage lower than the avalanche breakdown. The purpose is to
この従来例の如くガードリングを備えたAPDの製造方
法として、従来p+型領領域4とp型ガードリング領域
25との何れか一方の領域を選択するマスクをnff1
”導体#23上に設けて、拡散或いはイオン注入法によ
る不純物の導入をそれぞれ別々に行なう方法が多く行な
われている。As a manufacturing method of an APD equipped with a guard ring as in this conventional example, a mask for selecting either one of the p+ type region 4 and the p type guard ring region 25 is conventionally used.
``Many methods are used in which impurities are provided on conductor #23 and impurities are introduced separately by diffusion or ion implantation.
この製造方法では2度の不純物導入処理を必要とし、か
つ、不純物濃度、拡散深さ、拡散の横方向の拡がりなど
をそれぞれの場合について厳密に制御する必要がある。This manufacturing method requires impurity introduction treatment twice, and it is necessary to strictly control the impurity concentration, diffusion depth, lateral spread of diffusion, etc. in each case.
この問題点に対処するために、ガードリングを埋め込み
成長層によって形成する製造方法が、例えば特開昭55
−99782によって提供されている。In order to deal with this problem, a manufacturing method in which the guard ring is formed by a buried growth layer has been developed, for example, in Japanese Patent Laid-Open No. 55
-99782.
該製造方法によれば、第2図(b)の断面図に示す如く
、半導体に2層32およびn層33を形成して接合を形
成し、次にこの半導体の表面に、例えばSin、を塗布
し、これを適当な方法によって選択的にエツチングして
所望の大きさに残し、マスク36とする。このマスク3
6を利用し図に示したように、マスク36に被われてい
ない部分の半導体層をpn接合面34が露出する以上に
深く−までエツチングする。According to this manufacturing method, as shown in the cross-sectional view of FIG. 2(b), a double layer 32 and an n-layer 33 are formed on the semiconductor to form a junction, and then, for example, Sin is coated on the surface of the semiconductor. This is then selectively etched using an appropriate method to leave a desired size as a mask 36. This mask 3
6, as shown in the figure, the portion of the semiconductor layer not covered by the mask 36 is etched to a depth deeper than the pn junction surface 34 is exposed.
次にこの半導体層上に選択的にエピタキシャル成長を行
なう0このエピタキシャル成長によりマスクを除いた半
導体露出部のみに新たな半導体層35が成長するが、そ
の不純物濃度、結晶組成などを制御して、この成長層3
5をガードリングとして動作させている。Next, epitaxial growth is selectively performed on this semiconductor layer. Through this epitaxial growth, a new semiconductor layer 35 is grown only on the exposed semiconductor part excluding the mask. layer 3
5 is operated as a guard ring.
しかしながら該製造方法に従い液相エピタキシャル成長
方法によって形成したガードリングには下記の問題点が
おる。However, the guard ring formed by the liquid phase epitaxial growth method according to this manufacturing method has the following problems.
まず埋め込み成長層の5in2マスク36の近傍に、第
2図(c)に模式的に例示する如く波紋状の起伏37が
現われるなど、成長層表面のモホロジーが良好でけ々い
。First, near the 5in2 mask 36 of the buried growth layer, ripple-like undulations 37 appear as schematically illustrated in FIG. 2(c), and the morphology of the surface of the growth layer is excellent.
これはエピタキシャル成長層に、特に重要な成長界面近
傍において歪を生じ、不均一になっていることの現われ
である。This is a sign that the epitaxially grown layer is strained and non-uniform, especially near the important growth interface.
半導体受光装置の受光領域は通常円形とされており、埋
め込み成長層の界面は結晶方向が周期的に変化する状態
となっている。これは半導体レーザのストライプ領域を
埋込むエピタキシャル成長とけ大きく異なる点であるが
、この様に結晶方向が変化する面上へのエピタキシャル
成長に9いてはなお問題が多い。The light-receiving region of a semiconductor light-receiving device is usually circular, and the crystal direction of the interface of the buried growth layer changes periodically. Although this is significantly different from epitaxial growth for filling the striped region of a semiconductor laser, there are still many problems in epitaxial growth on a surface where the crystal direction changes in this way.
また前記発明の如く埋め込み成長層全体をガードリング
とすることは、接合容量を極めて大きくする結果となる
。Furthermore, using the entire buried growth layer as a guard ring as in the invention results in an extremely large junction capacitance.
上述の如く、半導体受光装置の受光領域を埋め込む選択
的エピタキシャル成長は結晶方向が変化する面上へのエ
ピタキシャル成長であるが、受光装置の特性を向上し再
現性を改善するために、埋め込み層の特に界面近傍の結
晶性の改善が必要である。As mentioned above, selective epitaxial growth for burying the light-receiving region of a semiconductor light-receiving device is epitaxial growth on a surface where the crystal direction changes. It is necessary to improve the crystallinity in the vicinity.
前記問題点は、半導体基体上側受光領域を被覆するマス
クを設けて、該半導体基体の該領域の周囲を選択的に除
去し、次いで該領域を埋め込む半導体層を液相エピタキ
シャル成長するに際して、前記マスクを窒化シリコンを
用いて形成する本発明による半導体受光装置の製造方法
によ抄解決される。The problem is that when a mask is provided to cover the upper light-receiving region of the semiconductor substrate, the periphery of the region of the semiconductor substrate is selectively removed, and then a semiconductor layer to fill the region is grown by liquid phase epitaxial growth, the mask is removed. This problem is solved by a method of manufacturing a semiconductor light receiving device according to the present invention, which is formed using silicon nitride.
本発明においては、受光領域を被覆するマスクを窒化シ
リコンによって形成して、選択的エッチング及び液相エ
ピタキシャル成長を実施する。In the present invention, selective etching and liquid phase epitaxial growth are performed using a mask made of silicon nitride that covers the light-receiving region.
窒化ンリコン膜けSiO□膜等よし柔軟性があり、エピ
タキシャル成長層に及ぼすストレスが緩和される。Silicon nitride films, SiO□ films, etc. are flexible, and the stress exerted on the epitaxial growth layer is alleviated.
なお窒化シリコン膜はプラズマ化学気相成長方法によっ
て形成することが望ましく、その厚さは60nm以上で
かつ200nm以下が望ましい。Note that the silicon nitride film is preferably formed by a plasma chemical vapor deposition method, and its thickness is preferably 60 nm or more and 200 nm or less.
以下本発明を第1図の工程順断面図に示す実施例により
具体的に説明する。The present invention will be specifically explained below with reference to embodiments shown in step-by-step cross-sectional views in FIG.
第1図(a)参照
n型InP基板1上に下記の半導体層2〜4を連続して
エピタキシャル成長する。2は不純物濃度I X 10
”cm−3+厚さ2μm程度のn型InGaAs層、3
はこれと同等の不純物濃度で厚さ05μm程度のn型I
nGaAsP層、4も同等の不純物濃度で厚さ3μm程
度のn型InP層である。Referring to FIG. 1(a), the following semiconductor layers 2 to 4 are successively epitaxially grown on an n-type InP substrate 1. 2 is the impurity concentration I x 10
"cm-3 + n-type InGaAs layer with a thickness of about 2 μm, 3
is an n-type I with an impurity concentration equivalent to this and a thickness of about 05 μm.
The nGaAsP layer 4 is also an n-type InP layer with the same impurity concentration and a thickness of about 3 μm.
なおInGaAsPnGaAs層2As層2からInP
n種層の正孔の注入を容易にするために設けている0
第1図(b)参照
InP層4上に受光領域を被覆す、るマスク5を設ける
。Note that InGaAsPnGaAs layer 2As layer 2 to InP
A mask 5 covering the light-receiving region is provided on the InP layer 4 provided to facilitate the injection of holes into the n-type layer (see FIG. 1(b)).
本実施例においては、プラズマ化学気相成長方法によっ
て厚さ約1100nの窒化シリコン膜を形成し、これを
リングラフィ法によってパターニングして、直径約10
0μmの円形のマスク5を形成している。In this example, a silicon nitride film with a thickness of about 1100 nm was formed by plasma chemical vapor deposition, and this was patterned by phosphorography to have a diameter of about 10 nm.
A circular mask 5 of 0 μm is formed.
次いでメルトバック又は化学エツチング法等によって、
図に示す如く受光領域の周囲を除去してメサ形とする。Then, by melt-back or chemical etching method, etc.
As shown in the figure, the periphery of the light receiving area is removed to form a mesa shape.
この際にn型InPMf4を例えば0.5μm程度残置
する。At this time, for example, about 0.5 μm of n-type InPMf4 is left.
第1図(c)参照
埋め込み層として、例えば不純物濃度lXl01!″(
m −’程度のn型InP層6を液相エピタキシャル成
長する。このInP層6を成長させるInPn種層表面
を劣化させないために、先のメサ形成をメルトバックに
よって行ない、直チにInP層6を成長させることが望
ましく、本実施例においては、メルトバックを温度65
0℃においてIn溶媒中のInPの未飽和度2℃の溶液
で行ない、連続してInP層6の成長を過冷却度5℃の
InPのIn溶液によって実施している。As the reference buried layer in FIG. 1(c), for example, the impurity concentration lXl01! ″(
An n-type InP layer 6 having a thickness of approximately m −' is grown by liquid phase epitaxial growth. In order to avoid deteriorating the surface of the InPn seed layer on which this InP layer 6 is grown, it is desirable to perform the previous mesa formation by meltback and then grow the InP layer 6 immediately. 65
The growth of the InP layer 6 is carried out using a solution of InP in an In solvent at an unsaturated level of 2°C at 0°C, and the InP layer 6 is continuously grown using an In solution of InP at a supercooling level of 5°C.
第1図(d)参照
マスク5を除去しマスク7を設けて、アクセプタ不純物
の拡散を行なう。アクセプタ不純物としては例えばカド
ミウム(Cd ) 、亜鉛(Z’n)等を用いる。FIG. 1(d) The reference mask 5 is removed and a mask 7 is provided to diffuse acceptor impurities. As the acceptor impurity, for example, cadmium (Cd), zinc (Z'n), etc. are used.
この拡散によって、受光領域のInPn種層埋め込み層
であるInPJM6とにまたがってp型頭域が形成され
るが、InP#6はn型の不純物濃度がI X 10
l5cWL−’程度であるために不純物拡散の裾の領域
までがp型領域9となり、ガードリングを構成する。Due to this diffusion, a p-type head region is formed across InPJM6, which is the InPn seed layer buried layer in the light-receiving region, but the n-type impurity concentration of InP#6 is I x 10.
Since it is about l5cWL-', the area up to the bottom region of the impurity diffusion becomes the p-type region 9, forming a guard ring.
他方InP層4はこれよりは高不純物濃度であるために
受光領域のp属領域8は領域9より浅い。On the other hand, since the InP layer 4 has a higher impurity concentration than this, the p-group region 8 of the light receiving region is shallower than the region 9.
本実施例においては、はぼ均一な濃度が得られる高濃度
部分を] X 10 ’7”以上とし、領域8は約1.
5μm、領域9は約2μmの深さとしてbる。In this embodiment, the high density area where a fairly uniform density can be obtained is larger than 10'7", and the area 8 is about 1.
5 μm, and region 9 is approximately 2 μm deep.
第1図(社)参照
従来技術によって反射防止膜10.保護絶縁膜11、p
側電極12及びn側電極13を設ける。Refer to FIG. 1 (Corporation) Anti-reflection coating 10 according to the prior art. Protective insulating film 11, p
A side electrode 12 and an n-side electrode 13 are provided.
以上説明した実施例において、マスク5とする窒化シリ
コン膜をプラズマ化学気相成長方法で形成しているが、
この製造方法によれば既にしばしば報告されている如く
、シリコン及び窒素以外の元素が膜に含まれて柔軟性が
増している。In the embodiments described above, the silicon nitride film serving as the mask 5 is formed by plasma chemical vapor deposition.
According to this manufacturing method, as has been often reported, elements other than silicon and nitrogen are included in the film, increasing its flexibility.
また窒化シリコン膜の厚さが60nm未満である場合に
はこれにピンホールを生ずる可能性が多く、200nm
を超える場合には剛性が大きく成長時の熱ひずみによっ
てマスクが割れるなどの障害を招き易い。Furthermore, if the thickness of the silicon nitride film is less than 60 nm, there is a high possibility that pinholes will occur in it;
If the mask exceeds 100%, the rigidity becomes large and problems such as cracking of the mask due to thermal strain during growth are likely to occur.
この様な配慮の下で窒化シリコンマスクを用いることに
よって、埋め込み層の不均一、結晶のひずみ及びパター
ンの変形等のないエピタキシャル成長を実現することが
できる。By using a silicon nitride mask with such consideration, epitaxial growth can be achieved without unevenness of the buried layer, distortion of the crystal, deformation of the pattern, etc.
以上1548Aした如く本発明の製造方法によって、受
光領域を埋め込む半導体層を欠陥なくエピタキシャル成
長することが可能となり、良好なガードリング効果によ
って優れた特性のAPDを提供することができる。As described above, the manufacturing method of the present invention makes it possible to epitaxially grow the semiconductor layer burying the light-receiving region without defects, and provides an APD with excellent characteristics due to the good guard ring effect.
第1図は本発明の実施例を示す工程順断面図、第2図(
a)及び(b)は従来例の断面図、同図(c)はその要
部平面図である。
図において、
■はn型InP基板、 2はn型InGaAa層、3
はn型InGaAsP層、4はn型InP層、5は−r
スク、 6はn型InP層、8はp型頭域
9はp型ガードリング領域、10は反射防止膜、
11は保護絶縁膜、12はpflll電極
13はn側電極、を示す。 −
第 1 ■
第 1 図
第 2 図Fig. 1 is a cross-sectional view showing an embodiment of the present invention in the order of steps, and Fig. 2 (
Figures a) and (b) are cross-sectional views of the conventional example, and figure (c) is a plan view of the main parts thereof. In the figure, ■ is an n-type InP substrate, 2 is an n-type InGaAa layer, and 3 is an n-type InP substrate.
is an n-type InGaAsP layer, 4 is an n-type InP layer, 5 is -r
6 is n-type InP layer, 8 is p-type head area
9 is a p-type guard ring region, 10 is an antireflection film,
11 is a protective insulating film, 12 is a pflll electrode
13 indicates an n-side electrode. - Part 1 ■ Fig. 1 Fig. 2
Claims (3)
て、該半導体基体の該領域の周囲を選択的に除去し、次
いで該領域を埋め込む半導体層を液相エピタキシャル成
長するに際して、前記マスクを窒化シリコンを用いて形
成することを特徴とする半導体受光装置の製造方法。(1) A mask covering a light-receiving region is provided on a semiconductor substrate, the area around the region of the semiconductor substrate is selectively removed, and then the mask is nitrided when a semiconductor layer to fill the region is grown by liquid phase epitaxial growth. A method for manufacturing a semiconductor light receiving device, characterized in that it is formed using silicon.
学気相成長方法によって堆積することを特徴とする特許
請求の範囲第1項記載の半導体受光装置の製造方法。(2) The method of manufacturing a semiconductor light receiving device according to claim 1, wherein the silicon nitride used for the mask is deposited by a plasma chemical vapor deposition method.
m以下とすることを特徴とする特許請求の範囲第2項記
載の半導体受光装置の製造方法。(3) The thickness of the mask is 60 nm or more and 200 nm
3. The method of manufacturing a semiconductor light-receiving device according to claim 2, wherein the distance is less than or equal to m.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59123170A JPS613477A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor photodetector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59123170A JPS613477A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor photodetector |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS613477A true JPS613477A (en) | 1986-01-09 |
Family
ID=14853911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59123170A Pending JPS613477A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor photodetector |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS613477A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57136319A (en) * | 1981-02-17 | 1982-08-23 | Toshiba Corp | Selective growing method for crystal |
JPS5891687A (en) * | 1981-11-26 | 1983-05-31 | Fujitsu Ltd | Manufacture of light-receiving element |
-
1984
- 1984-06-15 JP JP59123170A patent/JPS613477A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57136319A (en) * | 1981-02-17 | 1982-08-23 | Toshiba Corp | Selective growing method for crystal |
JPS5891687A (en) * | 1981-11-26 | 1983-05-31 | Fujitsu Ltd | Manufacture of light-receiving element |
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