JPS6133547A - ベクトル・レジスタのオ−バフロ−情報通知方式 - Google Patents

ベクトル・レジスタのオ−バフロ−情報通知方式

Info

Publication number
JPS6133547A
JPS6133547A JP15448484A JP15448484A JPS6133547A JP S6133547 A JPS6133547 A JP S6133547A JP 15448484 A JP15448484 A JP 15448484A JP 15448484 A JP15448484 A JP 15448484A JP S6133547 A JPS6133547 A JP S6133547A
Authority
JP
Japan
Prior art keywords
vector
loop
registers
vector register
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15448484A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0512752B2 (enrdf_load_stackoverflow
Inventor
Takahiro Ishitani
石谷　隆広
Yukio Kamiya
幸男 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15448484A priority Critical patent/JPS6133547A/ja
Publication of JPS6133547A publication Critical patent/JPS6133547A/ja
Publication of JPH0512752B2 publication Critical patent/JPH0512752B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)
JP15448484A 1984-07-25 1984-07-25 ベクトル・レジスタのオ−バフロ−情報通知方式 Granted JPS6133547A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15448484A JPS6133547A (ja) 1984-07-25 1984-07-25 ベクトル・レジスタのオ−バフロ−情報通知方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15448484A JPS6133547A (ja) 1984-07-25 1984-07-25 ベクトル・レジスタのオ−バフロ−情報通知方式

Publications (2)

Publication Number Publication Date
JPS6133547A true JPS6133547A (ja) 1986-02-17
JPH0512752B2 JPH0512752B2 (enrdf_load_stackoverflow) 1993-02-18

Family

ID=15585250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15448484A Granted JPS6133547A (ja) 1984-07-25 1984-07-25 ベクトル・レジスタのオ−バフロ−情報通知方式

Country Status (1)

Country Link
JP (1) JPS6133547A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0675816A (ja) * 1992-08-24 1994-03-18 Nec Corp ループ処理誤り検出装置
JP2010160594A (ja) * 2009-01-07 2010-07-22 Meidensha Corp ソフトウェアの開発支援システム、開発支援方法およびプログラム
JP2018521422A (ja) * 2015-07-31 2018-08-02 エイアールエム リミテッド ベクトル長クエリ命令

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109085A (en) * 1980-12-26 1982-07-07 Fujitsu Ltd System for optimizing object program of parallel computer
JPS58149565A (ja) * 1982-02-27 1983-09-05 Fujitsu Ltd ベクトル・レングス制御範囲分割処理方式

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109085A (en) * 1980-12-26 1982-07-07 Fujitsu Ltd System for optimizing object program of parallel computer
JPS58149565A (ja) * 1982-02-27 1983-09-05 Fujitsu Ltd ベクトル・レングス制御範囲分割処理方式

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0675816A (ja) * 1992-08-24 1994-03-18 Nec Corp ループ処理誤り検出装置
JP2010160594A (ja) * 2009-01-07 2010-07-22 Meidensha Corp ソフトウェアの開発支援システム、開発支援方法およびプログラム
JP2018521422A (ja) * 2015-07-31 2018-08-02 エイアールエム リミテッド ベクトル長クエリ命令
US11314514B2 (en) 2015-07-31 2022-04-26 Arm Limited Vector length querying instruction

Also Published As

Publication number Publication date
JPH0512752B2 (enrdf_load_stackoverflow) 1993-02-18

Similar Documents

Publication Publication Date Title
KR100505799B1 (ko) 코프로세서 데이터 액세스 제어
US7386844B2 (en) Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions
US8893095B2 (en) Methods for generating code for an architecture encoding an extended register specification
JP3983857B2 (ja) ベクトルレジスタの複数バンクを用いた単一命令複数データ処理
US6301653B1 (en) Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks
JP3847672B2 (ja) コンパイラ装置及びコンパイル方法
US8370817B2 (en) Optimizing scalar code executed on a SIMD engine by alignment of SIMD slots
CN101495959A (zh) 组合微处理器内的多个寄存器单元的方法和系统
KR100500889B1 (ko) 데이터 처리장치에서의 레지스터 어드레싱
US7013321B2 (en) Methods and apparatus for performing parallel integer multiply accumulate operations
US5333284A (en) Repeated ALU in pipelined processor design
US8856759B2 (en) Method and apparatus providing COBOL decimal type arithmetic functions with improved performance
EP2799986A1 (en) Apparatus and method for translating multithread program code
JPS6133547A (ja) ベクトル・レジスタのオ−バフロ−情報通知方式
US5987597A (en) Data processor with execution control for first and second execution units
KR20000048531A (ko) 데이터 처리장치에서의 입력 오퍼랜드 제어
KR20000048528A (ko) 데이터 처리 조건 코드 플래그
Hong et al. The design of the SACLIB/PACLIB kernels
JP3175768B2 (ja) 複合型命令スケジューリング処理装置
KR19980018071A (ko) 멀티미디어 신호 프로세서의 단일 명령 다중 데이터 처리
Ling A set of high-performance level 3 BLAS structured and tuned for the IBM 3090 VF and implemented in Fortran 77
Shaw et al. Performance tuning scientific codes for dataflow execution
JP3276479B2 (ja) コンパイル方式
Moraes et al. R8 Processor Architecture and Organization Specification and Design Guidelines
JP2862969B2 (ja) プロセッサ