JPS6133154B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital sequential timer device that automatically controls sequentially turning on and off electricity to electrical equipment.

In conventional sequential control timer devices, the time interval settings for each energized state or de-energized state are fixed, or even if they can be adjusted, they can only be adjusted roughly, making it difficult to adjust the time intervals accurately and easily. I couldn't do it.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to allow arbitrarily selected time intervals to be reset as necessary over an extremely wide time range, and to provide two types of time intervals. By setting the time intervals, it is possible to arbitrarily change the two time intervals of the active time and inactive time of the time-limited control elements that are to be operated sequentially, and the duty thereof, and the above-mentioned sequential control can be programmed in real time. An object of the present invention is to provide a digital sequential timer device suitable for integration into an integrated circuit.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital sequential timer device of the present invention.
In FIG. 1, reference numeral 1 designates a frequency dividing circuit which is supplied with a clock pulse outputted from, for example, a crystal oscillation circuit through a terminal 2, divides the frequency of this pulse, and outputs a reference pulse serving as a time reference. The reference pulse here is, for example, 1/10 with an appropriate pulse width.
This may be a 0 second pulse or a 1 minute pulse. The reference pulse output from the frequency dividing circuit 1 is supplied to an arithmetic circuit 3 that performs subtraction. 4 is a time interval setting memory circuit, and this time interval setting memory circuit 4 temporarily stores each of the two types of time intervals set in the time interval setting circuit 5 and the above-mentioned time interval setting circuit 5. It is composed of storage registers 6 and 7 for storing data. The two types of time intervals temporarily stored in the storage registers 6 and 7 are transferred to the calculation registers 10 and 11 via gate circuits 8 and 9, respectively.
is supplied to The two types of time intervals supplied to the arithmetic registers 10 and 11 are subtracted by the time of the reference pulse in the arithmetic circuit 3 and fed back to the arithmetic registers 10 and 11 again. Reference numeral 12 denotes a time-up signal generation circuit, and this time-up signal generation circuit 12 outputs a time-up signal for controlling the gate circuits 8 and 9 according to the content time of the arithmetic registers 10 and 11. The signal is supplied to the arithmetic circuit 3 and two OR gates 13 and 14. Further, the OR gate 13 is supplied with a start signal output from a start signal generation circuit 15, and the OR gate 14 is supplied with a reset signal output from a reset signal generation circuit 16. Further, a start signal and a reset signal outputted from the start signal generating circuit 15 and the reset signal generating circuit 16, respectively, are supplied to the arithmetic circuit 3. The output of the OR gate 13 and the output of the OR gate 14 are supplied to a set input terminal and a reset input terminal of a timer control signal generation circuit 17, respectively. The timer control signal generation circuit 17 has an output terminal 18
A time-limited control element is connected to, for example, outputs a control signal that makes the time-limited control element active when set, and outputs a control signal that makes the time-limited control element inactive when one side is reset. .

Next, the operation of the circuit configured as described above will be explained using the time chart shown in FIG. 2.
First, a clock pulse is inputted to the frequency dividing circuit 1 via the terminal 2, and two arbitrary different time intervals T ₁ and T ₂ are respectively set in the time interval setting circuit 5. After setting, memory registers 6 and 7 are set to each time interval.
In addition to temporarily storing T ₁ and T ₂ , the gate circuit 8,
9 opens and the time interval is passed through this gate circuit 8 and 9.
T ₁ and T ₂ are output to calculation registers 10 and 11,
After this, the calculation registers 10 and 11 are set at the time interval.
Store T ₁ and T ₂ respectively. Next, at time _t0 , the start signal generation circuit 15 is activated. After operation, the start signal generation circuit 15 outputs a start signal to the OR gate 13 and the arithmetic circuit 3. The start signal input to the OR gate 13 is input to the set input terminal of the timer control signal generation circuit 17. Thereafter, the timer control signal generation circuit 17 outputs a control signal at the active voltage level via the terminal 18. Therefore, at time _t=0, the time control element connected to terminal 18 becomes active as shown in FIG. After the one-way start signal generating circuit 15 is activated, the arithmetic circuit 3 calculates the time interval stored in the arithmetic register 10.
The time of the reference pulse of the frequency dividing circuit 1 is sequentially subtracted from _T1 , and the subtracted time interval is fed back to the calculation register 10. Next, at _t1 when the time interval _T1 has elapsed from _t0 , when the remaining time interval of the calculation register 10 becomes 0, the time-up signal generation circuit 12 outputs the first time-up signal.
The time-up signal output from the time-up signal generation circuit 12 is input to the OR gate 14, the gate circuit 8, and the arithmetic circuit 3. The time-up signal input to the OR gate 14 is input to the reset terminal of the timer control signal generation circuit 17. When the time-up signal is input to the reset terminal, the timer control signal generation circuit 17 outputs a control signal at an inactive voltage level to the time control element via the terminal 18. Therefore, at t ₁ , which has elapsed from t ₀ to T ₁ ,
The timed control element becomes inactive as shown in FIG. After the first time-up signal is input at the same time, the calculation circuit 3 sequentially subtracts the reference pulse time of the frequency dividing circuit _{1 from the storage time interval T 2 of} the calculation register 11 in which the other time interval T 2 is stored. and calculate the time interval after subtraction again in calculation register 1.
At the same time, the subtraction from one arithmetic register 10 is stopped. Furthermore, after the first time-up signal is input, the gate circuit 8 transfers one time interval T ₁ stored in the storage register 6 to the calculation register 10 . Thereafter, the arithmetic circuit 3 sequentially subtracts the reference pulse time from the time interval _T2 stored in the arithmetic register 11. and from t ₁ to t ₂
At _t2 , when the time interval has elapsed, the remaining time interval in the calculation register 11 becomes 0, and the time-up signal generation circuit 12 outputs the time-up signal for the second day. The above time-up signal generation circuit 12
The second time-up signal output from the circuit is input to the OR gate 13, the gate circuit 8, and the arithmetic circuit 3. The time-up signal input to the OR gate 13 is input to the set end of the timer control signal generation circuit 17. When the time-up signal is input to the set terminal, the timer control signal generating circuit 17 again outputs a control signal at the active voltage level to the time control element via the terminal 18. Therefore from t ₁
At t ₂ , after a time interval of T ₂ has elapsed, the timed control element becomes active again as shown in FIG. After the second time-up signal is input at the same time,
The arithmetic circuit 3 sequentially subtracts the reference pulse time of the frequency dividing circuit ₁ from the time interval T ₁ stored in the arithmetic register 10 in which one time interval T 1 is stored, and stores the subtracted time interval in the arithmetic register again. 10, and the subtraction from the other arithmetic register 11 is stopped. Furthermore, after the second time-up signal is input, the gate circuit 9 converts the other time interval _T2 stored in the storage register 7 into the calculation register 1.
Transfer to 1. Below is the time-up signal generation circuit 1
By outputting the even-numbered time-up signals from the time-up signal generation circuit 12, the time control element connected to the terminal 18 becomes active at the time interval _T1 , while the odd-numbered time-up signals are output from the time-up signal generation circuit 12. By this, the timed control element is
It becomes inactive within a time interval of T ₂ . Next, by activating the reset signal generation circuit 16 and inputting the reset signal to the timer control signal generation circuit 17 via the arithmetic circuit 3 and the OR gate 14, the arithmetic circuit 3 stops the subtraction and starts generating the timer control signal. Circuit 17 outputs an inactive voltage level control signal to the timed control element via terminal 18 regardless of the previous output state. Therefore, all circuit operations stop at this time. The period of each active state and inactive state of the externally connected time control element is set digitally by the time interval setting circuit 5, for example, from 1/100 seconds to 1000 seconds.
It can be arbitrarily set within an extremely wide range of time, and since the circuit is operated digitally, the time control element can be turned on and off extremely accurately. Furthermore, since two types of time intervals are set in the time interval setting circuit 5, it is possible to arbitrarily change the two time intervals of the active time and inactive time of the time control elements that are to be operated sequentially, and the duty thereof. . Furthermore, since the above circuit does not include any analog elements, it is ideal for semiconductor integrated circuit implementation.

In the above embodiment, the arithmetic circuit 3 includes the arithmetic register 1
Two types of time intervals T ₁ and T ₂ stored at 0 and 11
The case has been described in which the time of the reference pulse is sequentially subtracted from the reference pulse, but as shown in FIG. The time-up signal generating circuit 12 is replaced with clear circuits 19 and 20 that clear the memory contents of the arithmetic registers 10 and 11, and the time-up signal generating circuit 12 clears the memory contents of the memory registers 6 and 7 and the arithmetic registers 10 and 1.
1 and output a time-up signal when the two match. Also, at this time, the arithmetic circuit 3 performs addition. That is, the time of the reference pulse is sequentially added to the calculation registers 10 and 11 starting from 0. In this case as well, sequential control as shown in the time chart of FIG. 2 is performed as in the case of subtraction.

FIG. 4 is a block diagram showing another embodiment of the present invention. The circuit shown in FIG. 4 has the circuit configuration shown in FIG. A time display unit 22 that displays the supplied current time, a time setting circuit 23 that arbitrarily sets two types of time, and storage registers 24 and 25 that store the two types of time set by this time setting circuit 23 (note that , the time setting circuit 23 and the two storage registers 24,
25 constitutes a time setting storage circuit 26 ), the time stored in the storage registers 24 and 25 and the current time output from the clock circuit 21 are compared, and the time setting circuit 23 sets the time. The configuration is such that a coincidence signal generation circuit 27 is added, which detects that the current time and the current time match each other, and outputs a coincidence signal. Further, in the circuit configuration shown in FIG. 4, the start signal generation circuit 1
5. The reset signal generating circuit 16 is omitted, and instead, one output of the coincidence signal generating circuit 27 is supplied to the arithmetic circuit 3 and the OR gate 13, and the other output is supplied to the arithmetic circuit 3. and is supplied to the OR gate 14.

The circuit configured as described above operates as follows. First, a clock pulse is input to the frequency divider circuit 1 via the terminal 2. The frequency dividing circuit 1 divides the frequency of the input clock pulse and outputs a reference pulse. Here, the reference pulse output from frequency divider circuit 1 is
Assume that the pulse is 512Hz. The basic pulses output from the frequency dividing circuit 1 are supplied to the arithmetic circuit 3 and the clock circuit 21, respectively. The timekeeping circuit 21 is composed of, for example, a binary counter, a decimal counter, and a hexadecimal counter connected in cascade in nine stages, and divides the input reference pulse into 1-second digits, 10-second digits, 1-minute digits, 10-minute digits, Outputs a clock signal corresponding to each digit of the hour digit. The clock signal output from the clock circuit 21 is input to the time display section 22 and the coincidence signal generation circuit 27, respectively. The time display section 22 sequentially displays the current time according to the input clock signal. On the other hand, the time setting circuit 23 sets two types of times: a time t _s to start the sequence control of the time limit control element and a time t _e to end it. The above two types of times t _s and t _e
After setting, each time t _s and t _e are stored in memory register 2.
4, 25. Then, after a certain period of time has passed and the time measured by the clock circuit 21 matches the time _ts stored in the storage register 24, the coincidence signal generation circuit 27 generates the first coincidence signal and the arithmetic circuit 3 and Input to OR gate 13. The coincidence signal input to the OR gate 13 is input to the set end of the timer control signal generation circuit 17. When the coincidence signal is input to the set terminal, the timer control signal generation circuit outputs a control signal at an active voltage level to the time control element connected to the terminal 18. The timed control element is therefore activated at time _ts , as shown in FIG. At the same time, the arithmetic circuit 3 reads from the arithmetic register 10 which has already stored _the time interval T ₁ of the two types of time intervals T 1 and T ₂ set by the time interval setting circuit 5.
Subtraction is started sequentially for each time of the reference pulse.
Hereinafter, similarly to the operation of the circuit shown in FIG. 1, the timer control signal generating circuit 17 has a time control element in an active state for a period of T ₁ and then a period of T ₂ as shown in FIG. 5.
It repeatedly outputs a control signal that causes it to be inactive for a period of . Next, when the time measured by the clock circuit 21 matches the end time _te of the sequence control stored in the storage register 25, the match signal generation circuit 27 detects that both times match and generates a second match signal. The signal is generated and output to the arithmetic circuit 3 and the OR gate 14. When the second coincidence signal is input, the arithmetic circuit 3 stops the subtraction. Further, the OR gate 14 outputs a second coincidence signal to the reset terminal of the timer control signal generation circuit 17. When the second coincidence signal is input to the reset terminal, the timer control signal generating circuit 17 outputs a control signal at the inactive voltage level regardless of the previous output state. Then, by inputting a control signal at an inactive voltage level through the terminal 18, the timed control element becomes inactive at t _e as shown in FIG. Thereafter, when the time measured by the clock circuit 21 coincides with the time _ts stored in the storage register 24, the above operation is repeated again. By using the above-described configuration, each of the storage registers 6, 7, 24, 25 and the calculation registers 10, 11 can be realized by a multi-bit shift register, and the clock circuit 21 can be realized by a counter consisting of a shift register and a half adder. If a so-called dynamic system is adopted as the main circuit, an extremely simple configuration can be achieved. In addition, a time setting memory circuit 26 , a clock circuit 21, and a coincidence signal generation circuit are provided to set the start and end times of sequence control, and the circuit operation is automatically turned on and off at both times, so that the time control element Sequential control can be programmed in real time.

In the embodiment shown in FIG. 4, the arithmetic circuit 3 sequentially subtracts the reference pulse time from two types of time intervals T ₁ and T ₂ stored in the arithmetic registers 10 and 11. As shown in FIG. 3, the time of the reference pulse may be sequentially added to the calculation registers 10 and 11.

The present invention is not limited to the embodiments described above. For example, in the embodiment described above, the output of the timer control signal generation circuit 17 is supplied to a serial time control element to perform on/off control. Alternatively, the output of the signal generating circuit 17 may be used to drive a relay or the like, and the time control element may be turned on and off using the contacts of this relay. Furthermore, in the above embodiment, the case where the frequency divider circuit 1 and the clock circuit 21 are provided separately has been explained, but in this case, both of them are provided as one unit.
It is also possible to configure two circuits to perform the respective functions. It goes without saying that various other modifications can be made to the present invention without departing from the scope thereof.

As explained above, according to the present invention, an arbitrarily selected time interval within an extremely wide time range can be freely reset as necessary, and two types of time intervals can be set. It is possible to arbitrarily change the two time intervals of the active time and inactive time of the timed control element that should be operated sequentially, and its duty, and it is suitable for semiconductor integrated circuits where sequential control can be programmed in real time. A digital sequential timer device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital sequential timer device of the present invention, FIG. 2 is a time chart for explaining the above embodiment, and FIG.
FIG. 4 is a block diagram showing another embodiment of the invention, FIG. 4 is a block diagram showing still another embodiment of the invention, and FIG. 5 is a time chart for explaining the above embodiment. DESCRIPTION OF SYMBOLS 1... Frequency division circuit, 2, 18... Terminal, 3... Arithmetic circuit, 4 ... Time interval setting memory circuit, 5... Time interval setting circuit, 6, 7, 24, 25... Memory register, 8 , 9... gate circuit, 10, 11...
Arithmetic register, 12... Time-up signal generation circuit, 13, 14... OR gate, 15... Start signal generation circuit, 16... Reset signal generation circuit, 17... Timer control signal generation circuit, 19, 2
0... Clear circuit, 21... Timing circuit, 22...
Time display section, 23... Time setting circuit, 26 ... Time setting storage circuit, 27... Coincidence signal generation circuit.

Claims (1)

[Claims] 1. A frequency dividing circuit that divides the frequency of a supplied clock pulse and outputs a reference pulse that serves as a time reference; 2.
a time interval setting memory circuit that sets and stores a type of time interval; and a time interval setting memory circuit for setting and storing a type of time interval; an arithmetic circuit that sequentially subtracts time or sequentially adds time for each reference pulse from 0, performs the above subtraction or addition alternately for two types of time intervals, and stops the subtraction and addition when a reset signal is supplied; When the arithmetic output of the arithmetic circuit is supplied and the arithmetic circuit is performing subtraction, it detects that the remaining time interval becomes 0 and outputs a time-up signal, and when it is performing addition, it outputs the time-up signal. a time-up signal generation circuit that outputs a time-up signal upon detecting that the time interval stored in the memory circuit matches the calculated output; and a time-up signal generation circuit that outputs a time-up signal when it detects that the time interval stored in the storage circuit matches the calculation output; When the time-up signal is supplied, an externally connected time control element outputs a control signal that maintains either the active state or the inactive state, and outputs the odd-numbered signal from the time-up signal generation circuit. a timer control signal generation circuit that outputs a control signal that causes a time control element to maintain its other state by being supplied with a time-up signal or by being supplied with a reset signal. timer device. 2. A frequency divider circuit that divides the frequency of the supplied clock pulse and outputs a reference pulse that serves as a time reference, and a clock circuit that counts the reference pulses output from the frequency divider circuit to measure the current time; a time setting memory circuit for setting and storing the time of , a coincidence signal generating circuit for detecting that the time set by the time setting memory circuit matches the current time and outputting a coincidence signal; One of the two types stored in the time interval setting memory circuit by being supplied with a coincidence signal from the time interval setting memory circuit that sets and stores the time interval setting memory circuit and the coincidence signal generating circuit.
The time for each reference pulse is sequentially subtracted from the other time interval, or the time for each reference pulse is sequentially added from 0, and the above subtraction or addition is performed alternately for the two types of time intervals, and the coincidence signal generation circuit again generates a coincidence signal. An arithmetic circuit that stops the above-mentioned subtraction and addition by being supplied with a signal, and a time-up circuit that detects that the remaining time interval becomes 0 when the arithmetic output of the above-mentioned arithmetic circuit is supplied and is performing subtraction. a time-up signal generation circuit that outputs a time-up signal upon detecting that the time interval stored in the time interval setting storage circuit matches the calculation output when the signal is output and addition is performed; When a coincidence signal is supplied from the signal generation circuit or an even-numbered time-up signal output from the time-up signal generation circuit is supplied, the externally connected time control element is in either an active state or an inactive state. The time-up control is performed by outputting a control signal that maintains one of the states, and by supplying an odd-numbered time-up signal from the time-up signal generation circuit or by supplying a coincidence signal from the coincidence signal generation circuit. 1. A digital sequential timer device comprising: a timer control signal generation circuit that outputs a control signal that causes one element to maintain the other state.