JPS6132799U - Pulse train input digital controller - Google Patents

Pulse train input digital controller

Info

Publication number
JPS6132799U
JPS6132799U JP11546584U JP11546584U JPS6132799U JP S6132799 U JPS6132799 U JP S6132799U JP 11546584 U JP11546584 U JP 11546584U JP 11546584 U JP11546584 U JP 11546584U JP S6132799 U JPS6132799 U JP S6132799U
Authority
JP
Japan
Prior art keywords
digital controller
input
pulse train
input digital
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11546584U
Other languages
Japanese (ja)
Inventor
悟 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP11546584U priority Critical patent/JPS6132799U/en
Publication of JPS6132799U publication Critical patent/JPS6132799U/en
Pending legal-status Critical Current

Links

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  • Control Of Stepping Motors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は通常に使用されるパルス列入カデジタ.ルコン
トローラーのブロック図、第2図はステツピングモータ
ーを使用した場合のモーター部のブロック図、第3図は
入力信号と時間、モーターの位置と時間との関係を示す
図。 第4図はF−V変換器、積分回路を備えたパルス列入力
デジタルコントローラーのブロック図。 第5図は第4図の回路を用いたときの入力信号と時間、
モーターの位置と時間との関係を示す図。 第6図は偏差カウンターの出力機能を示す図。
Figure 1 shows a commonly used pulse train input digital. Figure 2 is a block diagram of the motor section when a stepping motor is used, and Figure 3 is a diagram showing the relationship between input signals and time, and the position of the motor and time. FIG. 4 is a block diagram of a pulse train input digital controller equipped with an F-V converter and an integrating circuit. Figure 5 shows the input signal and time when using the circuit in Figure 4,
A diagram showing the relationship between motor position and time. FIG. 6 is a diagram showing the output function of the deviation counter.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)入力パルス信号をF−Vコンバーターにより電圧
に変換し、それを積分回路を通じ電圧として出力し、電
圧レベルで速度制御するモーターの入力信号としたパル
ス列入力デジタルコントローラー。
(1) A pulse train input digital controller that converts an input pulse signal into a voltage using an F-V converter, outputs it as a voltage through an integrating circuit, and uses it as an input signal for a motor whose speed is controlled by the voltage level.
(2)前記デジタルコントローラーの入力信号を並列に
偏差カウンターの入力となし、モーター軸からの回転エ
ンコーダーの出力信号を他方の入力となし、偏差カウン
ターの偏差が0でないときにはF−Vコンバーターの出
力にバイアス電圧を加えることを特徴とするパルス列入
力デジタルコントローラー。
(2) The input signal of the digital controller is used as the input of the deviation counter in parallel, and the output signal of the rotation encoder from the motor shaft is used as the other input, and when the deviation of the deviation counter is not 0, it is used as the output of the F-V converter. A pulse train input digital controller characterized by applying a bias voltage.
(3)前記偏差カウンターに上限値をプリセットし、こ
の値に到達した時、信号を出力するパルス列入力デジタ
ルコントローラー。
(3) A pulse train input digital controller that presets an upper limit value in the deviation counter and outputs a signal when this value is reached.
JP11546584U 1984-07-28 1984-07-28 Pulse train input digital controller Pending JPS6132799U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11546584U JPS6132799U (en) 1984-07-28 1984-07-28 Pulse train input digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11546584U JPS6132799U (en) 1984-07-28 1984-07-28 Pulse train input digital controller

Publications (1)

Publication Number Publication Date
JPS6132799U true JPS6132799U (en) 1986-02-27

Family

ID=30674435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11546584U Pending JPS6132799U (en) 1984-07-28 1984-07-28 Pulse train input digital controller

Country Status (1)

Country Link
JP (1) JPS6132799U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015062342A (en) * 2015-01-07 2015-04-02 株式会社リコー Conveying device, image forming apparatus, and conveying method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015062342A (en) * 2015-01-07 2015-04-02 株式会社リコー Conveying device, image forming apparatus, and conveying method

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