JPS6130156A - Audible sound discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate easily audible sounds by squaring an input signal and a signal obtained by delaying the input signal by the number of samples corresponding to a 1/4 period and adding these squared values and comparing this addition value with a threshold level. CONSTITUTION:A selector 2 selects an input signal Si, and a value kSi<2> (k is a coefficient) corresponding to the square of the amplitude value is stored in a ROM4 and is stored in a read buffer 5. Next, the selector 2 selects a delay signal Sd which is outputted from a shift register 1 and is delayed by the number of samples corresponding to the 1/4 period of an audible sound signal as the discrimination object, and this signal is inputted as an address to the ROM4. The value kSi<2> from the buffer 5 and a value kSd<2> from the ROM4 are added by an adder 6, and the addition result is sent to a comparator 7. The comparator 7 compares the addition result with a predeterminate threshold signal St and sets an output signal So to ''1'' if the addition result is larger than the threshold and sets the signal So to ''0'' otherwise. Thus, it is discriminated whether the frequency of the input signal is, for example, 400Hz or not or whether the amplitude is varied or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an audible tone identification circuit for confirming the normality of a single frequency audible tone used in a digital exchange.

The audible tones used in telephone exchanges, for example, the dial tone is 40
A single frequency signal of 0 hertz is used. In a digital switch, such audio signals are digitally encoded and stored in a read-only memory. It is necessary to check whether the frequency and amplitude of such an audible sound signal are normal.

[Conventional technology]

FIG. 3 is a diagram showing an example of a read-only memory for storing audible tones in a digital exchange.

In FIG. 3, data dl to dn, which are digital codes of audible sound signals such as dial tone DT or ring tone RBT,
Alternatively, di' to dn' are stored in read-only memory. A parity bit p is added to each data d1..., and the normality of each data d1... is confirmed by performing a parity check when each data d1... is output one after another. .

[Problem to be Solved by the Invention 3] As is clear from the above explanation, in the conventional audible sound identification method, the normality of the audible sound is determined by performing a parity check when each data of the audible sound signal is read. I was analogizing gender. Therefore, failures in peripheral circuits that cannot be detected by parity checks are not detected early, and necessary repairs are made only after the subscriber reports, which may result in a reduction in service to subscribers.

In order to eliminate such drawbacks, it has been considered to construct a receiving circuit for testing purposes, but such a receiving circuit has the drawbacks of being complex and expensive.

[Means for solving problems]

The present invention inputs a digitally encoded input signal,
a first means for delaying the number of samples corresponding to 1/4 period of an audible sound signal to be identified; and a signal outputted from the first means at the same time as the input signal and the input signal, respectively. A second means for squaring and then adding, and a third means for comparing the output of the second means with a predetermined threshold value and outputting a comparison result, and adjusting the input signal based on the comparison result. The above problem is solved by distinguishing it from the audible sound signal.

[Effect]

For example, two values A separated by 1/4 period of a single frequency signal
cosθ and Acos (θ−π/2) = As
If in θ are respectively squared and then added, a constant value A2 of the signal is obtained. However, if two values deviated by δ from the 1/4 period are squared and then added, the addition result is A' co
s:Iθ+A25in"(θ+δ)=A"(1'+s
in δ·sin (θ+δ)], which may result in A2 or less. Furthermore, if the amplitude A fluctuates, A
itself changes. Therefore, if the result of squaring and adding two values having a gap corresponding to 1/4 period of the single frequency of the signal whose frequency is unknown becomes a constant value, the amplitude of the signal is constant and the identification It turns out that it has the target frequency.

The present invention utilizes this principle to identify the amplitude and frequency of an audible sound signal using a simple arithmetic circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an audible sound identification circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the addition output in FIG. 1. FIG. 1 has a single frequency of 400 hertz and is sampled by a sampling frequency of 8 kilohertz;
Suppose we want to identify an audible signal, such as a dial tone, which is digitally encoded into a bit code.

In FIG. 1, the input signal 5L (=Acos θ) is
It is directly transmitted to the selector 2 via the shift register 1 as well as the shift register 1. The shift register 1 provides a delay of 40 bits (5ooo÷400÷4X8=40 bits), which is the number of bits corresponding to 1/4 period of the 400 Hz signal to be identified. Therefore, selector 2 receives input signals S1 and 40.
Input signal St before the bit (hereinafter referred to as delayed signal Sd)
are input at the same time. The selector 2 first selects the input signal S1 and inputs it to the read-only memory 4 as an address. The read-only memory 4 stores at each address a value proportional to the square of the amplitude value represented by each address value. Therefore, data kXsi2 (k is a coefficient) corresponding to the square of the input signal Si is read out and stored in the buffer 5. Next, selector 2 is shift register 1
The delay signal Sd outputted from the CPU 11 is selected and inputted to the read-only memory 4 as an address. As a result, the continuous read only memory 4 stores data kXS corresponding to the square of the delayed signal Sd.
d is read out and input to the adder 6 together with the data kXS t stored in the buffer 5. Adder 6
adds the input data kXS12 and kxSd, and sends the addition result kXsi2+kxSd to the comparator 7.
Enter. The comparator 7 compares the addition result kXS l= +kxSd input from the adder 6 with a predetermined threshold signal St,
If the addition output is always greater than or equal to the threshold signal St, the output signal S
O is set to a logical value of 1, and if there is a case where the value is equal to or lower than the threshold signal St, the output signal SO is set to a logical value of 0. If the threshold signal St is now set to -A (1-5 inS), the output signal SO will always be set to a logic value of 1 when the frequency f of the input signal Si has an error within the allowable range of 400 Hz. ing.

Therefore, by monitoring the output signal SO, the input signal S
It becomes possible to identify whether the frequency of i is 400 hertz or not. Note that even when the amplitude A of the input signal Si fluctuates, the output signal SO becomes the logical value O, and instability of the amplitude A is detected.

As is clear from the above description, according to this embodiment, the first
With a simple configuration as shown in the figure, it is possible to identify whether the frequency of the input signal is 400 hertz or not, and whether or not the amplitude A is a response.

Note that FIGS. 1 and 2 are only one embodiment of the present invention, and for example, the audible signal to be identified is not limited to 400 Hz, and many other variations may be considered. However, in either case, the effects of the present invention remain the same. Note that even if the 1/4 period of the audible sound signal to be identified is not an integral multiple of the sampling period, the nearest integer number of samples is adopted,
Moreover, by setting the threshold signal in consideration of the error in the number of samples, the effects of the present invention remain unchanged. It goes without saying that the configuration of the audible sound identification circuit is not limited to that shown in the drawings.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize an audible sound identification circuit that identifies the frequency of a single frequency audible sound signal with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an audible sound identification circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the addition output in FIG. 1,
FIG. 3 is a diagram showing an example of a read-only memory for storing audible tones in a digital exchange. In the figure, 1 is a shift register, 2 is a selector, 3 is a serial/parallel conversion circuit, 4 is a read-only memory, 5 is a buffer, 6 is an adder, 7 is a comparator, A is power, and dl to d
n and di' to dn' are data, DT is dial tone, p
is the parity bit, RBT is the ring tone, Si is the input signal,
SO indicates an output signal, and St indicates a threshold signal.

Claims (1)

[Claims] a first means for inputting a digitally encoded input signal and delaying the input signal by a number of samples corresponding to 1/4 cycle of an audible sound signal to be identified; a second means for squaring and then adding the signals output from the first means; and a third means for comparing the output of the second means with a predetermined threshold and outputting a comparison result. and identifying the input signal from the audible sound signal based on the comparison result.