JPH05145526A - Data communication equipment - Google Patents

Data communication equipment

Info

Publication number
JPH05145526A
JPH05145526A JP33142391A JP33142391A JPH05145526A JP H05145526 A JPH05145526 A JP H05145526A JP 33142391 A JP33142391 A JP 33142391A JP 33142391 A JP33142391 A JP 33142391A JP H05145526 A JPH05145526 A JP H05145526A
Authority
JP
Japan
Prior art keywords
data
circuit
output
twice
allowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33142391A
Other languages
Japanese (ja)
Inventor
Yoichi Shibaki
洋一 柴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Seiki Co Ltd
Original Assignee
Nippon Seiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Seiki Co Ltd filed Critical Nippon Seiki Co Ltd
Priority to JP33142391A priority Critical patent/JPH05145526A/en
Publication of JPH05145526A publication Critical patent/JPH05145526A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To prevent an output of error data by allowing an output circuit to output same output data twice separately, allowing a receiver side to compare both data and discriminating the data to be data subjected to noise effect during transmission when they are not identical and invalidating the discriminated data. CONSTITUTION:An output circuit 2 sends same data of measurement circuits 11-13 to a receiver side I/F circuit 4 via a transmission line 3 as 1st and 2nd data separately twice. A holding circuit 51 of a discrimination circuit 5 latches the 1st data and when the 2nd data are outputted, a comparator circuit 52 compares the 1st data and the 2nd data stored in the circuit 51 to discriminate whether or not they are identical. When the result of discrimination indicates to be identical the circuit 5 allows the latch circuit 53 to output the 2nd data to a processing circuit 6. If not, the circuit 5 invalidates the 1st and 2nd data while regarding it that the effect of noise takes place and inhibits the output to the circuit 6. Thus, the output of erroneous data is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、伝送路によって送信さ
れるデータの正誤を判定し、データに誤りが生じた場合
には後段の回路にこのデータを出力しないようにしたデ
ータ通信装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication apparatus which determines whether data transmitted by a transmission line is correct or not and does not output this data to a circuit in the subsequent stage when an error occurs in the data.

【0002】[0002]

【従来の技術及び本発明が解決しようとする課題】通常
のデータ通信は、各被測定対象の状態を電気信号に変換
し、これをシリアル、もしくはパラレル伝送路を介して
受信回路へ出力し、この受信回路で所定処理を行ったの
ち前記各被測定対象に対応する処理回路に送信される方
式が一般的である。ところで前記所定処理とは、データ
が正確に受信回路に出力されているかどうかをチェック
するもので、例えば送信中に生じるノイズでデータに誤
りが生じても、パリティチェック等の手段を用い、この
データが後段の回路に出力されない様になっている。
2. Description of the Related Art In ordinary data communication, the state of each object to be measured is converted into an electric signal, which is output to a receiving circuit via a serial or parallel transmission line, In general, this receiving circuit performs a predetermined process and then transmits it to a processing circuit corresponding to each of the measured objects. By the way, the predetermined processing is to check whether or not the data is accurately output to the receiving circuit. For example, even if an error occurs in the data due to noise that occurs during transmission, this data is checked using a means such as a parity check. Is not output to the circuit in the subsequent stage.

【0003】ところが前記パリティチェックでは、1回
の送信で2ビットのデータに誤りが生じた場合、このデ
ータは正確なデータとして扱われる場合があり、誤デー
タのの原因となる。
However, in the parity check, when an error occurs in 2-bit data in one transmission, this data may be treated as accurate data, which causes erroneous data.

【0004】[0004]

【課題を解決するための手段】本発明は、上記課題を解
決するために、被測定量に対応して出力回路の出力デー
タを2回に分けて出力し、このデータを受信する、内部
に比較回路を有する判定回路では、前記両出力データを
比較し、同一の場合はこのデータを有効としてそのまま
後段の回路に出力し、同一でない場合には送信中にノイ
ズ等の影響があったとし、このデータを無効とするとし
たものである。
In order to solve the above-mentioned problems, the present invention outputs the output data of the output circuit in two steps corresponding to the quantity to be measured, and receives this data internally. In the determination circuit having the comparison circuit, the both output data are compared, and if the two are the same, this data is validated and output as it is to the circuit in the subsequent stage. This data is invalidated.

【0005】[0005]

【実施例】図1に本発明の好的な実施例を図示し説明す
る。測定回路11, 12, 13は被測定対象ごとに設けられ、
それぞれの状態の変化に応じた電気信号を出力回路2に
出力する。出力回路2は前記測定回路11,12,13のデー
タをシリアル通信用のデータに変換するインターフェー
ス回路である。シリアルに変換されたデータは伝送路3
を介して受信側のインターフェース回路4へ出力され、
このインターフェース回路4によりパラレルデータに変
換される。このパラレルデータは判定回路5によりデー
タの正誤チェックを受けた後、データに誤りのないこと
が判定されると後段の処理回路6に出力されそれぞれの
処理が行われることになっている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention is shown in FIG. 1 and explained. Measuring circuits 11, 12 and 13 are provided for each measured object,
The electric signal according to the change of each state is output to the output circuit 2. The output circuit 2 is an interface circuit for converting the data of the measuring circuits 11, 12, 13 into data for serial communication. The data converted to serial is the transmission line 3
Is output to the interface circuit 4 on the receiving side via
The interface circuit 4 converts the data into parallel data. After the parallel data is checked for correctness by the judgment circuit 5, if it is judged that there is no error in the data, the parallel data is output to the processing circuit 6 in the subsequent stage and each processing is performed.

【0006】次に本発明の主要部である出力回路2と前
記判定回路5の作用についてさらに説明する。出力回路
2では同じデータを2度、すなわち第1,第2のデータ
に分けてインターフェース回路4へ出力する。第1のデ
ータはまず保持回路51に記憶保持される。次に第2のデ
ータが出力されると、比較回路52ではこの第2のデータ
と保持回路51に記憶した第1のデータとの比較を行い、
同一であればラッチ回路53へ信号を出力し、インターフ
ェース回路4から出力された第2のデータを処理回路6
へ出力する。しかし、比較回路52での比較結果が同一で
ないと判定された場合には、第1または第2のデータの
送信中にノイズの影響があったとみなし、このデータを
無効とし、処理回路6へデータを出力することを禁止す
る。
Next, the operation of the output circuit 2 and the judgment circuit 5 which are the main parts of the present invention will be further described. The output circuit 2 outputs the same data to the interface circuit 4 twice, that is, dividing into the first and second data. The first data is first stored and held in the holding circuit 51. Next, when the second data is output, the comparison circuit 52 compares the second data with the first data stored in the holding circuit 51,
If they are the same, a signal is output to the latch circuit 53, and the second data output from the interface circuit 4 is processed.
Output to. However, when it is determined that the comparison result in the comparison circuit 52 is not the same, it is considered that there was an influence of noise during the transmission of the first or second data, this data is invalidated, and the data is sent to the processing circuit 6. Is prohibited from being output.

【0007】すなわち、1つのデータを2度に分けて出
力し、比較することで正確にデータの送信が行われたか
どうかを判定することが簡単にできるものである。
That is, it is possible to easily determine whether or not the data has been transmitted accurately by outputting one data dividedly twice and comparing them.

【0008】尚、上記実施例では、判定回路5の具体的
回路については述べなかったが、複数(データのビット
数と同数)のEX−ORゲートの一方の入力に第1のデ
ータを、もう一方の入力に第2のデータを入力し、それ
ぞれのEX−ORゲートの出力をORゲートに接続して
比較回路を構成させ、ORゲートの出力をラッチ回路53
に出力させるなどして構成してもよく、要は第1と第2
のデータが同一でなければ処理回路6へデータを出力し
ないようにする回路構成であればよい。
Although the specific circuit of the decision circuit 5 is not described in the above embodiment, the first data is already input to one input of a plurality (the same number as the number of bits of data) of the EX-OR gates. The second data is input to one input, the output of each EX-OR gate is connected to the OR gate to form a comparison circuit, and the output of the OR gate is set to the latch circuit 53.
It may be configured to be output to, and the point is that the first and second
If the data is not the same, the circuit configuration may be such that the data is not output to the processing circuit 6.

【0009】またこの実施例では、送信されるデータの
1ヶ所でも誤りがあれば、データ全体を無効としていた
が、被測定対象ごとに判定回路5を設け、誤りのあった
ビットを含むデータのみを無効とする回路構成も考えら
れる。
Further, in this embodiment, if there is an error in even one portion of the data to be transmitted, the entire data is invalidated. However, the determination circuit 5 is provided for each object to be measured, and only the data including the erroneous bit is provided. A circuit configuration for invalidating is also possible.

【0010】[0010]

【発明の効果】以上の様に本発明は、被測定量に応じて
生成される出力データを2度伝送路を介して出力し、こ
の2度出力される両データの比較を行うことで送信中に
ノイズの影響があったかを判定でき、誤ったデータを後
段の回路へ出力させることのない効果がある。
As described above, according to the present invention, the output data generated according to the quantity to be measured is output twice via the transmission path, and the data output twice is transmitted by comparison. It is possible to determine whether or not there is an influence of noise, and there is an effect that erroneous data is not output to the circuit in the subsequent stage.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の好的な実施例を示したブロック図であ
る。
FIG. 1 is a block diagram showing a preferred embodiment of the present invention.

【符号の説明】[Explanation of symbols]

2 出力回路 3 伝送路 5 判定回路 52 比較回路 2 Output circuit 3 Transmission line 5 Judgment circuit 52 Comparison circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被測定量に応じて生成される出力データ
を2度伝送路に送信する出力回路と、この連続して出力
される出力データの比較を行う比較回路を有し、両出力
データが同一でない場合、この出力データの全体もしく
は一部を無効とする判定回路とを備えたデータ通信装
置。
1. An output circuit for transmitting output data generated according to a measured quantity to a transmission path twice, and a comparison circuit for comparing output data which are continuously output. And a determination circuit that invalidates all or part of the output data when the two are not the same.
JP33142391A 1991-11-20 1991-11-20 Data communication equipment Pending JPH05145526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33142391A JPH05145526A (en) 1991-11-20 1991-11-20 Data communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33142391A JPH05145526A (en) 1991-11-20 1991-11-20 Data communication equipment

Publications (1)

Publication Number Publication Date
JPH05145526A true JPH05145526A (en) 1993-06-11

Family

ID=18243505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33142391A Pending JPH05145526A (en) 1991-11-20 1991-11-20 Data communication equipment

Country Status (1)

Country Link
JP (1) JPH05145526A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007089243A (en) * 2005-09-20 2007-04-05 Yaskawa Electric Corp Motor control system
JP2017511625A (en) * 2014-01-30 2017-04-20 テレフオンアクチーボラゲット エルエム エリクソン(パブル) Redundant scheduling information for direct communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6351738A (en) * 1986-08-21 1988-03-04 Mitsubishi Electric Corp Optical space propagating communication equipment
JPS63138826A (en) * 1986-11-29 1988-06-10 Nec Corp Data transmission system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6351738A (en) * 1986-08-21 1988-03-04 Mitsubishi Electric Corp Optical space propagating communication equipment
JPS63138826A (en) * 1986-11-29 1988-06-10 Nec Corp Data transmission system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007089243A (en) * 2005-09-20 2007-04-05 Yaskawa Electric Corp Motor control system
JP4753069B2 (en) * 2005-09-20 2011-08-17 株式会社安川電機 Motor control system
JP2017511625A (en) * 2014-01-30 2017-04-20 テレフオンアクチーボラゲット エルエム エリクソン(パブル) Redundant scheduling information for direct communication
US10219216B2 (en) 2014-01-30 2019-02-26 Telefonaktiebolaget Lm Ericsson (Publ) Redundant scheduling information for direct communication

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