JPS6129497A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent malfunction without adversely affecting an action speed by varying a resistance value of a load transistor at the dummy cell memory side in accordance with the potential of a signal input line at the memory cell side of a differential data detecting means. CONSTITUTION:A gate of a load transistor 32 in a comparison potential generator circuit 24 is connected to one signal input line 23 of a differential sensor amplifier 22, and a resistance across a source and drain of an FET32 varies in accordance with the potential of the line 23. When the FET32 is made a P- channel and the potential of the line 23 changes at a high level, the resistance value of the FET32 rises, while the potential of a signal input line 26 drops. On the other hand, when the potential of the line 23 changes at a low level, the potential of the line 26 rises. As a result, a difference between both input potentials of the amplifier 22 is increased, and malfunction due to the fluctuation of a power source can be prevented. Moreover it is unnecessary to increase the amplitude of a potential V1 of the line 23, an acting speed will not speed down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data read-only semiconductor memory device equipped with a differential sense amplifier.

[Technical Background of the Invention] In general, differential sense amplifiers are often used in semiconductor storage devices (hereinafter referred to as memories) because their operation is stable and they can detect extremely small potential differences.

By the way, R that can read and write data
In an AM (random access type memory) or the like, a pair of data having mutually opposite levels is output as memory data. For this reason, this pair of data is led to a pair of signal input lines of a differential sense amplifier for data detection. However, in the case of ROM (data read-only memory), '1' is sent from the memory cell.
'' or OI+, so a comparison potential is prepared using a dummy memory cell transistor equivalent to the memory cell as a sense amplifier used in the ROM, and this potential is used together with the column line potential. The data is detected by supplying it to a sense amplifier.

The M2 diagram is, for example, an insulated gate field effect transistor (
1 is a circuit diagram showing the configuration of a conventional mask ROM using MOS transistors (hereinafter referred to as MOS transistors). In the figure, 10
is a memory cell array, and 11 is this memory cell array 10.
12 is a MOS transistor for column selection; 1 is a MOS transistor for column selection;
3 is a row decoder, 14 is a column decoder, 15 is a row line, 16 is a column line, and 17 to 19 are M for load.
OS l-transistors 20 and 21 are resistors for generating bias voltage.

The potential of the column line 16 is set according to the data read from the memory cells 11 in the memory cell array 1o, and this column line potential is level-shifted to the potential Vl by the transistor 19, and one of the differential sense amplifiers 22 It is supplied to the signal power line 23.

Reference numeral 24 denotes a comparison potential generation circuit, which includes a dummy memory cell 2 made of a MOS transistor similar to the memory cell 11.
5 is used to generate a comparison potential V2' to be supplied to the other one signal input line 26 of the sense amplifier 22, 27.28 is a bias generating resistor similar to the resistor 20.21, and 29 30 to 32 are MOS transistors whose gates are supplied with a °°1 level signal and which are always on, equivalent to the column selection MOS I-transistor 12; 30 to 32 are the load MOS transistors 1;
MOS transistor equivalent to 7 to 19, 33.34
is a bias resistor that supplies the gate of the dummy memory cell 25 with a constant bias potential at an intermediate level between the "'1" level and the "O++ level."

The sense amplifier 22 is supplied with control signals GE and CE, and the data detection operation in the sense amplifier 22 is controlled by these signals.

The data detected by the sense amplifier 22 is output as output data D via the output buffer 7 circuit 35.

Note that the load transistor 19. ' 32 are both P-channel ones, the gate of the transistor 19 is connected to the one signal input line 23, and the gate of the transistor 32 is connected to the other signal input line '! 6, respectively.

With ROMs like this, comparison! Since the gate potential of the dummy memory cell 25 in the potential generation circuit 24 is kept constant by the resistors 33 and 34, the comparison potential V2' obtained at the signal input line 26 changes over time as shown in the waveform diagram of FIG. It is at a constant, fixed potential with respect to. Therefore, when reading data from the memory cell 11, the potential v
When the potential V2' is changed to cross the potential V2' as shown by the solid line in the figure, the output of the sense amplifier 22 is inverted, and the output signal data D of the output buffer circuit 35 is changed to the potential V1' as shown by the broken line in FIG. changes according to changes in For example, if the threshold voltage of the memory cell 11 selected in the memory cell array 10 is high, the memory cell will not turn on even in the selected state, and the column line 16 will be at the power supply potential V
It will be charged in the channel direction! At this time, one input potential ■1 of the sense amplifier 22 is set to the other input potential ■2'
, and the output buffer circuit 35 outputs "'1".
``Level data D corresponding to the level storage data is output.On the other hand, if the threshold voltage of the selected memory cell 11 is low, when it is selected, the memory cell is turned on and the column line 16 is discharged toward the ground potential through this memory cell. At this time, one input potential 1 of the sense amplifier 22 becomes smaller than the other input potential V 2 L , and the output buffer 1 circuit 35 outputs an "O" level. Data D at a level corresponding to the stored data is output.

[Problems with the background art] By the way, in the above ROM, the differential sense amplifier 22
Then, the level of the output data D is inverted at the point where the potential V1 crosses the comparison potential V2'. In order to operate a memory using such a sense amplifier stably, it is desirable that the difference between the potential ■1 and the comparison potential V2', indicated by v3' in FIG. 3, be large. . When this potential V31 is small, noise enters the power supply, causing power supply fluctuations, which causes the above potential v1 to fluctuate, and when the potential v1 crosses the comparison potential V2' due to this fluctuation, the output data D is erroneously inverted. Put it away. This is a malfunction. Therefore, in order to prevent such malfunctions, it is better for the potential V3' to be large. However, if, for example, the amplitude of the potential 1 is increased in order to increase the potential Va', charging and discharging the column line 16 takes time, resulting in a disadvantage that the data read speed becomes slow.

[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor memory device that can prevent malfunctions without sacrificing operating speed. be.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention provides a differential sense amplifier whose potential is set in accordance with the data of a memory cell. By changing the resistance value of the load transistor connected to one signal input line, the potential change of the other signal input line is changed in the opposite direction to the potential change of one signal input line, thereby increasing the difference between the two potentials. ing.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device according to the present invention implemented in a ROM in the same manner as in the prior art. The difference between this embodiment circuit and the conventional circuit shown in FIG. 2 is that the gate of the load transistor 32 in the comparison potential generation circuit 24 is connected to the differential sense amplifier
Instead of being connected to the other signal input line 26 of 2, it is connected to one signal input line 23 on the memory cell side.

In such a configuration, the gate of the load transistor 32 in the comparison potential generation circuit 24 is connected to the differential sense amplifier 22.
Since the transistor 32 is connected to one signal input line 23, the resistance value between the source and the train of this transistor 32 changes depending on the potential of the signal input line 23.

Moreover, since this transistor 32 is of a P channel, when the potential of the signal input line 23 changes in the direction of increasing, the resistance value of this transistor 32 increases and the potential of the signal input line 26 decreases. On the contrary, when the potential of the signal input line 23 changes in the direction of decreasing, the resistance value of this transistor 32 decreases, and the signal input! ! The potential of 26 increases. Therefore, the potential v2 of the signal input line 26, which corresponds to the potential V2' which has conventionally always been kept at a constant value, is
As shown by the dashed line in the figure, the potential changes in the opposite direction to a change in the potential Vl, so the potential VB, which is the difference between the two potentials, can be made larger than in the conventional case. At this time, since the amplitude of the potential V of one signal input line 23 can be kept the same as in the conventional case, there will be no problem that the operating speed, especially the data read operation, will be slow.

As described above, according to this embodiment, the difference between the two input potentials of the sense amplifier 22 can be increased, so that malfunctions due to power supply fluctuations can be prevented. Furthermore, since there is no need to increase the amplitude of the potential V1, malfunctions can be prevented without sacrificing operating speed.

Note that the other signal input line 26 of the differential sense amplifier 22
Since the capacitance of the signal input line 26 is sufficiently smaller than that of the signal input line 23, the potential V2 of the signal input line 26 can be changed at a high speed.

It goes without saying that this invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in the above-mentioned embodiments, the case where this invention is implemented in a mask ROM has been described, but this In addition, in EPROMs and the like in which data can be erased, the resistance value of the load transistor on the dummy memory cell side is changed in accordance with the potential of the signal input line on the memory cell side of the differential data detection means. Therefore, malfunctions can be prevented without sacrificing operating speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing the structure of a conventional ROM, and FIG. 3 is a semiconductor memory device according to an embodiment of the present invention. and FIG. 9 is a waveform diagram for explaining the operation of a conventional ROM. 10... memory cell array, 11... memory cell,
12... MOS transistor for column selection, 13...
Row decoder, 14... Column decoder, 15... Row line,
16... Column line, 17-19° 30-32... MOS transistor for load, 20.21° 27, 28...
Resistor for bias voltage generation, 22... Differential sense amplifier, 23.26... Signal input line, 24... Comparison potential generation circuit, 25... Dummy memory cell, 33.34
...Bias resistance.

Claims (2)

[Claims] (1) A differential data detection means having a first and a second input line and detecting data by comparing the potentials of both input lines; First
, a second load transistor, a memory cell that is selectively driven according to an input address signal and sets the potential of the first input line according to pre-stored data, and the second input line. A semiconductor memory device comprising: a dummy memory cell for setting a potential of the second load transistor to a reference potential; and means for changing the resistance value of the second load transistor in accordance with the first input line potential. (2) The gate of the first load transistor is connected to the first load transistor.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to an input line of the first load transistor, and the gates of the first and second load transistors are connected in common.