JPS6129427A - Random access method - Google Patents

Abstract

PURPOSE:To attain access at a high speed and with high reliability by detecting the difference between identification signals of a target track and a subject track for each multi-jump of the subject track when the subject track is changed to retrieve the target track. CONSTITUTION:Both a target address and a start signal T are sent to a target resister 54 through a keyboard 52, and a target address is set. The difference between outputs of the register 54 and a present address register 56 is calculated by a subtractor 58. Then a difference code UD is sent to a feed motor control circuit 70. At the same time, the absolute value Y of the difference is sent to the circuit 70 and a sequence controller 60. The controller 60 compares the value Y with the prescribed value m2. When the value Y exceeds the value m2, a signal J is sent to the circuit 70. Then, a head 10 is shifted by a prescribed amount via a motor 83. The controller 60 gives an instruction to the register 56 to read addresses in response to a signal FE sent from the circuit 70. A difference signal Y between the address read by the register 56 and the register 54 is compared with the value m2 for shift of the head 10. This action is repeated for retrieval of a target track.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a random access method for a rotating recording medium for high-density recording, and particularly to a random access method suitable for shortening access time.

[Background of the invention]

In conventional video information files on magnetic disks, the track spacing is wide (approximately 500 .mu.m), and high-speed retrieval of arbitrary addresses is possible only by mechanical position detection.

Furthermore, regarding high-speed retrieval of arbitrary addresses using an optical video disk device that reproduces video information using a light beam, the "Address Recording and Reproducing System" [Patent Application No. 1982-69794 (Special Patent Application No. Kaisho 52-
153403)] has been adopted.

In this invention, a large number of tracks are recorded on a rotating recording medium, one of the tracks is selected, and the video information written on that track is reproduced.

The address signal used for track selection is recorded in advance on each track, and the access method is used to reach a predetermined address while detecting whether or not this address signal is a predetermined address. There is a problem in that it takes time to search and collate information. That is, to detect the address signal, a maximum disk rotation time (-seconds) is required, and in order to perform a jump while checking the address for each track, it is necessary to correct the difference between, for example, 30 tracks. will take 1 second. Note that when the amount of movement is large, the head feeder will rapidly forward the movement, but the feed error of the head feeder is as follows:
It is approximately 0 micron, and it is necessary to correct the track difference due to jumps.

[Purpose of the invention]

The present invention is an apparatus for arbitrarily high-speed searching of pre-addressed tracks on a recording medium, which reduces the time required for access, particularly the time required for jumps, to achieve faster and more reliable random access. The purpose is to provide an access method.

[Summary of the invention]

In order to achieve such an object, in the present invention, a light spot is irradiated from a head whose position is controlled by a first moving means onto a recording medium having a track on which an identification signal is recorded, and an object on which this light spot is located is emitted. The difference between the track identification signal and the identification signal corresponding to the desired track is detected, and the value of the difference is compared with a predetermined value, and until the value of the difference becomes smaller than the predetermined value, the A multi-jump is repeated in which the target track is changed one by one by moving the irradiation position of the light spot using the moving means 2, and the identification signal of the target track is detected for each multi-jump, and the difference with the identification signal corresponding to the desired track is detected. It is characterized by detecting and shortening access time without compromising reliability.

[Embodiments of the invention]

FIG. 1 shows the recording state of the video disc 94. As shown in FIG. The disk 94 rotates around a central axis 99 at 1800 revolutions per minute in the direction of an arrow 98, and each rotation converts continuous recording grooves (tracks) into one screen (one frame), that is, two fields according to the NTSC system. The corresponding frequency modulated signal is read out. The recording groove has a spiral shape toward the center of the circle, and the address of each frame is recorded in the recording groove for each frame. The interval between recording grooves is 2 μm. video disc 94
If the recording groove 74 from point 71 to point 72 recorded in 1 is an address, then the recording groove 74' from point 72 to 73 on the inside thereof is an address +1, and each has error check and error correction described later. For this purpose, odd field addresses and even field addresses indicating the same address are recorded in two areas 97.97' surrounded by two diameters 95.96 on the surface. FIG. 2 shows the demodulated waveform V of the recording groove 74.

The odd field period is 78, the even field period is 7.
8', 75 indicates an odd field vertical synchronizing pulse period 76 indicates an odd field address signal period, 77 indicates an odd field video signal period, 75', 76'
, 77' are various signal periods in the even field, and the periods 75 and 76 in the odd field, respectively.
．． 77 is supported. FIG. 3A is an enlarged view of signal V during odd field address signal period 76 in FIG.

The address signal is an (n+1) bit signal consisting of n address bits and 1 parity bit. Located between adjacent horizontal sync pulses 79. The horizontal scanning period includes signals of 2 bits among these (n+1) bits. In the figure, 20, 21. ...2n
-1 represents the first to nth address bits, respectively, and P represents the parity bit. Similarly, the even field address signal period 76' also includes an address signal, and the address signal is intended to represent the same address as the address signal contained in the odd field address signal period 76. be. FIG. 4 is a schematic block diagram of a video file device implementing the present invention. FIG. 5 is a detailed logic circuit diagram of the sequence controller 60. Figure 6 shows the error check circuit 40.
FIG. FIG. 7 is a schematic circuit diagram of the error correction circuit. FIG. 8 is a flowchart showing the flow of the file device operation of FIG. 4. The configuration and operation of the apparatus shown in FIG. 4 will be described below in accordance with the flow shown in FIG. 8 and with reference to FIGS. 5 to 7.

After the device is powered on, the keyboard 52 sends the target address to the target address register 54 via line 52B, and the keyboard 52 sends an activation signal T via line 52A to set the target address in the target address register 54. (Figure 8, block 101). At this time, the activation signal T is simultaneously sent to the sequence controller 60,
Notify it of the start of the search operation. The R-S flip-flop 608 (FIG. 5) in the sequence controller 60 is set by this signal T. Its high level output turns off video switch 14 via line 60K. This prohibits monitor display (Figure 8, block 10).
2).

The output of the target address register 54 and the output of the current address register 56 are input to a subtracter 58 where the difference between the two outputs is calculated. As a result of this subtraction, the absolute value of the difference Y is the line 58A
Above, the sign of the difference UD is output from the terminal BO on line 58B. Before starting the random access, the current address register 56 stores the address of the track currently readable by the read head 10 or an address predicted to be the address of the track.

The sequence controller 60, as shown in FIG.
A comparator 610 compares the difference signal Y with a value m2 stored in a register 612. mz is selected to be 32, for example. Depending on whether this difference signal Y is greater than or equal to m2 or less than mz, a high level or low level signal is output from comparator 610 and sent to AND gate 616. The activation signal T delayed by the delay circuit 614 is input to the AND gate 616 . The delay circuit 614 delays the activation signal T so as to output the activation signal T to the AND gate 616 after the comparator 610 outputs the determined comparison result between the difference signals Y and mz. The output of this AND gate 616 is input to the set terminal of flip-flop 618. Therefore, the flip-flop 618 is set when Y≧m2,
It is not set when Y<mz. The check as to whether Y is greater than or equal to m2 is performed in order to determine whether or not the read head 1o should be moved at high speed by the motor 83. Therefore, the output of this flip-flop 618 indicates the result of the judgment (block 103 in FIG. 8) as to whether or not to fast-forward the motor.

When flip-flop 618 is set and sends fast forward signal J, the fast forward operation (FIG. 8, block 104) is performed as follows.

From sequence controller 60, via line 60A, the high level output J of flip-flop 618 is sent to feed motor control circuit 7o of FIG.

On the other hand, a difference signal Y and a sign signal UD are sent to the feed motor control circuit 7o from a subtracter 58 through lines 58A and UD, respectively.
58B. The feed motor control circuit 70 receives these signals and sends a signal to the motor 8 to move the read head 10 by a distance corresponding to the address difference indicated by the difference signal Y in the movement direction indicated by the g-sign signal UD.
3 via line 70A. Motor 83 rotates in response to this signal, thereby causing read head 10 to move a predetermined amount.

The read head 10 includes a laser 2 and a mirror 3 that reflects light from the laser 2. Half mirror 4 and mirror 5. It consists of a focus lens 6, a photo selfie camera, and an amplifier 8.

These parts are mechanically fixed to each other and all of these parts are moved by a motor 83.

When this motor 83 performs a predetermined rotation and, as a result, the read head 10 is moved near the track of the target address, the feed motor control circuit 70 sends a signal FE indicating the end of fast forwarding to the sequence controller via a line 70B. 60
Send to. This signal FE is input to the reset terminal R of flip-flop 618. Therefore, flip-flop 618 is brought into a reset state by this signal FE.

The output J of the flip-flop 618 is inverted and then input to the trigger terminal (T) of the flip-flop 620. Therefore, flip-flop 620 is set when flip-flop 618 is reset. Therefore, flip-flop 620 outputs a signal indicating that the fast forward operation has ended. Note that the fast forward signal J is simultaneously sent to the error correction circuit 50 via the line 60G, indicating to the error correction circuit that fast forwarding is in progress.

After this fast forwarding, address reading operation 105 is sent as follows. The light reflected from the disk 94 passes through the mirror 5. It is detected by photoself through the half mirror 4 and amplified by the amplifier 8. At this time, a tracking device not shown in FIG.
The deviation between the position of the light spot irradiated on the top and the position of the recording groove is detected, and this signal is sent to the mirror control circuit to control the deflection angle of the mirror 5, thereby controlling the position of the light spot and the position of the recording groove. (track).

The FM wave amplified by the amplifier 8 is demodulated by the FMtji modulation circuit 12 and converted into an NTSC video signal (Fig. 2 V).
is converted to This video signal V is transmitted to the synchronization signal separation circuit 1
8, an address signal extracting circuit 24, and further distributed to a video switch 14 for monitor display. A synchronization signal separation circuit 18 separates horizontal synchronization pulses and vertical synchronization pulses from the video signal (2), and these pulses are frequency-adjusted by an AFC (automatic frequency adjustment) circuit 20 that includes a noise limiter, and are free from dropout components and the like. After noise is removed, the timing signal generation circuit 22
and is input to the rotation motor control circuit 76. The rotary motor control circuit 76 drives the rotary motor 78 at 1800 revolutions per minute while comparing the input horizontal synchronizing pulse and vertical synchronizing pulse with a reference pulse generated by an internal crystal oscillator.

Timing signal generator! '822 generates timing signals B, C, and D for reading address information and a signal E for controlling the jump timing of the mirror 5, as shown in FIG. 3, in response to the horizontal synchronization pulse and the vertical synchronization pulse. .

Timing signal B is a timing signal for extracting only the address bit from signal ■, timing C is a timing signal for reading the extracted address signal, and timing signal B is generated only in the case of an even field. The rising edge 80 determines the timing for determining the address signal reading result, and the falling edge 81
determines the timing for executing the determination.

(Details will be described later.) On the other hand, address signal sampling circuit 2
4 is a timing signal B input from the timing signal generation circuit 22 through line 22B, extracts only the address signal from the video signal, and outputs it through the AND gate 26 (n
+1) bits is input to the data input terminal of the shift register 28 having a capacity of +1) bits. The AND gate 26 is controlled by the signal MS on the line 60F from the sequence controller 60, and the read head is moved near the target address by the feed motor 83, and becomes open at the time when address information is to be read. The shift register 28 uses the timing signal C input from the timing signal generation circuit 22 to its Glock terminal via the line 22C as a shift clock signal.
(n+1) bit address signals are read one bit at a time.

The odd field address is now stored in the shift register 28 first. Furthermore, when reading the even field address following that field, the already stored odd field address signals are sequentially input from the shift register 28 to the shift register 29 having the same < (n+1) bit capacity in response to the timing signal C. . Shift register 29 receives timing signal C input via line 22G.
The input signals are stored sequentially using as a shift clock. During this time, the shift register 28 stores a new even field address in parallel with the storage operation of the shift register 29.

In this way, the addresses of even and odd fields for one screen near the target address are stored in the shift registers 28 and 29. Thus, an address read operation (FIG. 8, block 105) is performed. Next shift register 28.29
The contents of the lines 28A to the error check circuit 40, respectively.

29A, and the presence or absence of an error is determined (
Block 106).

FIG. 6 shows details of the error check circuit 40.

Comparator 43 compares the even and odd field address signals inputted from shift registers 28 and 29 through lines 28A and 29A, respectively, and if they match, outputs a high level match signal on line 43A. Output. Parity checkers 41 and 42 perform parity checking on the even field address signal and odd field address signal, respectively, and output the results on lines 41A and 42A. That is, each (n
+1) Each circuit outputs a high-level or low-level signal to indicate that there is no parity error or that there is a parity error, depending on whether the number of bits that are ``1'' in the bit address signal is odd or even. Therefore, on the output line 40A of the AND gate 44, the even field address signal and the odd field address signal match each other,
A high-level roaring signal OK is output only when there is no parity error. This signal OK is sent to the error correction circuit 5o and sequence controller 60 in FIG. 4 via the line 4OA. Parity checker 41 and 4
2 output lines 41A, 42A and lines 28A, 29
The even and odd field address bits (n bits excluding the parity bit) on A are sent as even and odd field data EV and OD, respectively, to the error correction circuit 50 of FIG. 4 via lines 40D and 40B, respectively. . Also, the odd field address bit on line 29A (
n bits) as the signal OD'#! /I.

C to the current address register 56 in FIG.

Thus, the error checking operation (Figure 8, block 10)
6) ends. If it is determined that there is an error as a result of the error check, the process moves to a +1 jump operation (FIG. 8, block 1o7).

This operation is processed in the sequence controller 60 (FIG. 5) as follows. OK signal is not output,
Therefore, the AND gate 622 is not opened, and therefore the flip-flop 620, which is set after the end of fast forwarding, is not reset. The output of this flip-flop 620 is input to an AND gate 629 via an OR gate 628.

In this state, the AND gate 629 is turned on by the pulse E outputted from the timing pulse generation circuit 22 (FIG. 4) via the line 22E with a delay of approximately one horizontal scanning period, and the pulse E is outputted via the line 60G. The level signal SJ is sent to the mirror control circuit 74 (FIG. 4). Upon receiving this signal, the mirror control circuit 74 outputs a signal for controlling the deflection angle of the mirror 5 onto a line 74B so that the light spot moves unconditionally by one track.

Thus +1 jump movement (Figure 8, block 107)
is completed, and the address reading operation of block 105 (FIG. 8) is performed again. If it is determined that there is no error as a result of this address reading operation, the read address is set to the current address register 5.
6 (FIG. 4) (FIG. 8, -Block 10)
8) is performed by the sequence controller 60 shown in FIG. 5 as follows. That is, the error check circuit 4
When the pulse D is input to the AND gate 622 in the sequence controller 60 in the state where the signal is outputted on the a/I OA at a high level O' due to 0, this gate is opened and the pulse D is output to the differential circuit. 624 and after being inverted, it is input to the positive terminal R of the Noritsubu flop 620. As a result, flip-flop 620 is reset at the falling edge of pulse D. The output of this flip-flop 620 and the output of the AND gate 622 are
The former is input through OR gate 630, and the latter is input directly to AND gate 632.

As a result, a high level signal AA is output from the AND gate 632.
is output only while pulse D is at high level. Furthermore, once this signal AA is output, it is not output thereafter because the flip-flop 620 is reset.

This signal AA is connected to the current address register 56 via line 60D.
(Figure 4). This register 56 receives this signal AA and takes in the read address signal OD' input via line 40C. In this way, the operation of fetching the read address into the register 56 (FIG. 8, block 10)
8) ends.

Almost parallel to this operation, an operation (block 109 in FIG. 8) of storing the read address in the correction memory in the error correction circuit 5o is performed. That is, the high level signal SJ of the flip-flop 620 is connected to the OR gates 628 and 66.
6 on 'ri60H. The signal RG on this line 60H is sent to the error correction circuit 50 and instructs the correction memory in that circuit to take in the read address signals EV and OD.

The operation of the error correction circuit 50 at this time will be explained later.

As a result of checking whether or not fast forwarding is necessary in block 103 of FIG. In the former case, the flip-flop 618 is not set and remains reset. Therefore, the fast forward signal J
is not output. Furthermore, the flip-flop 620 remains reset since no trigger signal is input thereto.

Further, after the operation in block 109 of FIG. 8 is completed, flip-flops 618 and 620 are in a reset state. In this state, a check as to whether the ±n jump (multi-jump) of block 110 in FIG. 8 is necessary is performed by determining whether the difference signal Y is larger than a predetermined value as follows. .

The flip-flop 640 is connected via the delay circuit 614 to
It is set by the activation signal T received.

The difference signal Y input from the subtracter 58 (FIG. 4) is sent to a register 636 in a comparator 634 in the controller 60.
It is compared with the value (ml) stored within. This value can be selected, for example, from 2 to 8, but here it is set to 3 as an example.

Comparator 634 outputs a high level signal when Y is less than ml. When the flip-flops 618 and 620 are in the reset state, the AND gate 638 is supplied with a high level signal inputted through the NOR gate 626, and together with the high level signal inputted from the comparator 634, the AND gate 638 turns on. As a result, flip-flop 640 is reset. On the other hand, comparator 6
34 does not output a high level signal when Y is greater than or equal to m□. Therefore, flip-flop 640 is not reset. In the end, the flip-flop is the result of comparing Y and m□,
In other words, it is displayed whether ±n jumps are necessary or not. The operation of block 110 in FIG. 8 is thus completed.

When Y>m□, ±n jumps (multi-jumps) are performed (FIG. 8, block 111). That is, the mirror control circuit 74 changes the deflection angle of the mirror 5 by ±n tracks. Control for this purpose is performed as follows. When flip-flops 618 and 620 are both in the reset state, NOR gate 626 outputs a high level signal.

On the other hand, since flip-flop 640 is in the set state, gate 642 is in the on state. and gate 62
7, when the signal E is input from the timing signal generation circuit 22 via the line 22E, the high level signal of the AND gate 642 is sent to the mirror control circuit 74 (the second Figure 4).

The mirror control circuit changes the deflection angle of the mirror 5 by 10 or - in response to this signal MJ and a sign signal UD inputted via line 58B from subtractor 58 (FIG. 4) via line 58B.
A signal that changes by n tracks is sent out. The ±n jump operation is thus completed while pulse E is high (FIG. 8, block 111). The post-jump mirror control circuit 74 sends a signal Jn indicating the number of jumps via line 74A to the error correction circuit 50 where it is stored. Thereafter, during the next revolution, the odd and even field addresses are read into shift registers 29 and 28 (FIG. 4), respectively (FIG. 8, block 112). This read address is checked for errors in the error check circuit 40 (FIG. 8, block 113). As a result of this error check, if it is found that there is no error, an operation is performed to set the read address OD' into the current address register 56 (FIG. 8, block 108). This operation is performed as follows.

Since the high level signal OK is input from the error check circuit 40 to the AND gate 622 in the sequence controller 60 shown in FIG. Outputs a level signal. This output is AND gate 6
32. Another input terminal of AND gate 632 is connected to AND gate 642 . or gate 644 and 63
A high-level signal is input from the flip-flop 640 via 0. Therefore, the AND gate 632 outputs a high level signal AA while the signal R is input to the AND gate 622. This signal AA causes the current address register 56 (FIG. 4) to take in the address data OD', as described above.

When the operation of block 108 in FIG. 8 is thus completed, the operation of block 109 in FIG. 8 is performed.

For this purpose, the error correction circuit 50 receives a high level signal from the AND gate 642 and outputs a high level signal RG from the OR gate 666.

On the other hand, if the result of the error check in block 113 in FIG. 8 is that there is an error, the operation in block 114 in FIG. 8 is performed by the sequence controller 60 in FIG. 5 as follows. That is, in this case, since the signal OK is not output from the error check circuit 40, the AND gate 622 in the controller 60 remains off, and the line 6
No signal AA is output on 0D. Instead, AND gate 648 outputs a high level signal.

That is, the AND gate 646 is on because the inverted OK signal and the high level signal of the AND gate 642 are input. The high level output level signal of the AND gate 646 is output to the AND gate 648 .

This high level signal activates the pulse train generation circuit 652. This circuit 652 outputs the value stored in the register 654 (
generate a number of pulse trains equal to n). This n is smaller than ml, for example chosen to be 2. The output of this circuit 652 is input to an AND gate 656. and gate 65
6 is in an open state due to the high level signal from the AND gate 642, so the input pulse train is output as is. This pulse train signal is connected to line 60 as signal C'LK.
It is input to the current address register 56 (FIG. 4) via E. This current address register 56 is composed of a counter that can go up and down, and responds to the signal CLK and responds to the code signal 'UD input from the subtracter 58 (Fig. JJ4) via the line 58B. In response, it counts up or down by n. In this way, corresponding to the ±n jump, the value 1 of RR+n or RR-n is stored in the current address register 56, assuming that the address before the jump is RR (FIG. 8, block 11/l).

After this operation, the operation of block 115 in FIG. 8 is performed. This operation is performed in the error correction circuit 50 IC in response to the signal RG, which is at a high level, as in the case where it is determined that there is no error in block 113 of FIG.

After the operations in blocks 109 and 115 in FIG. 8 are completed, block 110 is performed again by the sequence controller 1-roller in FIG.

A comparator 634 compares the difference signal Y when a new address value is set in the current address register 56 (FIG. 4) and the value in the register 636.

As long as the comparator 634 does not output a high level signal, the operations from blocks 111 to 109 or 115 are repeated. When Y≦m□ and a high level signal is output from the comparator 634, the operation of block 116 begins.

A high level signal from comparator 634 resets flip-flop 640. As a result, the AND gate 664, which had been closed due to the high level signal of the flip-flop 640, becomes open and the flip-flop 662
Outputs the output as is. Flip-flop 662 is set by the output of delay circuit 61/I.

The difference signal Y is input to the decoder 658, and its output is input to the reset terminal of the flip-flop 662 via an AND gate 660. This decoder output outputs a high level signal when signal Y is equal to 0. Flip-flop 674 has already input the output of delay circuit 614 to its reset terminal via OR gate 672.
It has been reset. When AND gate 660 outputs a high level signal, flip-flop 674 is set by this high level signal. As a result, a high-level signal RP is output on the line 60I, and a high-level signal PP is output for both the signals RI and OK from the anime game 1-676 on the line 60J. This is when the target address and the value in the current address register are equal.

When they are not equal, flip-flop 662 is not reset. Therefore, AND gate 664 outputs a high level signal, and OR gate 628 . A high level signal SJ is output via AND gate 629 onto line 60C. This signal SJ is output when signal E is input from line 22E. Signal SJ is line 60C
via the mirror control circuit 74 (FIG. 4).

The mirror control circuit 74 receives this signal SJ and the subtracter 58 (
+1 or - depending on the code signal UD input from Fig. 4).
A signal is sent to mirror 5 to jump the number of tracks of 1. At this time, a signal Jn indicating the number of jumps is sent from the mirror control circuit 74 to the error correction circuit 50 via the line 74A.
send to

The operation of block 117 in FIG. 8 is thus completed.

During one rotation after this, the address of the track after this jump is read again (FIG. 8, block 118). Furthermore, an error check is performed on this read address (FIG. 8, block 119), and if there is an error, the AND gate 646 is checked at the next rising edge of the timing signal.
, 648 are all turned on, and a high level signal is output from the AND gate 648. At this time, AND gate 65
Since a high level signal is inputted to AND gate 664, AND gate 650 outputs a signal that is at high level while signal 0 is at high level as a single clock pulse CLK onto line 60E. On the other hand, at this time, the AND gate 656 is in an off state because the flip-flop 640 has been reset, and does not output the pulse train from the pulse train generation circuit 652.

This signal CLK is sent to the current address register 56 (FIG. 4) via line 60E. Current address register 56 counts up or down by one in response to signal CLK and sign signal UD from subtractor 58 (FIG. 4). In this way, RR+1 or RR-1 is stored in the current address register 56 with respect to the value RR before the jump, and the operation of block 120 is performed. Thereafter, the operation moves to block 121 (FIG. 8). This is ANDGATE664. Orgate 628. Error correction circuit 50 performs this in response to a high level signal RG output from flip-flop 662 on line 60H via OR gate 666.

If it is determined that there is no error in the operation of block 119 (FIG. 8), that is, if the signal OK is output on line 40A, signal AA is output on line 60D, and M40C
The upper signal OD' is set in register 56 (FIG. 8, block 122).

Further, the signal RG causes the error correction circuit 50 to output the line 4oA.
Signals on 40B and 40D are OK and OD.

Capture the EV (Figure 8, block 123).

After that, the operation moves to block 116, and blocks 116 to 121 or 1 until reaching the target address is detected.
The operations 16 to 123 are repeated. When it is detected that the target address has been reached, the decoder 658 outputs a high level signal and resets the flip-flops 662 to 1.
do.

The processing from block 124 onward in this resultant method is performed by the error correction circuit 50. These processes as well as the processes of blocks 109, 115, 121, and 123 whose explanations are omitted will be explained with reference to FIG.

FIG. 7 shows an error correction circuit 50 constructed using a one-chip microprocessor.

The microcomputer system 250 includes a microprocessor 251 (for example, Intel 18080 model), an input/output (Ilo) bus 250A, and a microprocessor 251.
I10 bus controller 2 that controls data transfer between
52. A status control circuit 2531 that decodes the status of the microprocessor 251 and controls the I10 bus controller 252. An interrupt control circuit 254 that controls interrupts to the microprocessor 251 based on interrupt signals input via the interrupt bus 257A. A clock generator 255 that determines the machine cycles of the microprocessor 251. It consists of main memory 256. The main memory 256 has a read only memory (ROM) for storing control programs and a random access memory (RAM) for storing input/output data for calculations and the like.

Each interrupt bus 257A has an interrupt level of 3°2.1.
Bus drivers 257, 258, and 259 are connected to the terminal. The lower the interrupt level, the higher the priority of the interrupt.

Random access memories 277, 278, and 279 store address data OD output from the error check circuit 40.
, EV, and the number of mirror jumps J'n output from the mirror control circuit 74, respectively. The storage address for data into this random access memory is provided by program counter 266.

This stored data is used to correct erroneous addresses.

The counter 288 is for counting the number of times the track address has been read repeatedly after the target address has been detected.

The execution programs of the microcomputer system 250 are divided into two types. These selections are made by the bus driver 25.
It depends on the interrupt level input to 7, 258, and 259, respectively. When a signal is input to the bus driver 259,
Microprocessor 251 is a flip-flop 618
, 620° 640, '662, 674 (Fig. 5) and identifies which flow in Fig. 8 is currently being executed.

When signal P is input to bus driver 258, an address error correction routine (block 125 in FIG. 8) is activated.

When signal PP is input to bus driver 257, an address confirmation routine (block 126 in FIG. 8) is activated.

First, the loading of data into the random access memories 277-279 will be explained.

This is block 109゜11 in the flow in Figure 8.
5. Corresponds to the operations of 121 and 123. When the fast forward signal J is input from the sequence controller 60 via the line 60G under the condition that the signals P and PP are not input, this signal J is input to the reset terminal of the program counter 266 via the OR gate 275, and the program Counter 266 is reset to zero. After that, fast forwarding ends,
When the signal RG is input while the signal RG requesting storage of data in the correction memories 277, 278, 279 is input, the AND gate 271 is opened and the signal is passed through the NOR gate 270 to the memory 277. 278,279
is input to the write terminal (WE) of . At the same time, the output of this NOR gate 270 is input to the trigger terminal (T) of the program counter 266.

Therefore, the memories 277, 278, and 279 each receive a signal ○p at the address indicated by the program counter 266.
, EV, and Jn at the falling edge of the signal. At the same time as this signal falls, the program counter 266 counts up.

In this way, each time a signal is applied, the memory 277.27
Import data to 8,279.

Thereafter, when the test in block 116 of FIG. 8 detects that the target address is registered in the current address register 56 (FIG. 4), the signal RG goes low, as described above.

As a result of the signal RG becoming low level, the gate 271 is turned off, and no signal is sent to the write terminals of the memories 277 to 279, so that no data is written.

Now, the microprocessor 251 is the bus driver 25
9 to the line 22 from the timing signal generation circuit 22.
For each input through D, the flip-flops 618, 620, 640, in the sequence controller 1-roller 60,
662 and 674 from the AND gate 268 via the line 60L is sent onto the I10 bus 250A, and from the output of the captured flip-flop,
It is determined which operation in the operation flow shown in FIG. 8 is currently being executed.

Therefore, when the signal RG becomes low level, this FLG
From the signal to the microprocessor block 11 of FIG.
It is known that the process in step 6 has been completed.

At this time, the microprocessor 251 executes an instruction to import the contents j of the program counter 266 into the main memory 256 via the AND gate 263. Furthermore, after the execution of this instruction, the contents R of the current address register 56 (FIG. 4)
An instruction to load R into main memory 256 via line 56A and AND gate 261 is executed.

Thereafter, the error correction circuit 50 performs the operations starting from block 124 in FIG.

A test is made to see if an error has been detected when the signal RG goes low (block 124). In this test, when it is detected that there is no error and the output OK of the error check circuit 40 is at a high level, a high level signal is output from the AND gate 676 in the sequence controller 60 in FIG. 5 at the time when the signal becomes high level. A signal PP is output. This signal PP is input to the microcomputer system 250 through line 60J and bus driver 257.

Upon receiving this signal, microcomputer system 250 performs the next confirmation operation (block 125 in FIG. 8).

This confirmation operation is shown in FIG. In block 131, among the data EV in the memory 278, data (RIE) relating to the track read immediately before the current track is stored.
and the number of tracks Jo that the light beam jumped to reach the current track from that track among the data Jn in the memory 279. )
Check whether it is equal to or not.

To this end, microcomputer system 250 sends an instruction to read data RIE in memory 278 and the address at that time onto bus 250A. When the decoder 261 decodes this reading instruction, the decoder 261
sends a signal (not shown) to open AND gate 262 and to program counter 266 to set the address signal sent from AND gate 262.

Furthermore, the output of the decoder 261 causes an AND gate 265
is opened and the data R read out from the memory 278 by the address signal which is the output of the program counter 266.
IE is read out to main memory 256. Similarly, data ROE is transferred from the memory 277 to the main memory 256.
The data is read out through gate 264.

Similarly, data JO is then read out from memory 279 through gate 266 to main memory 256 .

With these data, RI E 1J o = RO
E is checked. If this check determines that they are not equal, block 132 (FIG. 9)
processing is performed. In other words, data ○D in memory 277
Among them, the data (R10) regarding the track read immediately before the current track, and the number of tracks Jo that the light beam jumped to reach the current track from that track among the data Jn in the memory 279. It is checked whether the sum is equal to the data RO○ for the current track among the data OD in the memory 277. As a result of the tests in blocks 131 and 132 (FIG. 9), if either test is When it is determined that the condition holds true, the operation of block 127 in FIG. 8 is performed. That is, if any of the tests is satisfied as a result of the recognition, the microprocessor 251 sends a command to the I10 bus 250A to permit display of the image of the currently read track. This permission command is decoded from the decoder 261.
The allowable signal CR obtained by
It is sent to the reset terminal of 8 and resets it.

As a result of this flip-flop 608 being reset, the video switch 14 (FIG. 4) sends the output of the FM demodulation circuit 12 to the CRT display device 16 to display an image.

If the test at block 132 (FIG. 9) reveals that the alternative test also fails, then block 126 of FIG. 8 is performed.

By checking in accordance with FIG. 9 in this manner, an extremely accurate error check has been performed.

Note that during the above processing, the reset terminal of the counter 288 remains reset because the OK multiplier signal is input via the gates 285 and 287.

On the other hand, when the signal RG becomes low level, it is determined that there is an error (FIG. 8, block 124), and when the output OK of the error check circuit 40 is low level, the signal PP is not sent out. Further, the counter 288 is not reset because of the low level of the OK double signal, but counts up when the signal inputted through the gate 286 changes from high level to low level. Then, the address of the same track is repeatedly read out (FIG. 8, block 129), an error check is performed (FIG. 8, block 124), and this read operation is repeated unless there is no error.

Test whether the number of repetitions has reached a predetermined value ma (for example, 8 to 16) (FIG. 8, block 128)L,
, when it is detected that the predetermined value has been reached, the counter 288
overflows and outputs signal P. This signal P is transmitted through a line 50A and a gate 672 (FIG. ffi5) to a flip-flop 674 (
(Figure 5). As a result, flip-flop 6
74 does not output the signal RP. On the other hand, this signal P is transmitted to the microcomputer system 250 and the bus driver 258.
sent via. Microcomputer system 25
0 performs error correction operation (block 12) upon receiving this signal.
6. Figure 8) begins. The details of this error correction operation are as shown in FIG.

First, while referring to j already stored in the main memory 256, the data RiO in the memory 277 and the data RiE in the memory 278 regarding the track retrieved i times before the current track are sequentially read. Detect matches and do this for all i (i=0 to j) (block 210).

As a result of the comparison, if a match is found for all i, ROE and the data R in the current address register 56 (FIG. 4)
Detect a match with R (block ~220)
.

This data RR is taken into main memory 256 via line 56A and AND gate 267.

As a result of this comparison, if a match is found, the operation of block 127 in FIG. 8 is performed.

If the result of matching in block 210 is that all i
Block 23 if no match is found for
After setting the constant a to 0 as shown in block 24
Perform the 0 test. That is, of the address data EV in the memory 278 regarding the track read a number of times before reading the current track, the bit representing the result of the parity check (this is referred to as PaE) is re
1.

(block 240). When PaE=O, there is a parity error as a result of the parity check. At this time, the operation moves to block 242. In this block, it is determined whether or not the bit representing the parity check result (this is expressed as PaO) in the address data OD regarding the track read out a number of times before the current track is read out in the memory 277 is It171. Check whether As a result of this check, PaE=O.

When it is determined that Pa0=1, RaE and RaO are exchanged (block 244). RaE here.

RaO stores memories 278 and 278, respectively, for tracks that were retrieved a times before the current track is retrieved.
This is data within 277. Block 246,
241 is repeated until <a=j. In this way, at least the memory 278 stores data free of parity errors.

However, the result of the test in block 242 is 1pao=rr
If it is on, the random access operation is stopped without sending the signal CR that allows display of one image as an address error onto the line 50B.

However, if at least one of PaE and PoE is 1/I It until a=j according to block 241, then the operation of block 250 is performed. The operation of this block 250 is performed in block 220 with ROE4
This is also performed when it is determined to be RR. Bron, Ri250
~260, sequentially RR-JO=R1'E, RIE-J
1=R2E,...Rj-I E-Jj
Compare whether 1=RjE. These blocks 250
As a result of the comparisons in steps 260 to 260, if there is a mismatch in any of the comparisons, it is determined that there is an error. If a match is found in all cases, the operation of block 127 in FIG. 8 is performed.

As described above, it is possible to detect a target address with extremely high reliability. In the above description, the control signal MS to the gate 26, which controls reading of addresses into the shift registers 28 and 29, is supplied to the sequence controller (fifth
is applied on line 60F from OR gate 670 in FIG.

The inputs to this OR gate 670 are the output of AND gate 642 and the output of OR gate 668. or gate 66
The inputs of 8 are the output of flip-flop 674 and the output of OR gate 628.

It is also possible to omit the operation of block 125 in the flowchart of FIG. 8 and to perform the operation of block 127 immediately after the determination of No in the operation of block 124 is made.

The embodiment described above is a highly reliable check-type random access system for image information files, but tracking The address is read every time there is an access jump in the mirror, an error is checked, and the address is registered in the error correction register group. Such a method can be said to be the result of pursuing certainty (reliability) even if it sacrifices the characteristics of multiple jumps5. Therefore, when the reference address after fast-forward movement is determined, jump to the target address by executing multiple jumps - times, and read surrounding addresses only if that address has caused an error. Accordingly, the method of automatically correcting address errors is effective in shortening access time without significantly impairing reliability compared to the previous embodiment.

FIG. 11 shows a flowchart of the high speed random access system.

Differences from the flow in FIG. 8 are (1) Blocks 109, 115, 121°12 in FIG.
There is no 3.

(2) Blocks 112 and 113 in FIG. 8 are absent, and block 114 is executed without making an error determination midway.

(3) There are no blocks 118 and 119 in FIG. 8, and block 120 is executed without making an error determination midway.

(4) There is no block 125 in FIG. 8, and monitor display is allowed without confirmation.

(5) The processing after block 128 in FIG. 8 is different from the processing after block 128 in FIG.

FIG. 12 is a logic circuit diagram of the sequence controller 60 for implementing the flow of FIG. 11.

- Elements indicated by dashed reference numbers in the figures are newly provided. Components having the same reference numerals as those in FIG. 5 are identical to the elements in FIG. Further, signals represented by the same symbols as the signals in FIG. 5 are signals for performing the same control as the signals in FIG. 5.

According to the above (1), the signal RG in FIG. 12 differs from the signal RG in FIG. 5 in that it is generated only in the operation subsequent to the operation of block 128 (FIG. 11).

Corresponding to the above (4), there is no circuit for generating the signal PP in FIG. 5 from the circuit in FIG. 12. Therefore, corresponding to FIG. 12, the error correction circuit 50 includes the bus driver 257 (
Figure 7) is unnecessary.

Corresponding to the above (5), FIG. 12 shows an R-S flip-flop 680' for the multiple jump request flag near the stop position.
, a flip-flop 682' for J- for a stop position return request flag, a counter 684' for counting the number of returns, and an AND gate 686'. Of course (2), (3
) Correspondingly, the circuit for generating the signals AA and CLK in FIG. 12 is different from that in FIG. 5, but the details are clear from the circuit diagram and the following explanation of the operation, so the explanation will be omitted.

The flow shown in FIG. 11 will be described below with reference to FIG. 12, focusing on the differences from that shown in FIG. 8. Furthermore, the 8th
Blocks with the same numbers in this figure and FIG. 12 are the same operation blocks. If the error check in block 106 passes, the read address is stored in the current address register 56 as the reference address after fast forwarding (block 108).
, serves as an input to the multiple jump determination block 110. Register 636 (first register) for multiple jump determination (110)
The data in Figure 2) is fixed at m1 = 2, and if it is greater than or equal to m1, multiple jumps (±n jumps) are executed in block 111.
), this multiple jump number is immediately added to the contents (RR) of the current address register 56 (FIG. 4), and the process returns to the register 56 (block 114) and multiple jump determination (block 110). At this time, register 65
4 (FIG. 12), the value n is chosen to be 2. When it is determined in block 110 that there is no need for multiple jumps (i.e. m
1=2), if the error between the value of the current address register 56 and the target value is +1 or address O, the block 11
6, and if there is an error of ±1 address, execute a single jump of +1 or -1 in block 117, and immediately transfer the RR to the current address register 56.
store the value +1 or RR-1 (block 120);
Then block 110 returns. When it is determined in block 116 that the target address has been reached (the current address at this time is 1, which normally indicates the predicted address), the parity pits are checked for each of the odd field address and even field address. and check the degree of agreement between the two (block 124);
If it passes, it is determined that the content RR of the current address register 56 is a normal value, an image is displayed on the monitor television screen (block 127), and the random access operation is terminated. In the error check (block 124), if it is determined that there is an address error, block 124
→Block 128 →Block 129 loop is executed m3 times by the error correction circuit 50, and only when an address error still occurs, the address recording status near the last access is registered in the automatic correction register group.

In other words, the number of repeated checks after access is stopped is m3.
When the value becomes larger, the counter 288 in the error correction circuit 50
(FIG. 7) overflows and signal P is output.

The rise of this signal P sets the multiple jump request flag flip-flop 680' and outputs the multiple jump command U' to the mirror control circuit 74 via the line 60M (this is not shown in FIG. 4). . At this time, or game) -667', AND gate 627 and line 60
Signal MJ is output to mirror control circuit 74 via B. The mirror control circuit 74 is configured to jump by the number of tracks -J m (J m = 5 to 10) when it receives both the signals U' and MJ.

Thus, -Jm multiple jumps are executed consecutively (block 138). At this time, the flip-flop 680
' high level output U' is OR gate 667', 670
via line 60F. The signal MS on line 60F is sent to AND gate 26 (FIG. 4), which allows shift registers 28, 29 to take in the address signal of the new jump destination track. In this way, a new address signal is taken in after one rotation of the disk (block 15o). The high level output U' of the flip-flop 680' is connected to l11 through the OR gate 666'.
Sent on 60H. The signal RG on this line 60H is sent to the error correction circuit 5o, and instructs the read address signal to be taken into the correction memories 277 and 278. The operation of block 151 is thus performed. At this time, as the pulse D falls, the flip-flop 680
The contents of ' are transferred to flip-flop 682', setting flip-flop 682'. flip flop 6
Terminal when setting 82'. At the falling edge of the output of , flip-flop 680' is reset.

The output U' of flip-flop 682' is sent to mirror control circuit 74 via line 6ON (not shown in FIG. 4). At this time, U# is OR gate 630'
, through AND gate 629 on line 60C. Signal SJ on line 60C is sent to mirror control circuit 74.

The mirror control circuit 74 is configured to receive these signals U# and SJ and jump by one trap in the opposite direction to the previous jump direction of -Jm.

The operation of block 153 is thus performed.

Signal U' is routed to line 6 via OR gates 668', 670.
Sent on 0F. Signal MS on line 60F instructs to take in the address into shift register 28.29 (FIG. ffi4). In this way, after one revolution, the address of the new post-jump track is taken into the correction memories 277 and 278 in the error correction circuit 50. At this time, the jump number signal Jm from the mirror control circuit is transmitted to the correction memory 297.
be taken in.

The act of block 150 is thus performed. Thereafter, the operations of blocks 151, 153, and 150 are repeated Jm times. When the same number of repetitions exceeds Jm, the operation moves to block 126. A counter 684' checks whether the number of repetitions Jm exceeds Jm. That is, after flip-flop 682 is set, pulse D
Each time is input, ant game)-686' is opened and the counter 684' counts up by one.

In this way, Jm times of signals are input, so Jm times +1
After the jump is performed, when the J m +1st signal is input, the counter 684 registers at the rising edge of the signal.
' overflows and outputs 1. This resets flip-flop 682'. Thus the signal U
is no longer output and the +1 jump is aborted. Error correction circuit 50 monitors the output of flip-flops 680', 682' via line 60L' and performs error correction routine 126 when the output of flip-flop 682 reaches a lower level than a high level. .

As described above, addresses can be detected quickly and accurately.

〔Effect of the invention〕

As described above, according to the present invention, when searching for a target track by changing the target track, a multi-jump is repeated in which the target track is changed one by one, and the identification signal of the target track is detected for each multi-jump to find the desired track. Since this is performed while detecting the difference between the identification signal and the identification signal corresponding to the track, highly reliable and high-speed access can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a video disk recording state diagram, FIG. 2 is a read signal diagram, FIG. 3 is an address signal and related timing signal diagram, and FIG. 4 is a video file system for implementing the access method of the present invention. 5 is a logic circuit diagram of the sequence controller, FIG. 6 is a block diagram of the error check circuit, FIG. 7 is a block diagram of the error correction circuit, FIG. 8 is an operation flowchart of the device in FIG. 4, and FIG. 9 is a detailed flowchart of block 125 in FIG. 8, FIG. 10 is a detailed flowchart of block 126 in FIG. 8, FIG. 11 is a flowchart of the operation of a reference example of the present invention, and FIG. Logical development diagram. 58: Subtractor, 250: Microcomputer system, 277-279: Memory No. 1, No. 2, M3 layer CE)'-111--→----'L No. 4, No. l!?Kuni 1θ Kuni 11

Claims (1)

[Claims] 1. A light spot is emitted from a head whose position is controlled by a first moving means onto a recording medium having a track on which an identification signal is recorded, and the light spot corresponds to the identification signal of the target track on which the light spot is located and the desired track. Detects the difference between the identification signal and the identification signal, compares the value of the difference with a predetermined value, and moves the light by the second moving means provided in the head until the value of the difference becomes smaller than the predetermined value. By moving the irradiation position of the spot, the number of target tracks on which the light spot is located is repeatedly changed one by one, and each time the number of target tracks is changed one by one, the identification signal of the target track is detected and the identification signal corresponding to the desired track is identified. A difference between the light spot and the signal is detected, and when the value of the difference is smaller than the predetermined value, the irradiation position of the light spot is moved by the second moving means according to the value of the difference, and the target track where the spot is located is moved. A random access method characterized in that the light spot is positioned on the desired track while detecting the identification signal of the target track each time the light spot is changed.