JPS61293180A - Protecting device for gto thyristor inverter - Google Patents

Abstract

PURPOSE:To prevent the output overcurrent of an inverter from generating by forcibly extinguishing all other normal GTO thyristors when the defect of at least one GTO is detected. CONSTITUTION:A main circuit has 3-phase bridge inverters of GTO thyristors G11-G32 as switching elements, current detectors 2 are connected with the anode sides of the GTOs, and high voltage side circuits 3A-3F are connected between the gates and the cathodes of the GTOs. Logic calculators 41-43 are connected with the high voltage side circuits 3A-3F. When the defect of at least one GTO thyristor is detected by defect detectors 5-7, the calculators 41-43 forcibly extinguish all other normal GTO thyristors.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an inverter using a so-called gate turn-or-thyristor (hereinafter also simply referred to as GTO) whose conduction and non-conduction states can be controlled by a gate signal. [Prior Art] As a protection device for such an inverter, the applicant has proposed the following.

That is, by monitoring the voltage between the gate and cathode (G-) of the GTO, the GTO of the upper and lower arms of each phase is
Detects the ON (conductivity) and OFF' (non-conduction) states of the In order to avoid an arm short-circuit accident due to the firing of the other GTO in the event that the other GTO becomes disabled, it is also possible to detect that both the upper and lower arm GTOs are in the ON state for other arm short-circuit accidents. This system immediately generates a failure signal to provide protection. In the latter case (in the case of an arm short-circuit accident), all GTOs and short-circuit thyristors are fired immediately when a fault signal is generated.

[Problem that the invention seeks to solve]

According to this method, if one of the upper or lower arms of one phase of the inverter is unable to turn off, it is possible to avoid an arm short-circuit accident due to the other GTO ignition. Therefore, no overcurrent will occur due to an arm short circuit, but even if an arm short circuit accident is avoided, if the GTO is faulty, the GT of the other phase
Since the ON/OFF pulse is still supplied to O, an overcurrent is generated in the GTO via the load circuit due to unbalance between each phase.
There is a risk that this will not only blow out the fuse in the DC intermediate circuit, but also cause an accident to spread.

Incidentally, such a phenomenon occurs regardless of the arm short-circuit M function.

Therefore, an object of the present invention is to prevent overcurrent caused by a failure of G'l'0 and to further enhance the poetry writing function.

[Means for solving problems]

A monitoring means for monitoring conduction or non-conduction of each GTO is provided, and a failure detection means for detecting a failure of the GTO based on the monitoring result and a turn-off command.

[Effect]

The above monitoring means monitors the voltage between the gate and cathode (G-K) of the GTO and detects the ON/OFF state of the 8 GTOs in the upper and lower arms of each phase, and the fault detection means detects abnormalities such as GTO failure. When detected, the normal GTO of the other phase is forcibly extinguished, and in the process of forced extinguishing, if the anode current of the GTO reaches an overcurrent that exceeds its controllable current, , the inverter is protected by forcing all GTOs to fire.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a DC power supply, 2 is a current detector, and 3 (3
A, 3B, 3F) is the high voltage side circuit, 4 (41
, 42, 43) are logic operation circuits, 5 is a failure detection circuit, and 6
is an overcurrent detection circuit, 7 is an OR circuit, 8 is an inverter control device, 011~G32 are GT0 thyristors, D11~
D32 is a feedback diode.

That is, the main circuit consists of a three-phase bridge inverter using GTO thyristors Gll to G32 as switching elements, and a current detector 2 is connected in series to the anode side of each GTO.

A high voltage side circuit 3 (3A to 3F) is connected between the cathodes. A logic operation circuit 4 is connected to the high voltage side circuit 3,
More specifically, a logical operation circuit 41 operates for the high voltage side circuits 3A and 3B, a logical operation circuit 42 operates for the high voltage side circuits 3C and 3D, and a logical operation circuit operates for the high voltage side circuits 3Bs and 3F'. Circuit 43 is connected. In FIG. 1, the connection relationship of one part is illustrated by dotted lines, but the other parts are connected in the same manner. This logic operation circuit 4
The GTO turn-off command signal pH, which is the output of the inverter control device 8, and PI3.・・・・・・P32 and GTO, which is the output of the high voltage side circuit 3, are turned on (conducting) or off (
(non-conducting) status signals C1l, C12゜...C3
2 and GT0 failure code 05 which is the output of the failure detection circuit 5.
and the GTO overcurrent signal 0 which is the output of the overcurrent detection circuit 6.
6 and the GTO forced firing signal 07 which is the output signal of the OR circuit 7, and the Louis logic calculation circuit 4 generates the GTO firing signals Qll, Q12 . ...
...G32) and arm short circuit signal Sl, 82.83
Output.

The GTO failure detection circuit 5 receives GTO turn-off signals Qll, Q12 .・・・・・・G3
2 and the GTO ON or OFF state signals C1l, C12, . The GTO overcurrent detection circuit 6 receives the output lG11, lG12 .・・・・・・
- Outputs qTO overcurrent signal 06 using lG32 as input. Further, the OR circuit 7 receives the arm short circuit signal s1. which is the output of the logic operation circuit 41.42.43 provided corresponding to each phase. s2) Using S3 as input, output GTO forced ignition signal 07. Furthermore, the inverter control device 8 performs arithmetic and adjustment control to supply desired power to the load, and outputs a point-extinguishing command signal P11°PI of each G'll'O.
3. ...Output P32.

Next, the configuration and operation of each part will be sequentially explained using 2A to 2EIN.

As shown in Figure 1H2A, the high voltage side circuit 3 (3A to 3F) includes a gate drive circuit 31 for supplying gate current to the GTO, a comparison circuit 33 for monitoring the ON or OFF state of the GTO, etc. It consists of As long as the GTO is normal, the voltage between the gate and cathode (G-K) of the GTO thyristor is approximately +0.7V to +1.5V when it is conducting.
A voltage of approximately V is applied, and a negative voltage that is in the non-conducting state is applied. Therefore, by monitoring this voltage,
It is possible to detect whether the GTO thyristor is conducting or non-conducting. Note that if the GTO thyristor is destroyed due to turn-off failure or the like, this can be detected because the gate cathode is short-circuited and no negative voltage is applied. Further, in this case, the voltage between the gate and cathode is used to detect conduction (ON) or non-conduction (OFF) of the GTO thyristor, but the voltage between the anode and cathode may also be used. The gate drive circuit 31 is the same as the conventional system that supplies gate current to the GTO thyristors Gll-G32, and the voltage detector 32 consists of a voltage dividing circuit of resistors R11 and 12,
The voltage between the gate and cathode of G32 is input, and an appropriate voltage proportional to the voltage is output. Further, the comparison circuit 33 converts the output voltage of the voltage detector 32, which outputs a voltage proportional to the voltage between the gate and cathode of the GTO thyristors Gll to G32, into a reference voltage VGKT using the comparator CP3.
Compare with. For example, the comparator CP3 outputs a logic "1" when the gates and cathodes of the GTO thyristors Gll to G32 are negatively reverse biased, and outputs a logic 60" when there is no reverse bias. Comparator CP3 The output of is the signal C1l isolated by the photocoupler PC.
, C12, . . . C32.

I'll leave the explanation of logic operation circuit 4 for later, and then move on to 9.
j/l −
The failure detection circuit 5 will be explained with reference to FIG. 2C.

The GTO failure detection circuit 5 receives the output signal Q of the logic operation circuit 4.
11 y Q 12 v......Each GTOO point extinguishing signal which is G32 and high voltage side circuit 3 (3A to 3F
) output signals C1l, C12, . . . C32, which are ON and OFF state signals of each GTO, are input.
After exclusive ORing the respective input signals corresponding to each GTO using exclusive OR EXOR, resistor 5. The signal is introduced into a voltage comparator CP5 through a filter circuit consisting of a diode D5 and a capacitor C5. This voltage comparator CP5 compares the output from the filter circuit with the voltage V5 of the reference voltage setter 5F35. In addition,
The filter circuit is operating normally. For example, when detecting the transition from ON to OFF of the GTO thyristor 11, there is a delay from the off command signal Qll of the GTO thyristor Gll to the accumulation time when the GTO thyristor Gll is turned off. Therefore, it is provided for the purpose of delaying detection by a time corresponding to this accumulation time. This circuit 51 is
For example, it is provided corresponding to the GTO thyristor Gll, and is similarly provided for the other GTO thyristors 012 to G32 (see 52 to 56). Then, each output passes through the AND gate AND5,
51 and 52.

Here, the output signals Qll, Q12) of the logic operation circuit 4
...Each GTOO point extinguishing signal, which is G32, is
It is “H” level when GTO is ignited, and “L” when it is extinguished.
level. In addition, the output signals C1l, C12, old...C32 of the high voltage side circuits 3A to 3F, which are the ON and OFF state signals of each GTO, are "L" level when the GTO is ignited, and "H" when it is extinguished. ``It's the level. As a result, the output of EXOR (EXOR) is at the 'L' level when the GTO is operating normally according to the turn-off signal.

If the GTO is destroyed due to turn-off failure, etc., the GTO
The TOO point extinguishing signal no longer corresponds to the ON and OFF state signals, and the output of the exclusive OR gate becomes H.
``level, and the outputs of voltage comparators CP and 5 become ``L''. When one or more GTO failures are detected, the output of the AND5 goes to the ``L'' level, and this signal is transmitted to the next stage as described in 1. The output 05 of the GTO failure detection circuit 5 continues to output an L'' level failure signal until the reset switch SW5 is pressed.

Next, the GTO overcurrent detection circuit 6 will be explained with reference to FIG. 2D.

The GTO overcurrent detection circuit 6 is connected in series to the anode side of each GTO, and the output of the current detector 2 outputs a voltage proportional to the anode current of the GTO IG 11 , I
G 12 e...Inputs lG32 and outputs overcurrent signal 06. That is, input lG11,
lG12,...lG32 are respectively led to voltage comparators CP61 to CP66, and are connected to reference voltage film regulator SE.
It is compared with voltage V6 of 6. Voltage comparator CP6 is GT
When an overcurrent occurs in O, a signal of ``L'' level is output. The output of AND6 is one or more GTO
When a failure is detected in the GTO, it becomes 'L' level, and this signal is led to the NAND game (NA'ND61, 62) which constitutes the memory circuit provided at the next stage, and thereby the GTO
The output 06 of the overcurrent detection circuit 6 is a reset switch SW.
It continues to output an overcurrent signal of "wH" level (be careful how to take out output 06) until 6 is pressed.

As shown in FIG. 2E, the OR circuit 7 receives the outputs Sl, 82 . It is composed of an OR game (OR, 7) for inputting and concatenating the arm short circuit detection signal S3 and calculating the logical sum of these signals. That is, when at least one of the three inputs is at the ``H'' level, the output of the OR circuit 7 outputs the arm short circuit generation signal 07 at the ``H'' level.

Next, referring back to FIG. 2B, the logic operation circuit will be explained.

This logic operation circuit 4 is connected to an arm short circuit (G of upper and lower arms).
TO refers to a short circuit in a DC circuit caused by, for example, Gll and 012 turning on at the same time. ), the ignition gate pulse of the GTO (e.g. G11) that is about to be ignited should be applied to the GTO (e.g. G12) on the opposite arm.
Logic circuit to supply after confirming the extinguishment of the arc, logic circuit to detect arm short circuit, logic circuit to give forced extinguishing command to all GTOs when a GTO failure occurs, logic circuit to supply a forced extinguishing command to all GTOs when a GTO overcurrent occurs. It consists of a logic circuit for giving a forced firing command to all GTOs, and a logic circuit for giving a forced firing command to all GTOs when an arm short circuit occurs.

First, with reference to FIG. 3A, the operation for preventing arm short circuit will be described. In addition, the signals A11,
12. C1l, 12. pH, 12) Qll, 12 correspond to those in FIG. 1, respectively.

Now, if GTO thyristor G12 becomes unable to turn off at time 1 (in other words, A12 in the figure
As shown in , when it should normally be off as shown by the dotted line (signal All, 12 is a negative voltage at the point where GTO is off), if it remains on,
The corresponding comparator output C12 is at a low level (in addition,
Signals C11 and C12 are at low level when GTO is on. ) remains the same. Therefore, GTO Zyristor G
Even if the firing command pH is issued to thyristor G11, the AND gate AND11 is not opened by the comparator output C12 from the high voltage side circuit 3B of the GTO thyristor G12, so this is blocked and the gate drive signal Qll for the thyristor Gll is also It remains at a low level, and arm short-circuit accidents are avoided. Note that this relationship is the same even when the firing thyristor Gll fails to turn off, and in this case, the firing command P12 is
It will be blocked by the comparator output C11 from the high voltage side circuit 3A applied to AND12.

Next, the arm short circuit detection operation will be described with reference to FIG. 3B. Note that the various signals in this case also correspond to those in FIG. 1, as in the case of FIG. 3A.

Now, assume that at time t8, when the thyristor Gll is firing as indicated by All in the figure, the voltage between the gate and cathode of the GTO thyristor G12 drops to nearly zero due to erroneous firing or failure of the thyristor G12. As a result, the comparator output C12 becomes low (L) level, but
At this time, since the comparator output C1l of the high voltage side circuit 3A is also at the 4-level as shown in the figure, these low level signals C
1l.

12 is applied to NOR in FIG. 2B, and a high level signal S1 is output from the output thereof, and an arm short circuit is detected.

Next, the forced arc extinguishing operation when a GTO failure occurs will be explained.

The output 05 of the GTO failure detection circuit 5 connected to the input TO5 of the logic operation circuit 40 changes to the ``L'' level when the GTO is destroyed due to turn-off failure or the like. This signal is ``AND21''.

22 is forcibly changed to L'' level.

Therefore, when the output 06 of the GTO overcurrent detection circuit 6 and the output 07 of the @rational sum circuit 7 are both at L" level, that is, when there is no overcurrent and no arm short circuit, the outputs of the OR gates 0Ri1 and 0R1z are forced. becomes L” level. As a result, a forced extinguishing signal is given to the GTO.

Next, forced ignition operation at the time of GTO overcurrent will be explained.

The output 06 of the GTO overcurrent detection circuit 6 connected to the input TO6 of the logic operation circuit 40 changes to the ``H'' level when an overcurrent occurs in the GTO. This signal is transmitted to the output Q of the logic operation circuit 4 through OR11 and 0RI2.
ll, Q12 are forcibly changed to the H" level. As a result, a forced ignition command is given to all m GTOs when a GTO overcurrent occurs.

Finally, the forced ignition operation when an arm short circuit occurs will be explained.

The output 07 of the OR circuit 7 connected to the input TO7 of the logic operation circuit 4 changes to the ``H'' level when an arm short circuit occurs in the inverter. This signal is passed through the OR gates 011 and 012 to the output Q1 of the logic operation circuit 4.
．． 1. Q12 is forcibly changed to "H" level. As a result, a forced firing command is given to all GTOs when a GTO arm short circuit occurs.

[Invention 0 effect] 5a. 1□4-~According to this invention, the O of the GTO is
N. Since the OFF state is determined and GTO failure is detected, all normal GTOs are forcibly extinguished immediately after the failure is detected, making it possible to prevent overcurrent from occurring through the load circuit. This has the effect of preventing the spread of an accident to a fuse provided in a DC intermediate circuit. In addition, when one of the two GTOs for each phase of the inverter becomes unable to turn off (extinguish), the other GTO is blocked without giving an ignition signal, thereby preventing arm short-circuit accidents. It can be prevented. Furthermore, despite this blocking function, when an arm short circuit occurs, all GTOs are forcibly fired to divert the short circuit current, further enhancing the inverter's body membrane function. It is something.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, 2All is a block diagram showing a specific example of the high voltage side circuit shown in FIG. 1, and FIG. 2B is a specific example of the logic operation circuit shown in FIG. 1. FIG. 2C is a configuration diagram showing a specific example of the failure detection circuit shown in FIG. 1, FIG. 2D is a configuration diagram showing a specific example of the overcurrent detection circuit shown in FIG. The figure is a configuration diagram showing a specific example of the OR circuit shown in Fig. 1, Fig. 3A is a time chart for explaining the operation to prevent an arm short circuit caused by the logic operation circuit, and Fig. 3B is the same. It is a time chart for explaining the detection operation at the time of arm short circuit. Code explanation 1...DC power supply, 2...Current detector,
3 (3A~3F)...High voltage side circuit, 4 (41~
43) Logic operation circuit for... 5... Failure detection circuit, 6... Overcurrent detection circuit, 7... Song m logic sum circuit,
8... Inverter control device, 31...
Gate drive circuit, 32... Voltage detector, 33.
...Comparison circuit, G], 1 to G32...G
TO thyristor, CF2, 5.6 (61-66)...
...Comparator, PC...Photocoupler, ANDl
l, 12, 21, 22, 5, 6...AND gate, 0RII, 12.7...OR gate, N.几・・・Noah Gate, NAND51, 52,
61. 62... Nantes Gate, EXOR...
Exclusive M logic sum gate, NOT...Not gate, sgs, 6...Reference voltage setter, SW5
, 6... Reset switch. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki---, -----J M2C Diagram 2θ

Claims (1)

[Claims] 1) Monitoring means for monitoring conduction or non-conduction of each gate turn-off (GTO) thyristor constituting a multiphase inverter, and detecting a failure of the GTO thyristor based on the monitoring result and an ignition/extinguishing command. When a failure of at least one GTO thyristor is detected by the failure detection means, all other normal GTO thyristors are forcibly extinguished to suppress the inverter output overcurrent. A protection device for the GTO thyristor inverter, which is characterized by preventing accidents. 2) In the protection device according to claim 1,
A protection device for a GTO thyristor inverter, wherein the monitoring means monitors whether the GTO thyristor is conductive or non-conductive using a voltage between its gate and cathode. 3) In the protection device according to claim 1,
A protection device for a GTO thyristor inverter, wherein the monitoring means monitors whether the GTO thyristor is conductive or non-conductive using a voltage between its anode and cathode. 4) In the protection device according to any one of claims 1 to 3, when one of the two GTO thyristors constituting each phase cannot be extinguished, the other GT thyristor
A protection device for a GTO thyristor inverter characterized by preventing an O thyristor from igniting to avoid an arm short-circuit accident. 5) In the protection device according to any one of claims 1 to 4, when an overcurrent is detected in at least one GTO thyristor during the forced arc extinguishing process, all components of the inverter A protection device for a GTO thyristor inverter, characterized by forcibly firing a GTO thyristor.