JPS61293018A - Gate circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements and to reduce the occupation area using a transfer gate composed of a single-conduction type MOSFET, an inverter circuit, and an opposite-conduction type MOSFET. CONSTITUTION:When an A1 rises from L to H while a B1 is at an H level (VCC), the output of an inverter 1 begins to fall according to input/output characteristics of the inverter 1 as a potential of the 2 rises because an N channel type MOSFETQ1 is on, and when the output drops down to a potential Vcc-VTP, a P channel type MOSFETQ5 begins to turn on, so that the potential of the 2 is raised through a Q5. Consequently, the output of the inverter 1 further drops and the Q5 turns on, thereby raising the potential at 2 abruptly. The potential of the 2 rises up to the VCC and the output of the inverter 1 falls to zero V through said positive feedback operation. At this time, the potential of the 2 is not an intermediate potential, but at the level VCC, so no stationary through current flows through the inverter 1. Then, when the input signal A1 falls from H to L, a potential of the 1 rises up to VCC-VTP in the reverse process similarly and then the Q5 turns off completely, so that the potential of the 2 becomes as high as the potential of the A1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a gate circuit composed of CMOS transistors.

[Prior art]

Conventionally, a CMO8-purchased transfer gate has been configured by connecting each of an N-channel type MO8FET and a P-channel type MOf9FET in parallel. FIG. 5 shows a conventional transfer gate circuit including a plurality of transfer gates. C1,02,C3
, Cn are input signals to the gate circuit, respectively, and DI, D
2. D3. Dn is a transfer control signal, 20,2
1, 22, 23 are CMOS inverters, Q2oI Q
1121 Quy Q10 is N-channel type MO8PE
T, Q2+, (hs, (hs, Q version is P channel type M
It is O8FET. Dl is 1 i 1 and D2+ D3.
When Dn is log, Q10 and (ht are both ONI, , Q
zz t Q23 s Qu sQ2g + Q26
r Q27 is OFF t,, output 10 has input signal C1
is output. Similarly, one of the other transfer control signals
Only one is 111 and the remaining transfer control signal group is 1
01, only the corresponding input signal is output to the output 10.

[Problems to be solved by the present invention]

When selecting one of n input signals, a conventional transfer gate circuit requires n inverters, n N-channel type IGFETs, and n P-channel type MO8Fs.
ET was required, and a total of 2n+n+n=4n elements were required. Therefore, there was a drawback that the area of the transfer gate circuit became large.

[Means to solve the problem]

The present invention provides an insulated gate field effect transistor of a second conductivity type complementary to the conductivity type at each output end of a plurality of input insulated gate field effect transistors of a first conductivity type connected in parallel or series-parallel. One end of the field effect transistor is connected to an input end of an inverter, and the gate of the second conductivity type insulated gate field effect transistor is controlled by the output of the inverter. As a result, the same operation as in the past can be achieved with a very small number of elements, and the occupied area can be significantly reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a CMO8) transfer gate according to an embodiment of the present invention. 1 is CMOS inverter, Q+, Q-, Q
s, Q4 is an N-channel type MO8FET%Q5 is a P-channel type IGFET%Al, A2. A3. An is an input signal to the gate circuit; Bl, B2, B3, and Bn are connected to the sources of Qx, Qz, Qg, and Qn, respectively; the drains of QIt, Q2, and Qn are commonly connected at node 2; is also connected to
Connected to the input of inverter 1. Output 0 taken out from inverter 1 is feedback connected to the gate of Qs,
The source of Qs is connected to Vcc.

B1 is at "H" (Vcc) level, B2. B3. When Bn is at 1L' (0■) level, Ql is on, Q, ,Q
s, Q are turned off, and input signal A1 attempts to transfer to output point 2 through Ql. When output point 2 is ``L level, inverter 1 is 1H level, Qs is off, and Bl is 1H1, input signal A1 is 1L level.
The waveforms of output point 2 and output O when the change from ' to 'H'K and from 1H1 to l L l will be explained using Fig. 2. In Fig. 2, (a) is the waveform of B1. , (b) is AI
(C) shows the waveform of 2, and (d) shows the output waveform of 1.

When B1 is at H level (Vcc), AI is i L w→”
When it becomes H”, the N-channel MO8FETQt is on, so the potential of 2 is VCC-(VTN+ΔVTN)
(V) Attempt to rise at a certain point. VTN is the threshold voltage of N-channel MOS FET, ΔVTN
is the increase in VTN due to the backgate effect. As the potential of inverter 2 rises, the output of inverter 1 begins to fall in accordance with the input/output characteristics of inverter 1 shown in FIG.
When the potential drops to VTP, the P-channel type MO8FE
TQ5 starts to turn on and increases the potential of 2 through sCh. As a result, the output of inverter 1 further decreases and Qs
turns on more and more, raising the potential of 2 rapidly.

Due to the positive feedback operation described above, the potential of inverter 2 rises to the Vcc level, and the output of inverter l becomes 0.

At this time, the potential of inverter 2 is at an intermediate potential (Vcc level), so no steady through current flows through inverter 1.

Next, when the input signal A1 becomes @H"→l L l level, a current flows from Vcc to A1 through sQstQt.The output impedance to the ground side of A1 and Q
The threshold voltage of the MO8FETQ is the sum of the impedances of s and the impedance of Qs. As Al falls, the potential of 2 begins to fall below Vcc, and when the potential of 2 reaches Vcc - ■rp, the output of inverter 1 rises slightly, and the ON current of s Qs slightly decreases.
The impedance of Qs becomes slightly larger, and the potential of 2 further falls. When the potential of inverter 2 decreases, inverter 1
The output of % Qs further decreases, and the on-current of Qs further decreases.
The impedance of Qs further increases, a positive return delay occurs, the potential of 2 falls more and more, the output of 1 rises more and more, and when the potential of 1 rises to the voltage Vcc - VTP, Qs is completely turned off, and the potential of 2 becomes more and more. The potential is the same as that of Al. Q
l, Q2, Qs, Q4 are P channel type M
08FET with Qs of N-channel type MO8FET operates in the same manner.

To summarize the above operation, although the transfer gate is composed of MOSFETs of only a single conductivity type, the transfer gate is Gate output is not at intermediate potential,
An output that is in phase with the input signal is output, and an output that is in phase opposite to the input signal is output at the output of the inverter.

Also, as in another embodiment shown in FIG. 4, QsvQ7.
Even if Qs are connected in series, Fl, F2 . F3 is “H” at the same time
”When the level (Vc) becomes low, Qs, QI, Qs turn on,
When El has the waveform shown in FIG. 2(b), 3 and 40
The waveforms are as shown in Figure 2 (C) and fd), respectively.
The same operation as in the embodiment of FIG. 1 is performed. in this case,
Output impedance to the ground side of A1 and Qs vQ,,
The sum of the impedances of Qs is a MOSF of the opposite conductivity type to the transfer gate depending on the impedance of Qo.
ET may be added.

〔Effect of the invention〕

According to the present invention, it can be constructed with a transfer gate composed of a single conductivity type MO8FB'l', one inverter, and one MOSFET of the opposite conductivity type, so that the conventional one shown in FIG. 5 and the present invention shown in FIG. Comparing the number of MOSFETs in the embodiment, the present invention has a control signal inverter of 20.
The output lines of 21, 22, and 23 are respectively Q21 + Q2
3 + Q25 t Since it is necessary for Q26, the area occupied by such an output line is required in the conventional case, whereas in the present invention there is no such area, so the area is
This decreases more than the decrease in the number of T. As described above, the CMOS gate circuit of the present invention has the great advantage of occupying a much smaller area than the conventional CMOS gate circuit, and can provide a low-cost CMO8LSI.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an operating waveform diagram of an embodiment of the invention, Fig. 3 is an input/output characteristic diagram of an inverter, and Fig. 4 is another embodiment of the invention. FIG. 5 is a conventional circuit diagram. QIT Q2 + Q3 + Q4 + Q6! Q
7+Qa+ Q9+Q10 y Q20 + Q22
tQ24 r Q2I,...N-channel type M
O8FET%Qs t Qn. Q211 Qzs T Q25 t Qrr・・・・−
・P channel type MO8FET. 1 , 4 , 20 , 21 , 22 , 23 --- Inverter, Vcc --- High potential side power supply, 2, 3,
10...--Transfer gate output. 19 = Hana II! I ■ □Bone Dodai Z Zuirih@Otsuka 3 Sen$ 4 Jun

Claims (1)

[Claims] An insulated gate field effect transistor of a second conductivity type complementary to the conductivity type is connected to the output terminal of a plurality of insulated gate field effect transistors of a first conductivity type for input connected in parallel or in series and parallel. A gate circuit, wherein one end and an input end of an inverter are connected, and the gate of the second conductivity type insulated gate field effect transistor is controlled by the output of the inverter.