JPS6129273A - Recorder - Google Patents

Recorder

Info

Publication number
JPS6129273A
JPS6129273A JP15081084A JP15081084A JPS6129273A JP S6129273 A JPS6129273 A JP S6129273A JP 15081084 A JP15081084 A JP 15081084A JP 15081084 A JP15081084 A JP 15081084A JP S6129273 A JPS6129273 A JP S6129273A
Authority
JP
Japan
Prior art keywords
recording
line
signal
image signal
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15081084A
Other languages
Japanese (ja)
Inventor
Hiroaki Saeki
佐伯 宏壮
Nobuo Sugino
杉野 信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15081084A priority Critical patent/JPS6129273A/en
Publication of JPS6129273A publication Critical patent/JPS6129273A/en
Pending legal-status Critical Current

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Landscapes

  • Facsimile Image Signal Circuits (AREA)
  • Electronic Switches (AREA)
  • Fax Reproducing Arrangements (AREA)

Abstract

PURPOSE:To prevent the occurrence of the recording irregularity in terms of a facsimile of a thermal head system by extending a conductive period to a recording head at the time of recording a specific dot. CONSTITUTION:Data by block is read out when line memories 1 and 2 are in the readable state and when a line memory 3 is in the writable state. Said memories are switched by a select signal from a select circuit 4, and two-line grouping signals (e) are outputted. A basic signal (f) and a comparison signal (g) are stored in block memories 5 and 6, and parallel signals are outputted from both memories 5 and 6. In terms of the 1st gate circuit 7, a dot corresponding to a previous line signal is compared with that corresponding to a recording picture signal. Then a specific bit of data zero and that of data 1 are extracted in a previous line and recording line, respectively, and outputted to a pulse generator circuit 8, where a pulse (i) wider than normal recording signal width is generated. Finally the recording signal is outputted from the 2nd gate circuit 9.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は記録装置の中でも、特にサーマルヘッドを利用
し、濃度コントロールをして階調記録を行なう記録装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to printing apparatuses, and particularly to a printing apparatus that uses a thermal head to control density and perform gradation printing.

従来例の構成とその問題点 従来、サーマルヘッド式のファクシミリにおいては、副
走査方向に対し1ドツトを記録する場合も、連続ドツト
を記録する場合も1ドツトに対するエネルギー量は同一
とされており、1ドツトのみを記録した時には濃度が上
がらず薄い記録となり記録ムラを生じ大変見にくく、場
合によっては全く記録されないと云った場合などがある
Conventional configuration and its problems Conventionally, in thermal head facsimile machines, the amount of energy per dot is the same whether recording one dot or continuous dots in the sub-scanning direction. When only one dot is recorded, the density does not increase and the recording becomes thin, uneven recording occurs, and it is very difficult to see, and in some cases, it may not be recorded at all.

発明の目的 本発明は1ドツト記録に生ずる記録ムラを無くして均一
な記録を実行できる記録装置を提供することを目的とす
る。
OBJECTS OF THE INVENTION An object of the present invention is to provide a recording apparatus that can eliminate recording unevenness that occurs in one-dot recording and perform uniform recording.

発明の構成 本発明の記録装置は、1ライン分の画像信号を蓄積する
第1、第2、第3のラインメモリと、この3個のライン
メモリのうち2つのラインメモリを選択してそれぞれの
メモリに蓄積されたライン単位の画信号をブロック分割
しこのブロック分割した画信号を交互にセレクトし出力
するセレクト回路と、前記交互にブロック分割した画信
号を蓄積する第1、第2のブロックメモリとを設けて第
1のブロックメモリに蓄積された基本画信号と第2のブ
ロックメモリに蓄積された比較画信号のうちの基本画信
号に応じて記録ヘッドに通電して記録を実行するよう構
成すると共に、前記基本画信号と比較画信号の同一位置
を比較して比較画信号ラインで記録データが無くて基本
画信号ラインで記録データがある特定ドツトを抽出する
ゲート回路と、このゲート回路出力信号により前記特定
ドツト記録時の記録ヘッドへの通電時間をその他のドツ
ト記録一時、よりも延長する補正手段を設けたことを特
徴とする。
Structure of the Invention The recording device of the present invention includes first, second, and third line memories that store image signals for one line, and selects two line memories from among these three line memories to record each line. a selection circuit that divides a line-by-line image signal stored in a memory into blocks and alternately selects and outputs the divided image signals; and first and second block memories that store the image signals that are alternately divided into blocks. and is configured to perform printing by energizing the recording head in accordance with the basic image signal of the basic image signal stored in the first block memory and the comparison image signal stored in the second block memory. At the same time, a gate circuit compares the same position of the basic image signal and the comparison image signal and extracts a specific dot where there is no recording data on the comparison image signal line and there is recording data on the basic image signal line, and an output of this gate circuit. The present invention is characterized in that a correction means is provided for extending the time during which the recording head is energized during recording of the specific dot by a signal, compared to when recording other dots.

実施例の説明 以下、本発明の一実施例を図面に基づいて説明する。第
1図は本発明の構成を示す。(1)〜(3)は入力画信
号(a)を記憶する1ラインのメモリで、ラインメモリ
(1)→(2)→(3)の順でそれぞれ画像信号の記憶
、読み出し、読み出しを3ライン単位で繰り返してそれ
ぞれの読出し出力画像信号(b)。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the present invention. (1) to (3) are 1-line memories that store the input image signal (a), and store, read, and read out the image signals in the order of line memories (1), (2), and (3), respectively. Each readout output image signal (b) is repeated line by line.

(C)、(d)をセレクト回路(45に出力する。セレ
クト回路(4)はあらかじめ設定されているブロック単
位毎にNラインのMブロック信号、(N+1)ラインの
Mブロック信号となる様、入力される2個のラインメモ
リの信号を選択し、ブロック単位に分割し交互に切替え
、2ライン一括信号(e)を出力する。(5) (6)
はブロック単位メモリでブロックメそり(5)は前記(
N+1)ラインのMブロック信号を、メモリ(6)はN
ラインのMブロックの信号を記憶してそれぞれ、記録す
べき基本画信号(f)、比較画信号(g)として出力す
る。第1のゲート回    1路(7)は記録すべきブ
ロック単位の基本画信号(f)と前ラインの同一ブロッ
ク位置の出力である比較画信号(g)との副走査方向に
対し相対するドツトの比較を行い基本画信号にのみ存在
するドツトを抽出してパルス発生回路(8)に出力する
。パルス発生回路(8)は入力信号に対しあらかじめ設
定されている記録1ドツトより少し広い幅のパルスを発
生し、ゲート回路(9)によりメモリ(5)の基本画信
号と合成し、副走査方向に対し、最初に出現するドツト
の記録信号幅を広くシ、記録装置を均一化する。
(C) and (d) are outputted to the select circuit (45).The select circuit (4) outputs the M block signals of N lines and the M block signals of (N+1) lines for each block set in advance. Selects the input two line memory signals, divides them into blocks, switches them alternately, and outputs a two-line collective signal (e). (5) (6)
is a block unit memory and the block memory (5) is the above (
The memory (6) receives the M block signal of the N+1) line.
The signals of M blocks of lines are stored and output as a basic image signal (f) and a comparison image signal (g) to be recorded, respectively. The first gate circuit 1 (7) detects dots that are opposite to each other in the sub-scanning direction between the basic image signal (f) in block units to be recorded and the comparative image signal (g) which is the output of the same block position in the previous line. The dots existing only in the basic image signal are extracted and output to the pulse generating circuit (8). The pulse generation circuit (8) generates a pulse with a width slightly wider than one recording dot set in advance in response to the input signal, and the gate circuit (9) synthesizes it with the basic image signal in the memory (5), and generates a pulse in the sub-scanning direction. On the other hand, the recording signal width of the first appearing dot is widened to make the recording device uniform.

次に第1図の動作を第2図、第3図により詳細に説明す
る。なお、ここでは1ブロック単位のデータ長を4ドツ
トとしラインメモリ(1)(2)it続出し、ラインメ
モリ(3)は書込み状態にある場合を例に挙げて説明す
る。
Next, the operation shown in FIG. 1 will be explained in detail with reference to FIGS. 2 and 3. Here, an example will be explained in which the data length of one block is 4 dots, line memories (1), (2), and so on are successively written, and line memory (3) is in the writing state.

第2図の(k)はラインメモリ(3)に対する書込みク
ロックを表わす。ラインメモリ(2)のデータが記録さ
れるタイミングにおいて(β)(0)はそれぞれライン
メモリ(1)(2)の読出しクロックで、4ビット単位
間欠で読み出され、(b)(Q)のブロック単位のデー
タがそれぞれ読み出され、セレクト回路(4)によりセ
レクト信号(p)で切替えられて2ライン一括信号(e
)が出力される。図中のnはライン位置でmはブロック
位置を示すもので信号(b)の1nと(c)の2nは副
走査方向に1ライン異なった同一ブロック位置のデータ
である。次ラインにおいてはラインメモリ(2) (3
)において同一の動作が行われる62ライン一括信号(
e)の内容を第3図の(e −1)の状態とした時、ブ
ロックメモリ(5) (6)には基本画信号(f)、比
較画信号(g)が記憶され、それぞれ(f −1)〜(
f−4)、(g−1)〜(g−4)のパラレル信号が出
力されている。第1のゲート回路(7)において前ライ
ン信号〔比較画信号〕と記録画信号〔基本画信号〕の相
対するドツト((f−1)と(g−1)、(f −2)
と(g −2)・・・りを比較して前ラインにおいてデ
ータ″0”で記録ラインにおいてデータIt I I+
の特定ドツトを抽出し、パルス発生回路(8)に出力す
る。ここではドツト(n−1)が特定ドツトであって、
パルス発生回路(8)においては、ドツト(n−1)に
対し通常の記録信号幅よりT″′だけ広いパルス(i 
−1)を発生し、第2のゲート回路(9)により従来の
記録信号(f −1)〜(f−4)とパルス発生回路(
8)出力の(i−1)〜(i−4)と合成し、そのブロ
ックデータ2nに対する記録信号(j−1)〜(j −
4)を出力する。
(k) in FIG. 2 represents a write clock for the line memory (3). At the timing when the data of line memory (2) is recorded, (β) and (0) are read clocks of line memory (1) and (2), respectively, and are read out in 4-bit units intermittently, and (b) and (Q) Each block of data is read out, and is switched by a select signal (p) by a select circuit (4) to receive a 2-line batch signal (e
) is output. In the figure, n indicates a line position and m indicates a block position, and signals 1n in (b) and 2n in (c) are data at the same block position different by one line in the sub-scanning direction. In the next line, line memory (2) (3
) 62-line batch signal (
When the contents of e) are set to the state of (e-1) in FIG. -1)~(
f-4) and (g-1) to (g-4) parallel signals are output. In the first gate circuit (7), opposing dots ((f-1), (g-1), (f-2) of the previous line signal [comparison picture signal] and the recording picture signal [basic picture signal] are detected.
Comparing (g −2)..., data is "0" in the previous line and data It I I + in the recording line.
A specific dot is extracted and outputted to the pulse generation circuit (8). Here, dot (n-1) is a specific dot,
The pulse generating circuit (8) generates a pulse (i) wider than the normal recording signal width by T''
-1), and the second gate circuit (9) generates the conventional recording signals (f-1) to (f-4) and the pulse generating circuit (
8) Combine outputs (i-1) to (i-4) and record signals (j-1) to (j −
4) Output.

発明の詳細 な説明のように本発明の記録装置は基本画信号と比較画
信号のうちの基本画信号に応じて記録ヘッドに通電して
記録を実行するよう構成すると共に、前記基本画信号と
比較画信号の同一位置を比較して比較画信号ラインで記
録データが無くて基本画信号ラインで記録データがある
特定ドツトを抽出するゲート回路と、このゲート回路出
力信号により前記特定ドツト記録時の記録ヘッドへの通
電時間をその他のドツト記録時よりも延長する補正手段
を設けたため、副走査方向に対し1ドツトを記録する場
合また連続ドツトの先端ドツトにおいて、記録エネルギ
ーを増大させ記録濃度を上げることが可能となり、従来
のような記録ムラを生じることなく、濃度の均一な記録
を実現できるものである。
As described in the detailed description of the invention, the recording apparatus of the present invention is configured to execute recording by energizing the recording head according to the basic image signal of the basic image signal and the comparison image signal, and also to A gate circuit that compares the same position of the comparison image signal and extracts a specific dot for which there is no recording data on the comparison image signal line and that has recording data on the basic image signal line; Since a correction means is provided to extend the power supply time to the recording head compared to when recording other dots, the recording energy is increased to increase the recording density when recording one dot in the sub-scanning direction or at the leading end of continuous dots. This makes it possible to realize recording with uniform density without causing recording unevenness as in the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の記録装置の一実施例の要部構成図、第
2図は第1図における2ライン一括信号の説明図、第3
図は具体的な信号例による特定ドツト記録状態の説明図
である。 (1) (2) (3)・・・ラインメモリ、(4)・
・・セレクト回路、(5) (6)・・・ブロックメモ
リ 〔第1、第2のブロックメモリ〕、(7)・・・第
1のゲート回路、(8)・・・パルス発生回路、(9)
・・・第2のゲート回路、(e)・・・2ライン一括信
号、(f)・・・基本画信号、(g)・・・比較画信号
。 (j)・・・記録信号 代理人   森  本  義  弘 大
FIG. 1 is a block diagram of essential parts of an embodiment of the recording apparatus of the present invention, FIG. 2 is an explanatory diagram of the 2-line batch signal in FIG.
The figure is an explanatory diagram of a specific dot recording state using a specific example of a signal. (1) (2) (3)... line memory, (4)...
...Select circuit, (5) (6)...Block memory [first and second block memories], (7)...First gate circuit, (8)...Pulse generation circuit, ( 9)
. . . second gate circuit, (e) . . . 2-line batch signal, (f) . . . basic image signal, (g) . . . comparative image signal. (j)... Recording signal agent Yoshihiro Morimoto

Claims (1)

【特許請求の範囲】[Claims] 1、1ライン分の画像信号を蓄積する第1、第2、第3
のラインメモリと、この3個のラインメモリのうち2つ
のラインメモリを選択してそれぞれのメモリに蓄積され
たライン単位の画信号をブロック分割しこのブロック分
割した画信号を交互にセレクトし出力するセレクト回路
と、前記交互にブロック分割した画信号を蓄積する第1
、第2のブロックメモリとを設けて第1のブロックメモ
リに蓄積された基本画信号と第2のブロックメモリに蓄
積された比較画信号のうちの基本画信号に応じて記録ヘ
ッドに通電して記録を実行するよう構成すると共に、前
記基本画信号と比較画信号の同一位置を比較して比較画
信号ラインで記録データが無くて基本画信号ラインで記
録データがある特定ドットを抽出するゲート回路と、こ
のゲート回路出力信号により前記特定ドット記録時の記
録ヘッドへの通電時間をその他のドット記録時よりも延
長する補正手段を設けた記録装置。
1st, 2nd, and 3rd to accumulate image signals for one line.
The line memory and two of these three line memories are selected, the line-by-line image signal stored in each memory is divided into blocks, and the image signals divided into blocks are alternately selected and output. a select circuit, and a first circuit for accumulating the image signals divided into blocks alternately.
, a second block memory is provided, and the recording head is energized according to the basic image signal of the basic image signal stored in the first block memory and the comparison image signal stored in the second block memory. A gate circuit configured to execute recording and for comparing the same position of the basic image signal and the comparison image signal to extract a specific dot for which there is no recording data on the comparison image signal line and there is recording data on the basic image signal line. and a recording apparatus provided with a correction means for extending the time during which the recording head is energized when recording the specific dot, using the gate circuit output signal, as compared to when recording other dots.
JP15081084A 1984-07-19 1984-07-19 Recorder Pending JPS6129273A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15081084A JPS6129273A (en) 1984-07-19 1984-07-19 Recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15081084A JPS6129273A (en) 1984-07-19 1984-07-19 Recorder

Publications (1)

Publication Number Publication Date
JPS6129273A true JPS6129273A (en) 1986-02-10

Family

ID=15504912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15081084A Pending JPS6129273A (en) 1984-07-19 1984-07-19 Recorder

Country Status (1)

Country Link
JP (1) JPS6129273A (en)

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