JPS61292268A - Extracting method for digital synchronizing pattern - Google Patents

Extracting method for digital synchronizing pattern

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Publication number
JPS61292268A
JPS61292268A JP13327785A JP13327785A JPS61292268A JP S61292268 A JPS61292268 A JP S61292268A JP 13327785 A JP13327785 A JP 13327785A JP 13327785 A JP13327785 A JP 13327785A JP S61292268 A JPS61292268 A JP S61292268A
Authority
JP
Japan
Prior art keywords
address
circuit
synchronization pattern
signal
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13327785A
Other languages
Japanese (ja)
Other versions
JPH0668883B2 (en
Inventor
Yoshihiro Murakami
芳弘 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13327785A priority Critical patent/JPH0668883B2/en
Publication of JPS61292268A publication Critical patent/JPS61292268A/en
Publication of JPH0668883B2 publication Critical patent/JPH0668883B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To execute a good extraction with a simple constitution by estimating an address from the rotating position of a rotating head and extracting a synchronizing pattern using an estimated value and a reproducing address. CONSTITUTION:A signal reproduced from a tape 1 by a rotation head 2 is supplied to a serial/parallel conversion circuit 4 with being demodulated/ waveform shaped at a reproducing circuit 3, and a data and the address are outputted to output terminals 5 and 6. With supplying a reference signal from a terminal 8 to a survo circuit 9, the rotation of a rotating head 2 is controlled and with supplying the reference signal to an address estimating circuit 10, the address corresponding to the rotating position of the rotating head is formed. The estimated value from the address estimating circuit 10 and the reproducing address from the conversion circuit 4 are supplied to a comparison circuit 11 and when they are allowable coincide a coincidence output is supplied to an AND circuit 12 and a detecting signal from a synchronizing pattern detecting circuit 7 is outputted to a synchronizing signal output terminal 13 through the AND circuit 12.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばデジタルビデオチーブレ占−ダに使用
して好適なデジタル同期パターン抽出方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital synchronization pattern extraction method suitable for use in, for example, a digital video chip reader.

〔発明の概要〕[Summary of the invention]

本発明はデジタル同期パターン抽出方法に関し、回転ヘ
ッドの回転位置からアドレスを予測し、この予測値と再
生アドレスを用いて同期ツクターンを抽出することによ
シ、簡単な構成で良好な抽出が行えるようにするもので
ある。
The present invention relates to a method for extracting digital synchronization patterns, which enables good extraction with a simple configuration by predicting an address from the rotational position of a rotary head and extracting a synchronization pattern using the predicted value and the playback address. It is something to do.

〔従来の技術〕[Conventional technology]

例えばデジタルビデオテープレコーダにおいては、デジ
タル変換された映像信号を所定量ずつ分割し、この所定
量ごとにデジタルの同期・9ターンとアドレスを付加し
て記録を行う。
For example, in a digital video tape recorder, a digitally converted video signal is divided into predetermined amounts, and each predetermined amount is recorded by adding digital synchronization, nine turns, and an address.

すなわち、例えば第2図Aに示すように走査線数256
本、水平解像度768バイトの1フイールドの映像信号
を全体で約1.2倍の冗長ピットを設けて走査線数28
0本、水平解像度832バイトに変換する。この変換さ
れたデータを同図Bに示すように208バイトずつに分
割し、所定のシャフリング等を行った後、記録順に従っ
て各分割ごとに2バイトの同期パターン及び2バイトの
アドレスを付加する。この信号を同図Cに示すように1
フイールドが8本のトラックとなるように回転ヘッドに
て記録を行う。
That is, for example, as shown in FIG. 2A, the number of scanning lines is 256.
In this book, one field of video signal with a horizontal resolution of 768 bytes is provided with approximately 1.2 times as many redundant pits as a whole, and the number of scanning lines is 28.
0 lines, converted to a horizontal resolution of 832 bytes. This converted data is divided into 208 bytes each as shown in Figure B, and after performing predetermined shuffling, etc., a 2-byte synchronization pattern and a 2-byte address are added to each division according to the recording order. . This signal is 1 as shown in C in the same figure.
Recording is performed using a rotating head so that the field has eight tracks.

・従ってこの場合に、各トラックにはそれぞれ140の
上述の分割と同期、p4ターン及びアドレスが記録され
る。そこで上述のアドレスにおいては。
- Therefore, in this case, 140 of the above-mentioned divisions, synchronizations, p4 turns, and addresses are recorded in each track. So at the above address.

2バイト婁16ビツトの内の5ピツトをトラックアドレ
スとし、残シの11ビツトでトラックの一端を起点とし
て順次歩進するトラック内アドレスを形成している。
Five pits of 2 bytes and 16 bits are used as a track address, and the remaining 11 bits form an intra-track address that sequentially steps from one end of the track as a starting point.

ところで上述の装置において、信号の再生を行う場合に
は同期パターンの検出が極めて重要である。すなわち上
述の装置で、データの分割は同期A?ターンによって示
されておシ、データ中の近似の)4ターンをノイズ等の
影響で同期パターンと誤検出すると、それによって分割
の検出が誤動作し、シャフリングを元に戻す等の操作が
大幅に誤動作するおそれがある。なお正規の同期パター
ンの欠落については、内挿等によって容易に補償可能で
ある。
By the way, in the above-mentioned apparatus, detection of a synchronization pattern is extremely important when reproducing a signal. In other words, in the above device, is data division synchronous A? If 4 turns (approximately indicated by a turn in the data) are mistakenly detected as a synchronous pattern due to the influence of noise, etc., the division detection will malfunction, and operations such as undoing shuffling will be significantly delayed. There is a risk of malfunction. Note that the lack of a regular synchronization pattern can be easily compensated for by interpolation or the like.

そこで従来よシ同期パターンのビット長を長くして、誤
検出を生じにくくすることが考えられている。′しかし
ながら同期パターンのビット長を長くすることはその分
データのビット数が減ることになシ、特に高密度の記録
を行う場合には不都合である。
Therefore, conventional methods have been considered to increase the bit length of the synchronization pattern to make false detection less likely to occur. 'However, increasing the bit length of the synchronization pattern does not necessarily reduce the number of data bits, which is particularly inconvenient when performing high-density recording.

これに対して、同期ノ臂ターンの周期性、あるいは前後
の分割のアドレスから算出される相対アドレスを再生ア
ドレスと比較して一致のときに同期ノ譬ターンを検出す
るなどの方法も考えられるが、いずれの場合も周期を求
めたシ、相対アドレスを算出するための構成が必要とな
シ、特に前後のアドレスを検出する場合には、後のアド
レスを検出するまでの1〜2分割分のデータを保存する
メモリ等が必要と表る。またいわゆるサーチ等の高速再
生を行っている場合には、周期が変化した夛、前後の分
割のアドレスが得られな〜・可能性もあった。
On the other hand, it is possible to consider methods such as comparing the relative address calculated from the periodicity of the synchronous arm turn or the addresses of the previous and subsequent divisions with the playback address and detecting a synchronous rambling turn when they match. In either case, a configuration is required to calculate the period and the relative address.Especially when detecting the previous and subsequent addresses, one to two divisions until the subsequent address is detected. It appears that memory etc. to save data is required. Furthermore, when high-speed playback such as so-called search is performed, there is a possibility that the addresses of the previous and subsequent divisions cannot be obtained even though the period has changed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のデジタル同期パターン抽出方法では、データのピ
ット数が減少したシ、回路構成の増大、高速再生には適
用できないなどの問題点があった。
Conventional digital synchronization pattern extraction methods have problems such as a reduced number of data pits, an increased circuit configuration, and inability to be applied to high-speed playback.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、同期パターン及びアドレスの付加されたデジ
タル信号を、上記同期/4ターン及びアドレスがトラッ
ク上で所定の位置になるように回転ヘッドにて記録した
テープを再生するに当り、再生を行う上記回転ヘッドの
回転位置を検出し、この検出された回転位置よりその位
置に記録されている上記アドレスを予測し、この予測さ
れた値と再生された上記アドレスとを比較し、この比較
が一致したときに上記同期パターンの検出出力を取出す
ようにしたデジタル同期パターン抽出方法である。
The present invention reproduces a digital signal to which a synchronization pattern and an address are added when reproducing a tape recorded with a rotary head so that the synchronization/4 turn and address are at predetermined positions on the track. The rotational position of the rotary head is detected, the address recorded at that position is predicted from the detected rotational position, the predicted value is compared with the reproduced address, and this comparison results in a match. This digital synchronization pattern extraction method extracts the detection output of the synchronization pattern when the synchronization pattern is detected.

〔作用〕[Effect]

この方法によれば、回転ヘッドの回転位置払らアドレス
を予測しているので、極めて容易にアドレスを予測する
ことができ、これを用いて良好な同期・ぐターンの抽出
を行9ことができる。
According to this method, since the address is predicted based on the rotational position of the rotating head, the address can be predicted extremely easily, and this can be used to extract good synchronization and turns. .

〔実施例〕〔Example〕

第1図において、(1)はデジタル信号の記録され九テ
ーグであって、このチーf(1)から回転ヘッド(2)
にて信号が再生される。この信号が再生回路(3)で復
調・波形整形等されてシリアル/−4′ラレル(sp)
変換回路(4)に供給される。そしてこの変換回路(4
)からデータ及びアドレスが出力端子(5) (6)に
出力される。
In FIG. 1, (1) is a digital signal recorded on the nine tags, and from this chip f(1) to a rotary head (2).
The signal is played back. This signal is demodulated and waveform shaped in the reproducing circuit (3) and converted to serial/-4' parallel (sp).
It is supplied to the conversion circuit (4). And this conversion circuit (4
), data and addresses are output to output terminals (5) and (6).

また変換回路(4)の出力の一部が同期パターン検出回
路(7)に供給される。
A part of the output of the conversion circuit (4) is also supplied to the synchronization pattern detection circuit (7).

さらに端子(8)には動作の基準信号が供給され、この
基準信号がサーボ回路(9)に供給されて回転ヘッド(
2)の回転が制御されている。この基準信号がアドレス
予測回路αQに供給され、回転ヘッド(2)の回転位置
に応じたアドレスが形成される。
Further, a reference signal for operation is supplied to the terminal (8), and this reference signal is supplied to the servo circuit (9) and the rotating head (
The rotation of 2) is controlled. This reference signal is supplied to the address prediction circuit αQ, and an address corresponding to the rotational position of the rotary head (2) is formed.

すなわち上述の装置で、各トラックにはそれぞれ140
の分割が記録され、各分割の長さは等しいので、それぞ
れのアドレスはテープを幅方向に140等分した各位置
にテープの長手方向に整列して記録されている。さらに
アドレス中の11ビットは各トラックの一端を起点とし
て順次歩進する値となっておシ、従って各等分位置の長
手方向には。
That is, in the device described above, each track has 140
Since the length of each division is equal, the respective addresses are recorded in alignment in the longitudinal direction of the tape at each position where the tape is divided into 140 equal parts in the width direction. Furthermore, the 11 bits in the address are values that are sequentially stepped from one end of each track as a starting point, so that each equally divided position in the longitudinal direction.

同じ11ピツトのアドレスが記録されている。The same 11 pit addresses are recorded.

一方回転ヘッド(2)の回転位置はテープ(1)の幅方
向の対接位置に対応しておシ、これによって回転ヘッド
(2)の回転位置よシ、その対接位置に記録されている
アドレスを予測することができる。
On the other hand, the rotational position of the rotary head (2) corresponds to the widthwise position of the tape (1), so that the rotational position of the rotary head (2) and the position of the tape (1) are recorded. Addresses can be predicted.

そζでアドレス予測回路αQからの予測値と変換回路(
4)からの再生アドレスとが比較回路α優に供給され、
これらが一致したとき一致出力がアンド回路(2)に供
給される。そして同期パターン検出回路(7)からの検
出信号がアンド回路(2)を通じて同期信号の出力端子
(6)に出力される。
At that ζ, the predicted value from the address prediction circuit αQ and the conversion circuit (
The playback address from 4) is supplied to the comparator circuit α,
When these match, a match output is supplied to the AND circuit (2). The detection signal from the synchronization pattern detection circuit (7) is outputted to the synchronization signal output terminal (6) through the AND circuit (2).

こうして同期パターンの抽出が行われるわけであるが、
上述の方法によればアドレスを比較し。
This is how synchronization patterns are extracted,
Compare the addresses according to the method described above.

このアト9レスが一致したときのみ同期信号を出力する
ようにしたので、同期ツタターンが実質的にアドレスの
11ビット分長くされたことになシ、誤検出のおそれを
大幅に減少させるととができる。
Since the synchronization signal is output only when the addresses 9 and 9 match, the synchronization turn is effectively lengthened by 11 bits of the address, which greatly reduces the possibility of false detection. can.

またアドレスの予測を回転ヘッド(2)の回転位置から
行うようにしたので、予測を極めて簡単な構成かつ容易
に行うことができる。さらに高速再生時等にも支障なく
予測を行うことができる。
Further, since the address is predicted based on the rotational position of the rotary head (2), the prediction can be easily performed with an extremely simple configuration. Furthermore, prediction can be made without any problem even during high-speed reproduction.

なおこの方法はビデオチーブレコーダに限ラス、他のデ
ジタル機器に応用できる。
Note that this method is limited to video recorders, but can be applied to other digital devices.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、回転ヘッドの回転位置からアドレスを
予測しているので極めて容易にアドレスを形成すること
ができ、これを用いて良好な同期ノ臂ターンの抽出を行
うことができるようになった。
According to the present invention, since the address is predicted from the rotational position of the rotary head, the address can be formed extremely easily, and this can be used to extract a good synchronous arm turn. Ta.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を実施する装置の一例の構成図、第2図
はデジタルビデオチーブレコーダの説明のための図であ
る。 (1)はテープ、(2)は回転ヘッド、(3)は再生回
路、(4)はシリアル/・9ラレル変換回路、(5) 
(6)は出力端子、(7)は同期パターン検出回路、(
8)は基準信号の入力端子、(9)はサーが回路、αQ
はアドレス予測回路、αりは比較回路、(6)はアンド
回路、(2)は同期信号出力端子である。
FIG. 1 is a block diagram of an example of a device implementing the present invention, and FIG. 2 is a diagram for explaining a digital video recorder. (1) is tape, (2) is rotating head, (3) is playback circuit, (4) is serial/9 parallel conversion circuit, (5)
(6) is an output terminal, (7) is a synchronization pattern detection circuit, (
8) is the reference signal input terminal, (9) is the circuit, αQ
is an address prediction circuit, α is a comparison circuit, (6) is an AND circuit, and (2) is a synchronization signal output terminal.

Claims (1)

【特許請求の範囲】 同期パターン及びアドレスの付加されたデジタル信号を
、上記同期パターン及びアドレスがトラック上で所定の
位置になるように回転ヘッドにて記録したテープを再生
するに当り、 再生を行う上記回転ヘッドの回転位置を検出し、この検
出された回転位置よりその位置に記録されている上記ア
ドレスを予測し、 この予測された値と再生された上記アドレスとを比較し
、 この比較が一致したときに上記同期パターンの検出出力
を取出すようにしたデジタル同期パターン抽出方法。
[Claims] A digital signal to which a synchronization pattern and an address have been added is reproduced when playing back a tape recorded with a rotary head so that the synchronization pattern and address are at predetermined positions on the track. Detect the rotational position of the rotary head, predict the address recorded at that position from the detected rotational position, compare this predicted value with the reproduced address, and if this comparison matches. A digital synchronization pattern extraction method that extracts the detection output of the synchronization pattern when the above synchronization pattern is detected.
JP13327785A 1985-06-19 1985-06-19 Digital synchronization pattern extraction method Expired - Lifetime JPH0668883B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13327785A JPH0668883B2 (en) 1985-06-19 1985-06-19 Digital synchronization pattern extraction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13327785A JPH0668883B2 (en) 1985-06-19 1985-06-19 Digital synchronization pattern extraction method

Publications (2)

Publication Number Publication Date
JPS61292268A true JPS61292268A (en) 1986-12-23
JPH0668883B2 JPH0668883B2 (en) 1994-08-31

Family

ID=15100873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13327785A Expired - Lifetime JPH0668883B2 (en) 1985-06-19 1985-06-19 Digital synchronization pattern extraction method

Country Status (1)

Country Link
JP (1) JPH0668883B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021897A (en) * 1987-06-12 1991-06-04 Matsushita Electric Industrial Co., Ltd. Memory system for recording and reproducing block unit data
US5228041A (en) * 1987-06-12 1993-07-13 Matsushita Electric Industrial Co., Ltd. Sync signal detection system in a memory system for recording and reproducing block unit data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021897A (en) * 1987-06-12 1991-06-04 Matsushita Electric Industrial Co., Ltd. Memory system for recording and reproducing block unit data
US5228041A (en) * 1987-06-12 1993-07-13 Matsushita Electric Industrial Co., Ltd. Sync signal detection system in a memory system for recording and reproducing block unit data

Also Published As

Publication number Publication date
JPH0668883B2 (en) 1994-08-31

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