JPS6129216B2 - - Google Patents

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Publication number
JPS6129216B2
JPS6129216B2 JP50105370A JP10537075A JPS6129216B2 JP S6129216 B2 JPS6129216 B2 JP S6129216B2 JP 50105370 A JP50105370 A JP 50105370A JP 10537075 A JP10537075 A JP 10537075A JP S6129216 B2 JPS6129216 B2 JP S6129216B2
Authority
JP
Japan
Prior art keywords
phase
circuit
current
terminal
zero
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50105370A
Other languages
Japanese (ja)
Other versions
JPS5228650A (en
Inventor
Kenji Suzuki
Makoto Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP50105370A priority Critical patent/JPS5228650A/en
Publication of JPS5228650A publication Critical patent/JPS5228650A/en
Publication of JPS6129216B2 publication Critical patent/JPS6129216B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 この発明は、被保護系統が、特に送電保護等に
おいて各端子電流を互に他の全端子に伝送して差
動保護しようとする多端子差動保護継電装置の異
常検出装置に関するものである。
[Detailed Description of the Invention] The present invention provides a multi-terminal differential protection relay device in which a protected system attempts differential protection by transmitting each terminal current to all other terminals, especially in power transmission protection, etc. The present invention relates to an abnormality detection device.

近年、需要電力増大の必要から超高圧送電線を
3端子系とすることが多いが、3端子系であるが
故に、従来の汎用保護継電方式である方向比較搬
送保護継電方式、あるいは位相比較搬送保護継電
方式では、その保護能力に限界がある。
In recent years, due to the need to increase power demand, ultra-high voltage power transmission lines are often made into three-terminal systems. Comparative carrier protection relay systems have limits to their protection capabilities.

このため、いかなる系統条件にあつても確実な
保護能力を発揮する電流差動搬送保護方式の適用
が注目されている。
For this reason, attention is being paid to the application of a current differential transfer protection system that provides reliable protection under any system conditions.

周知に如く電流差動方式を各端子間が互に離れ
ている送電線保護等に適用する場合、各端子電流
を互に他の全端子に伝送することが必要で、電力
線搬送、マイクロ回線等の手段によつている。
As is well known, when applying the current differential method to protection of power transmission lines where the terminals are separated from each other, it is necessary to transmit the current from each terminal to all other terminals, and it is necessary to transmit the current from each terminal to all the other terminals. It depends on the means of

従つて、一口に電流差動といつても電流を電圧
に変換する回路、電圧を変調して伝送に適したも
のにする変調回路、伝送路、伝送された波形を受
信して元の波形を再現させる復調回路、そして復
調された波形から差動保護をする差動保護回路
等、非常に複雑かつ多数の回路が途中に挿入され
ているので、このうちのどの部分に不具合が発生
しても忠実な波形の再現ができず、又、伝送路は
一般に空中にさらされているので、雑音等の侵入
による外乱の影響をもろに受けるので、差動保護
を実施する上で誤判定する可能性がでてくる。
Therefore, current differential means a circuit that converts current into voltage, a modulation circuit that modulates voltage to make it suitable for transmission, a transmission line, and a circuit that receives the transmitted waveform and converts it to the original waveform. A large number of extremely complex circuits are inserted in the middle, such as a demodulation circuit for reproduction and a differential protection circuit for differential protection from the demodulated waveform, so even if a problem occurs in any part of these circuits, It is not possible to reproduce faithful waveforms, and since the transmission line is generally exposed to the air, it is susceptible to disturbances such as noise, so there is a possibility of erroneous judgments when implementing differential protection. comes out.

この発明は、上記原因による誤判定を防止して
信頼度の高い多端子差動保護継電装置を実現させ
るために、当該端子から送られて復調された各相
の電流ベクトル和と、当該端子からの零相電流を
前記各相と同様に送り、復調して零相の電流ベク
トルを作り、前記各相の電流ベクトル和と比較す
ることによつて伝送路を含めた異常現象を検出す
ることを提案するものである。
In order to prevent misjudgments due to the above causes and realize a highly reliable multi-terminal differential protection relay device, the present invention provides a combination of the current vector sum of each phase sent from the terminal and demodulated, and the Detect abnormal phenomena including the transmission line by sending the zero-phase current from the same as for each phase, demodulating it to create a zero-phase current vector, and comparing it with the sum of the current vectors of each phase. This is what we propose.

説明の都合上、従来の異常検出方式、本発明に
よる異常検出方式の実施例のいずれも2端子系送
電線で、伝送方式は、周波数変調(以下FM変調
と呼ぶ)で伝送路に雑音が侵入した場合について
説明する。
For convenience of explanation, both the conventional abnormality detection method and the embodiment of the abnormality detection method according to the present invention are two-terminal power transmission lines, and the transmission method uses frequency modulation (hereinafter referred to as FM modulation) to prevent noise from entering the transmission path. Let's explain the case.

第1図は、A端、B端の2端子系送電線保護に
適用されたFM方調方式による差動保護の回路構
成原理を説明するために1相分について示したも
ので、1,11は遮断器(以下CBと称す)、2,
12はCT、3,13はCT2次電流を処理し易く
するため電圧に変換するI―V変換器、4,14
は電圧の瞬時値を伝送のため周波数の大小に変換
するV―F変換器5,15は送信部で、互に他の
端子にFM変調された信号を伝送するもの、6,
16は受信部で互に他の端子からの信号を受信す
るためのもの、7,17は受信周波数の大小を電
圧の瞬時値に変換するF―V変換器である。8と
18は前記I―V変換器3,13の電圧値と、前
記F―V変換器7,17の電圧値とを入力として
差動保護を行なう差動保護回路であり、この差動
保護回路の判定によつて、系統事故がA端、B端
の間に発生したとき出力し、それぞれCB1と1
1に指令を出し、送電を停止するように構成され
る。
Figure 1 shows one phase in order to explain the circuit configuration principle of differential protection using the FM scheme applied to two-terminal power transmission line protection at ends A and B. is a circuit breaker (hereinafter referred to as CB), 2,
12 is a CT; 3 and 13 are IV converters that convert the CT secondary current into voltage to make it easier to process; 4 and 14
V-F converters 5 and 15, which convert the instantaneous value of voltage into a frequency for transmission, are transmitting sections, and transmit FM-modulated signals to other terminals;
Reference numeral 16 designates a receiving section for receiving signals from other terminals, and reference numerals 7 and 17 designate FV converters that convert the magnitude of the reception frequency into an instantaneous value of voltage. 8 and 18 are differential protection circuits that perform differential protection by inputting the voltage values of the IV converters 3 and 13 and the voltage values of the FV converters 7 and 17; Based on the judgment of the circuit, it is output when a system fault occurs between terminals A and B, and outputs CB1 and CB1 respectively.
1 to stop power transmission.

第2図、第3図は第1図装置の動作説明図であ
り、第2図は系統の外部事故X、第3図は内部事
故Yに対して差動保護する原理を説明したもので
ある。
Figures 2 and 3 are explanatory diagrams of the operation of the device shown in Figure 1. Figure 2 explains the principle of differential protection against an external accident X in the system, and Figure 3 explains the principle of differential protection against an internal accident Y. .

第1図において、外部事故がX点で発生したと
すれば、CT1,11を流れる事故電流は互に逆
極性となり貫通する電流となる。
In FIG. 1, if an external fault occurs at point X, the fault currents flowing through CTs 1 and 11 have opposite polarities and become penetrating currents.

第2図aはこの電流を示したもので、A端、B
端で逆位相になつている。bはI―V変換器3,
13の出力であり、この出力によりcにに示すよ
うにFM変調された出力V―F変換器4,14か
ら得られる。すなわち、波形の大きい時は周波数
大とし、波形の小さい時は周波数小と制御され
る。
Figure 2a shows this current, with terminal A and terminal B
They are out of phase at the ends. b is the IV converter 3,
13, and this output is obtained from the FM-modulated output VF converters 4 and 14 as shown in c. That is, when the waveform is large, the frequency is controlled to be high, and when the waveform is small, the frequency is controlled to be low.

このFM変調された波をdに示すように互に受
信してeに示すように、F―V変換器7,17で
復調して電圧にもどす。f,gは差動保護回路
8,18の内部状態を示したもので、fはbとe
を加算したもので動作力を形成し、gはbとeを
減算したもので抑制力を形成する。
These FM modulated waves are mutually received as shown in d and demodulated by F-V converters 7 and 17 to return to voltage as shown in e. f and g indicate the internal states of the differential protection circuits 8 and 18;
The sum of g forms the operating force, and the subtraction of b and e forms the restraining force.

従つて第2図ではA端、B端とも動作力が零
で、抑制力のみが存在するので、差動保護回路か
ら出力が出ない。このため、CBの開放は行なわ
れないことになる。
Therefore, in FIG. 2, the operating force is zero at both the A terminal and the B terminal, and only the suppressing force exists, so that no output is output from the differential protection circuit. Therefore, CB will not be opened.

第3図は第1図において、内部事故がY点で発
生したときの説明図で、B端の事故電流は明らか
にX点事故と逆方向になる。従つて、第3図では
第2図と比べて、B端のa,b,c,A端のd,
eが逆位相になることによつて、差動保護回路の
動作力はbとeの加算で出力が出てfとなり、抑
制力はbとeの減算でgに示すように出力が無く
なる。
FIG. 3 is an explanatory diagram when an internal fault occurs at point Y in FIG. 1, and the fault current at end B clearly goes in the opposite direction to the fault at point X. Therefore, in Fig. 3, compared to Fig. 2, a, b, c at the B end, d at the A end,
Since e is in the opposite phase, the operating force of the differential protection circuit is outputted by adding b and e and becomes f, and the suppressing force is reduced by subtracting b and e, as shown in g.

従つて、第3図ではA端、B端とも動作力のみ
存在して、抑制力が零となるから、差動保護回路
から出力が出て、両端のCB1,11が開放され
ることになる。
Therefore, in Figure 3, only the operating force exists at both ends A and B, and the suppressing force is zero, so an output is output from the differential protection circuit and CB1 and 11 at both ends are opened. .

第1図は、単線図にて原理構成を説明したが系
統を差動保護する場合、各相毎に両端電流の比較
を行なうため、第4図の構成となる。この第4図
は、差動保護継電器の従来の構成を示したもの
で、A端からB端に電流を電送する場合について
示したものであり、B端からA端に伝送する場合
も同様である。
Although FIG. 1 illustrates the principle configuration using a single line diagram, when the system is differentially protected, the currents at both ends are compared for each phase, so the configuration is as shown in FIG. 4. This figure 4 shows the conventional configuration of a differential protection relay, and shows the case where current is transmitted from the A terminal to the B terminal, and the same applies when transmitting current from the B terminal to the A terminal. be.

先づA端で、2a〜2cはCTで2次電流を3
a〜3cで示すI―V変換器に流して電圧を得
て、4a〜4cのV―F変換器でFM変調する。
これら各相の出力を送信機5a〜5cでB端に伝
送する。
First, at the A terminal, 2a to 2c are CT to increase the secondary current by 3.
A voltage is obtained by passing it through the IV converters shown as a to 3c, and FM modulation is performed by the VF converter shown as 4a to 4c.
The outputs of these phases are transmitted to the B end by transmitters 5a to 5c.

B端ではこの伝送を16a〜16cの受信機で
受けて、17a〜17cのF―V変換器で復調し
て、差動保護回路18a〜18cの一方の入力と
し、B端の電流から得られた電圧Va,Vb,Vcを
他の入力として差動保護を行なう。
At the B end, this transmission is received by the receivers 16a to 16c, demodulated by the F-V converters 17a to 17c, and used as one input of the differential protection circuits 18a to 18c. Differential protection is performed using the other input voltages Va, Vb, and Vc.

この差動保護回路の出力信号は、系統事故が内
部であればインヒビツト回路22を径て、B端
CB(図示せず)に送られ、CBが開放される。
If the system fault is internal, the output signal of this differential protection circuit will be routed through the inhibit circuit 22 to the B terminal.
The signal is sent to the CB (not shown), and the CB is released.

今、伝送路に雑音が侵入したとすれば、B端で
は信号が誤つて伝えられたことになり、―V変換
器17a〜17cの全部又は一部が誤出力とな
り、差動保護回路18a〜18cの全部又は一部
が誤しや断信号を出してしまい、系統健全時と外
部事故時に問題となる。
If noise were to enter the transmission path now, the signal would be erroneously transmitted at the B end, causing all or part of the -V converters 17a to 17c to output incorrectly, and the differential protection circuits 18a to All or part of 18c may issue an error or a disconnection signal, which poses a problem both when the system is healthy and when an external accident occurs.

従つて、対策として、雑音が侵入したことを検
出してしや断をロツクすることが一般に行なわれ
ている。
Therefore, as a countermeasure, it is common practice to detect the intrusion of noise and lock the interruption.

A端に、一定周波数Foの発振器20を設置
し、送信機SoでB端に送信すれば、B端の受信
機16nは一定周波数を受信している。これをF
―V変換器17nで電圧に変換すればVoの一定
電圧が得られる、今、雑音N2が伝送路に侵入す
れば受信周波数は一定でなくなり、F―V変換器
17nの出力はV2に変化するので、その出力を
検出器21で検出することができる。従つて、検
出器21の出力が出ることをもつて、インヒビツ
ト回路22で差動保護回路18a〜18cの信号
をロツクすれば、CBの誤しや断は防止できる。
If an oscillator 20 with a constant frequency F o is installed at the A end and the transmitter S o transmits to the B end, the receiver 16n at the B end receives the constant frequency. F this
- If the voltage is converted to voltage by the V converter 17n, a constant voltage of V o can be obtained. If noise N 2 enters the transmission path, the receiving frequency will no longer be constant, and the output of the F-V converter 17n will be V 2 The output can be detected by the detector 21. Therefore, by locking the signals of the differential protection circuits 18a to 18c with the inhibit circuit 22 when the output of the detector 21 is output, CB errors and disconnections can be prevented.

第5図は、一定周波数Foに雑音が侵入したと
きの状態を説明するためのもので、イは周波数―
電圧の変換特性を示したものでFoのときVoの電
圧が得られているが、F2になるとV2に、F1にな
るとV1になる。ロはタイムチヤートで、dは一
定周波数(周期t)のものが、雑音N2が侵入し
て周期が密になつた場合と、大きさが反体の雑音
N1が侵入して周期が粗になつた場合を示したも
ので、F―V変換器ではeに示す出力となる、こ
れを検出器のレベル(LD2又はLD1)で検出して、
出力hを得ることができる。
Figure 5 is for explaining the situation when noise enters a constant frequency F o , where A is the frequency -
This shows the voltage conversion characteristics, and when F o, the voltage of V o is obtained, but when it becomes F 2 , it becomes V 2 , and when it becomes F 1, it becomes V 1 . B is a time chart, and d is a constant frequency (period t), when noise N 2 enters and the period becomes dense, and when the noise is opposite in magnitude.
This shows the case where N 1 enters and the period becomes coarse, and the F-V converter outputs as shown in e. This is detected at the detector level (LD 2 or LD 1 ),
An output h can be obtained.

従つて、hに示した信号で、前述のインヒビツ
ト回路を制限するようにしていた。
Therefore, the above-mentioned inhibit circuit was limited by the signal shown in h.

このように、従来の雑音検出方式は、各相とは
別に雑音検出相を設置して伝送路に、一定周波数
の信号を乗せて送り、受信側でこれを復調し一定
の電圧を得て、雑音が侵入したときには、復調し
た電圧が変化することを利用して検出していた。
In this way, the conventional noise detection method installs a noise detection phase separately from each phase, sends a signal with a constant frequency on the transmission path, demodulates this on the receiving side to obtain a constant voltage, When noise invades, it is detected by using changes in the demodulated voltage.

このような従来の方法では、各相と雑音検出相
の伝送路が別であるため、各相の例えばa相の伝
送路にのみ雑音が侵入して、b相、c相及び雑音
検出相に侵入しなければ、雑音検出が不可能で、
誤しや断する可能性があつた。
In such conventional methods, the transmission paths for each phase and the noise detection phase are separate, so noise enters only the transmission path of each phase, for example, the A phase, and is transmitted to the B phase, C phase, and the noise detection phase. Noise detection is impossible without intrusion,
There was a possibility of making a mistake or making a mistake.

また伝送路に侵入する雑音以外に、第4図で示
した各相のI―V変換器3a〜3c,V―F変換
器4a〜4c,送信機5a5e,受信機16a〜
16c,F―V変換器17a〜17eのいずれか
が異常になつた場合にも、差動保護の原理が成立
しなくなり、誤しや断する可能性があつた。
In addition to the noise that invades the transmission path, the I-V converters 3a to 3c, V-F converters 4a to 4c, transmitters 5a5e, and receivers 16a to 16a of each phase shown in FIG.
16c and any of the F-V converters 17a to 17e becomes abnormal, the principle of differential protection no longer holds true, and there is a possibility of an error or disconnection.

この発明は、このような実情に鑑みてなされた
もので、各相電流の他に、零相電流も伝送して、
受信側で総和をとるようにして、雑音が侵入又は
回路の異常がなければ、常に総和が零、雑音が侵
入又は回路が異常となれば、零でなくなることを
利用して雑音又は回路の異常を検出する方式を提
案するものである。
This invention was made in view of these circumstances, and in addition to each phase current, zero-phase current is also transmitted,
By calculating the sum on the receiving side, if there is no noise intrusion or circuit abnormality, the sum is always zero, and if noise intrusion or circuit abnormality occurs, the sum is not zero. This paper proposes a method for detecting

以下、この発明の実施例について説明する。 Examples of the present invention will be described below.

すなわち、第6図において、A端のCT2次の零
相電流回路にI―V変換器30を設置し、その出
力電圧をV―F変換器40に入れてFM変調す
る。これを送信機50にて信号をB端に伝送す
る。
That is, in FIG. 6, an IV converter 30 is installed in the CT second-order zero-phase current circuit at the A terminal, and its output voltage is input to a V-F converter 40 for FM modulation. The transmitter 50 transmits the signal to the B end.

B端では受信機160でこれを受信して、F―
V変換器170で電圧に復調する。
At the B end, the receiver 160 receives this and sends it to the F-
The V converter 170 demodulates it into a voltage.

これら、零相電流伝送用の各I―V変換器V―
F変換器、送信機、受信機、F―V変換器は各相
のものと同一である。F―V変換器170で復調
された電圧は符号反転器23に送られ、極性が逆
にされる。
These IV converters for zero-phase current transmission V-
The F converter, transmitter, receiver, and F-V converter are the same for each phase. The voltage demodulated by the FV converter 170 is sent to the sign inverter 23 and its polarity is reversed.

一方、各相電流を復調した各相の電圧は、各相
の差動保護回路18a〜18cへ与えられると同
時に、総和回路24の入力として与えられる。こ
れと、前記符号反転器23の出力との総和を得
て、検出器21に送られ、総和が設定値を超えれ
ば、インヒビツト回路22に信号が送られ、差動
保護回路18a〜18cから、B端CB(図示せ
ず)へのしや断信号をロツクする。B端からA端
にも、図示はしないが、全く同様の回路構成が設
けられる。
On the other hand, the voltage of each phase obtained by demodulating each phase current is provided to the differential protection circuits 18a to 18c of each phase, and at the same time, is provided as an input to the summation circuit 24. The sum of this and the output of the sign inverter 23 is obtained and sent to the detector 21. If the sum exceeds the set value, a signal is sent to the inhibit circuit 22, and from the differential protection circuits 18a to 18c, Locks the break signal to the B end CB (not shown). Although not shown, a completely similar circuit configuration is provided from the B end to the A end.

今、A端で各相電流をIa,Ib,Ic,零相電流を
3I0とすれば、系統が正常な場合でも、系統事故
がある場合でも、必ず3I0=Ia+Ib+Icの関係が成
立するので、これをB端に伝送して復調して得ら
れた電圧をIa→V′a,Ib→V′b,Ic→V′c,3I0
3V′0とすれば、必ず3V′0=V′a+V′b+V′cの関係
が成立する。
Now, at the A terminal, each phase current is Ia, Ib, Ic, and zero phase current is
If 3I 0 , the relationship 3I 0 = Ia + Ib + Ic will always hold whether the system is normal or there is a system fault, so this is transmitted to the B terminal and the voltage obtained by demodulating is Ia → V′a, Ib→V′b, Ic→V′c, 3I 0
If 3V′ 0 , then the relationship 3V′ 0 =V′a+V′b+V′c always holds true.

3V′0を符号反転器23に与えて得られる出力
は、−3V′0であるから総和回路24の入力は Σ=Va′+Vb′+Vc′−3I0′となり 雑音の侵入がなければ又は回路が正常であればΣ
=0となる。
The output obtained by applying 3V' 0 to the sign inverter 23 is -3V' 0 , so the input of the summation circuit 24 is Σ=Va'+Vb'+Vc'-3I 0 ', and if there is no noise intrusion, the circuit If is normal, Σ
=0.

もし雑音が、4個の伝送路のどれにでも侵入し
たり、回路が異常となれば、Σ≠0となり、総和
回路24から出力が出て、検出器21で検出する
ことができる。
If noise enters any of the four transmission paths or the circuit becomes abnormal, Σ≠0, an output is output from the summation circuit 24, and can be detected by the detector 21.

第7図は、本発明の動作状態を説明するタイム
チヤートであり、(イ)は系統が正常で、雑音の侵入
がなく回路が正常の場合、(ロ)と(ハ)は系統に1線地
絡事故が発生して(ロ)は雑音の侵入がなく回路が正
常の場合、(ハ)はa相にのみ雑音が侵入したが回路
が異常の場合を示したものである。
FIG. 7 is a time chart explaining the operating state of the present invention. (A) is when the system is normal and there is no noise intrusion and the circuit is normal, (B) and (C) are when there is only one line in the system. When a ground fault occurs, (b) shows a case where there is no noise intrusion and the circuit is normal, and (c) shows a case where noise intrudes only into the a phase but the circuit is abnormal.

(イ)の(e)に示す波形は、復調波形、Va′,Vb′,
Vc′,3V0′であり系統が正常であるから3V0′=0
である。
The waveform shown in (e) of (a) is the demodulated waveform, Va′, Vb′,
Vc′, 3V 0 ′ and the system is normal, so 3V 0 ′=0
It is.

(j)は総和回路の出力Σを示したもので零とな
り、従つて(k)に示す検出器の出力も零となる。
(j) shows the output Σ of the summation circuit, which becomes zero, and therefore the output of the detector shown in (k) also becomes zero.

(ロ)は1線地絡で、a相の波形Va′が零相の波形
3V0′と同しになり、Σ=Va′−3V0′=0であるか
ら、(j),(k)とも零である。
(b) is a one-wire ground fault, and the a-phase waveform Va′ is a zero-phase waveform.
Since it is the same as 3V 0 ′ and Σ=Va′−3V 0 ′=0, both (j) and (k) are zero.

(ハ)は1線地絡a相に雑音が侵入するか又は回路
が異常となつてVa′の点線部分が復調されなかつ
た場合を示したもので、この場合Σ=Va′−
3V0′≠0となり、(j)に示すようにその誤差分だけ
出力が現われ、検出レベルLDを超えたとき、(k)
で示す出力が得られる。この出力を前記インヒビ
ツト回路に撞入して、前記差動回路からのしや断
信号を阻止することによつて、外部事故時の誤し
や断をロツクできる。
(C) shows the case where the dotted line portion of Va' is not demodulated due to noise entering the a phase of the single-wire ground fault or the circuit becoming abnormal; in this case, Σ=Va'-
3V 0 '≠0, and as shown in (j), the output appears by the amount of the error and exceeds the detection level LD, (k)
The output shown is obtained. By inputting this output to the inhibit circuit and blocking the failure signal from the differential circuit, it is possible to lock out errors and disconnections in the event of an external fault.

なお、前記実施例では、第6図に示すように、
零相電流成分を得るために零相のI―V変換器3
0を使用したもので説明したが、各相のI―V変
換器3a〜3cの異常発生が無視できるならば、
零相I―V変換器30を省略して、第9図に示し
たように、各相のI―V変換器3a〜3cの出力
電圧を合成する加算回路31を設ける変形も可能
である。この加算回路31の出力は、零相電流成
分に比例したものであることは自明である。この
場合は、当然、各相のI―V変換器3a〜3cの
異常を検出することができないが、それ以降に結
合されているV―F変換器4a〜4c,送信機5
a〜5c,受信機16a〜16c及びF―V変換
器17a〜17cの異常と、伝送路に侵入する雑
音とを検出することは、可能である。
In addition, in the above embodiment, as shown in FIG.
Zero-phase IV converter 3 to obtain zero-phase current component
0, but if the occurrence of abnormalities in the IV converters 3a to 3c of each phase can be ignored,
It is also possible to omit the zero-phase IV converter 30 and provide an adder circuit 31 for synthesizing the output voltages of the IV converters 3a to 3c of each phase, as shown in FIG. It is obvious that the output of this adder circuit 31 is proportional to the zero-phase current component. In this case, it is naturally impossible to detect an abnormality in the IV converters 3a to 3c of each phase, but the VF converters 4a to 4c and the transmitter 5 connected after that cannot be detected.
It is possible to detect abnormalities in the transmitters a to 5c, receivers 16a to 16c, and FV converters 17a to 17c, as well as noise entering the transmission path.

内部事故時には、このロツクはしや断ロツクと
なり、しや断時間を遅くすることになるが、これ
は従来方式でも同様である。
In the event of an internal accident, this lock becomes a failure lock, slowing down the failure time, and this is the same in the conventional system.

なお、前記実施例においては、3V0′を符号反転
して、各相電流の復調波との総和をとるとして説
明したが、符号反転させないで、各相電流の復調
波の和との大小比較(差分をとる)させてもよ
い。また、前記実施例においては、2端子系につ
いて述べたが、3端子以上の各端子であつてもよ
い。
In the above embodiment, it was explained that the sign of 3V 0 ' is inverted and the sum of the demodulated waves of each phase current is calculated. (take the difference). Further, in the above embodiments, a two-terminal system was described, but three or more terminals may be used.

なお、前記実施例においては、伝送路が各相電
流分それぞれと、零相電流との合計4回線あり、
電流を並列に同時に伝送するとして説明したが、
PCM等を利用したデイジタル伝送を利用して伝
送路は1回線で、時間的に分割して各相電流と零
相電流とを送信する第8図の方式であつても、1
フレーム分を時間的に記憶して各相電流の和の成
分と零相電流成分とを比較する方式であつてもよ
い。
In the above embodiment, there are a total of four transmission lines, one for each phase current and one for the zero-phase current.
I explained that the current is transmitted simultaneously in parallel, but
Even if the method shown in Fig. 8 uses digital transmission using PCM etc., the transmission path is one line, and each phase current and zero-phase current are transmitted temporally divided.
It may be a method of temporally storing frames and comparing the sum component of each phase current with the zero-sequence current component.

前記のようにこの発明による差動保護継電装置
の異常検出装置は、各相電流の和と零相電流と
が、系統状態にかかわらず、常に等しいという原
理を利用しているので、異常が特定の相にだけ発
生した場合にでも確実に検出できる効果がある。
As mentioned above, the abnormality detection device for the differential protection relay device according to the present invention utilizes the principle that the sum of the phase currents and the zero-sequence current are always equal regardless of the system status, so that abnormalities can be detected. This has the effect of ensuring reliable detection even when it occurs only in a specific phase.

また、各相電流の伝送と全く同じ回路方式によ
る零相電流の伝送を行なうため、回路定数等の変
化にるばらつきも各相で同一であるため相殺さ
れ、検出感度の変動が少ない。
Furthermore, since the zero-phase current is transmitted using exactly the same circuit system as the transmission of each phase current, variations due to changes in circuit constants, etc. are the same for each phase and are canceled out, resulting in little variation in detection sensitivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は2端子系送電線の差動保護の回路構成
図で、第2図、第3図はその動作説明図、第4図
は従来の差動保護継電器の雑音検出方式を示す回
路構成図、第5図は従来の雑音検出方法を説明す
る図、第6図と第9図は本発明による差動保護継
電器の雑音検出方式を示す回路構成図、第7図は
本発明の雑音検出方法を説明する図、第8図は伝
送路が1回線の伝送形態を示す図であり、 図において1,11,1a〜1cは遮断器、
2,12,2a〜2cはCT、3,13,3a〜
3c,30はI―V変換器、4,14,4a〜4
c,40はV―F変換器、5,15,5a〜5
c,50,5nは送信機、6,16,16a〜1
6c,160,16nは受信機、7,17,17
a〜17c,170,17nはF―V変換器、
8,18,18a〜18cは差動保護回路、9は
被保護送電線、20は発振器、21は検出器、2
2はインヒビツト回路、23は符号反転回路、2
4は総和回路31は加算回路である。尚、各図中
同一符号は同一又は相当部分を示す。
Figure 1 is a circuit configuration diagram of differential protection for a two-terminal power transmission line, Figures 2 and 3 are diagrams explaining its operation, and Figure 4 is a circuit configuration showing the noise detection method of a conventional differential protection relay. Figure 5 is a diagram explaining the conventional noise detection method, Figures 6 and 9 are circuit configuration diagrams showing the noise detection method of the differential protection relay according to the present invention, and Figure 7 is the noise detection method according to the present invention. Figure 8, which is a diagram explaining the method, is a diagram showing a transmission form in which the transmission line is one line, and in the diagram, 1, 11, 1a to 1c are circuit breakers,
2, 12, 2a ~ 2c are CT, 3, 13, 3a ~
3c, 30 are IV converters, 4, 14, 4a-4
c, 40 are V-F converters, 5, 15, 5a-5
c, 50, 5n are transmitters, 6, 16, 16a-1
6c, 160, 16n are receivers, 7, 17, 17
a to 17c, 170, 17n are F-V converters,
8, 18, 18a to 18c are differential protection circuits, 9 is a protected transmission line, 20 is an oscillator, 21 is a detector, 2
2 is an inhibit circuit, 23 is a sign inversion circuit, 2
4, the summation circuit 31 is an addition circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 被保護系統の一端子各相の電流を、他の全端
子に伝送して、各相分毎に差動保護する差動保護
継電装置の異常検出装置において、当該端子の各
相分電流を伝送する信号伝送路に、当該端子の零
相分電流を伝送する信号伝送路を設け、この信号
伝送路で伝送後、復調された各相分電流の各相の
和と零相分電流との差の有無を判定して差動保護
継電装置の異常を検出するようにしたことを特徴
とする差動保護継電装置の異常検出装置。
1. In an abnormality detection device for a differential protection relay device that transmits the current of each phase of one terminal of the protected system to all other terminals and provides differential protection for each phase, the current of each phase of the terminal is detected. A signal transmission path that transmits the zero-sequence current of the terminal is provided in the signal transmission path that transmits the current, and after transmission through this signal transmission path, the sum of each phase of the demodulated phase current and the zero-sequence current are calculated. 1. An abnormality detection device for a differential protective relay device, characterized in that an abnormality in the differential protective relay device is detected by determining the presence or absence of a difference between the two.
JP50105370A 1975-08-29 1975-08-29 Abnormality detector for differential protective relay Granted JPS5228650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50105370A JPS5228650A (en) 1975-08-29 1975-08-29 Abnormality detector for differential protective relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50105370A JPS5228650A (en) 1975-08-29 1975-08-29 Abnormality detector for differential protective relay

Publications (2)

Publication Number Publication Date
JPS5228650A JPS5228650A (en) 1977-03-03
JPS6129216B2 true JPS6129216B2 (en) 1986-07-05

Family

ID=14405810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50105370A Granted JPS5228650A (en) 1975-08-29 1975-08-29 Abnormality detector for differential protective relay

Country Status (1)

Country Link
JP (1) JPS5228650A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52103647A (en) * 1976-02-27 1977-08-31 Chugoku Electric Power Co Ltd:The Protection controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116932A (en) * 1973-06-13 1975-09-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116932A (en) * 1973-06-13 1975-09-12

Also Published As

Publication number Publication date
JPS5228650A (en) 1977-03-03

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