JPS6129153A - Flattening method of irregular surface substrate - Google Patents
Flattening method of irregular surface substrateInfo
- Publication number
- JPS6129153A JPS6129153A JP59149586A JP14958684A JPS6129153A JP S6129153 A JPS6129153 A JP S6129153A JP 59149586 A JP59149586 A JP 59149586A JP 14958684 A JP14958684 A JP 14958684A JP S6129153 A JPS6129153 A JP S6129153A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- irregular surface
- substrate
- surface substrate
- silicone resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はエレクトロニクスデバイスにおける凹凸基板の
平坦化方法に係り、特にＩ Ｃ、ＬＳＩ 、磁気バブル
メモリデバイス等の微細パターンを有するデバイスの層
間絶縁の方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for planarizing uneven substrates in electronic devices, and more particularly to a method for interlayer insulation of devices having fine patterns such as ICs, LSIs, and magnetic bubble memory devices. It is something.
従来の技術
従来上記の微細ノ４ターンを有するデバイスの層間絶縁
方法は、ＳＩを熱酸化することによって得られるＳｌＯ
□、シラン系ガスを用いた化学的気相成長（ＣＶＤ）法
によって得られる５１０２系絶縁材料、あるいはポリイ
ミド系樹脂、あるいはシリコーン樹脂等の有機系絶縁材
料を用いて行表われている。2. Description of the Related Art Conventionally, an interlayer insulation method for a device having four fine turns as described above uses SlO obtained by thermally oxidizing SI.
□, 5102 series insulating material obtained by chemical vapor deposition (CVD) using silane gas, or organic insulating material such as polyimide resin or silicone resin.
しかしながら４００〜１０００℃の温度における耐熱性
の問題、及び基板との密着性、絶縁不良で生じる電食性
、あるいは１．０μｍ以上の厚膜の形成性等における信
頼性の問題においてそれぞれ一長一短があシ、良好力層
間絶縁法が要望されている。However, each has advantages and disadvantages in terms of heat resistance at temperatures of 400 to 1000°C, adhesion to the substrate, electrolytic corrosion caused by poor insulation, and reliability in forming thick films of 1.0 μm or more. , a good strength interlayer insulation method is desired.
本発明で使用する絶縁材料に最も近いと思われる従来の
絶縁材料としてポリジアルコオキシシランがある。ポリ
ジアルコオキシシランは一般式変化する。この一般式中
でＲ′は一価の炭化水素、例えばＣＨ３，Ｃ２Ｈ５等や
水素を示す。一般にＯＲ’はアルコキシとＯＲの混合物
である。このアルコキシが熱分解あるいは縮重合するこ
とによって揮発する際、ポリマに与える歪とピンホール
のため０．２〜０．５μｍ以上の膜厚を有する絶縁膜を
形成するとクラックが入シ、またそれ以下の薄膜でも電
食不良を引き起す。Polydialkoxysilane is a conventional insulating material that is considered to be closest to the insulating material used in the present invention. Polydialkoxysilanes vary in general formula. In this general formula, R' represents a monovalent hydrocarbon such as CH3, C2H5, etc. or hydrogen. Generally OR' is a mixture of alkoxy and OR. When this alkoxy volatilizes through thermal decomposition or polycondensation, cracks will occur if an insulating film is formed with a thickness of 0.2 to 0.5 μm or more due to the strain and pinholes it gives to the polymer. Even a thin film can cause electrolytic corrosion defects.
発明が解決しようとする問題点
以上の点を鑑みて凹凸基板の平坦化材料に有効な性質と
しては以下の２つの点が考えられる（１）全く熱分解揮
発物を生成しない材料、この性質を有する材料はＳｉｎ
、及び５ｌＯ２の１分子づつが遊離した状態で集合して
いるものであるが現実的でない。In view of the above-mentioned problems that the invention aims to solve, the following two points can be considered as effective properties for a material for flattening an uneven substrate: (1) A material that does not generate any pyrolytic volatiles; The material has Sin
, and 5lO2 are aggregated in a free state, but this is not realistic.
（２）熱分解温度が高く、且つ熱分解揮発物の生成が少
ないものでその抜は穴を何らかの方法で埋めることが可
能な材料、
本発明ではこの（２）の材料の性質を有する材料を見出
そうとするものである。(2) A material that has a high pyrolysis temperature and generates little pyrolysis volatiles, and can fill the holes by some method.The present invention uses a material that has the properties of the material in (2). This is what we are trying to find out.
本発明の目的は凹凸基板上に塗布形成した際にピンホー
ル、クラック等を発生することなしに厚膜形成が可能な
緻密々平坦化機能を有する、凹凸基板を平坦化する方法
を提供することである。An object of the present invention is to provide a method for planarizing an uneven substrate, which has a dense planarization function that allows a thick film to be formed without generating pinholes, cracks, etc. when coating is formed on an uneven substrate. It is.
問題点を解決するための手段
上記問題点は本発明によれば
一般式： Ｒ３−８１０＋ＣＨ３８１０，５−）Ｓｉ
Ｒ３上記式中ＲはＣＨ，、Ｃ（ＣＨ３） 、 Ｃ２Ｉ（
５もしくはＣ６Ｈ５で示される重量平均分子量約４００
００以上のシリコーン樹脂を凹凸基板上に形成し、該シ
リコーン樹脂を加熱溶融することを特徴とする凹凸基板
の平坦化方法によって達成される。Means for Solving the Problems The above problems are solved according to the present invention by the general formula: R3-810+CH3810,5-)Si
R3 In the above formula, R is CH,, C(CH3), C2I(
5 or C6H5 weight average molecular weight of about 400
This is achieved by a method for planarizing an uneven substrate, which is characterized by forming a silicone resin of 0.00 or more on an uneven substrate and heating and melting the silicone resin.
作用
本発明によれば該シリコーン樹脂の流動温度が重量平均
分子量２５０００〜５００００で３００〜４００℃であ
るために該シリコン樹脂の熱硬化を３５０〜４００℃で
行うことにより硬化の際に発生する熱分解生成物による
ピンホール及び歪を緩和することが出来る。また、該シ
リコーン樹脂 １が流動するため凹凸基板は
、完全に平坦化できる。Effect According to the present invention, since the flow temperature of the silicone resin is 300 to 400°C with a weight average molecular weight of 25,000 to 50,000, heat generated during curing can be reduced by thermally curing the silicone resin at 350 to 400°C. Pinholes and distortion caused by decomposition products can be alleviated. Furthermore, since the silicone resin 1 flows, the uneven substrate can be completely flattened.
更に、本発明に用いられるシリコーン樹脂はポリメチル
シルセスキオキサン（ＰＭＳＳ）が好ましいが該ＰＭＳ
Ｓは室温で固体でちゃ、例えばスピンコード等の回転
塗布法を用いて凹凸基板に塗布する時はトルエン、キシ
レン、等の芳香族系の有機溶剤に溶解して用いる。ＰＭ
Ｓ Ｓの膜厚制御は重量平均分子量、有機溶剤の種類、
濃度、回転数によって可能である。Further, the silicone resin used in the present invention is preferably polymethylsilsesquioxane (PMSS), but the PMS
S is solid at room temperature, and when it is applied to a textured substrate using a spin coating method such as a spin cord, it is used after being dissolved in an aromatic organic solvent such as toluene or xylene. PM
The film thickness of SS can be controlled by weight average molecular weight, type of organic solvent,
Possible depending on concentration and rotation speed.
実施例 以下本発明の詳細な説明する。Example The present invention will be explained in detail below.
トリクロルメチルシラン（ＴＣＭＳ）をメチルイソブチ
ルケトン（ＭＩ ＢＫ）中で水を用いて約５時間重合さ
せ、トリメチルクロルシラン（ＴＭ０１）でシリル化し
た重量平均分子量約３００００のＰＭＳＳをトルエンに
溶解し、２０重量パーセントの樹脂液を作製した。Trichloromethylsilane (TCMS) was polymerized in methyl isobutyl ketone (MI BK) using water for about 5 hours, and PMSS, which had been silylated with trimethylchlorosilane (TM01) and had a weight average molecular weight of about 30,000, was dissolved in toluene. A weight percent resin solution was prepared.
次にシリコーン基板上に形成された厚さ０．９μｍ１最
小線幅３μｍ１最小線間隔２μｍのアルミニウム配線上
に、上記の樹脂液を２５０Ｏｒｐｍ。Next, the above resin liquid was applied at 250 rpm onto aluminum wiring having a thickness of 0.9 μm, a minimum line width of 3 μm, and a minimum line spacing of 2 μm formed on a silicone substrate.
４０秒の条件で回転塗布し、８０℃３０分間の溶剤乾燥
後、窒素気流中、３５０℃の温庫で６０分間熱処理を行
なった（該温度は３５０〜４００℃が好ましい）。上記
アルミ配線上では０．６μｍス被−メースは１．５μｍ
の膜厚が確保され、段差は０．０５μｍとほぼ平坦化が
達成された。Spin coating was carried out for 40 seconds, and after drying the solvent at 80°C for 30 minutes, heat treatment was performed in a nitrogen stream for 60 minutes in a 350°C warm room (the temperature is preferably 350 to 400°C). On the above aluminum wiring, the thickness of 0.6μm is 1.5μm.
A film thickness of 0.05 μm was ensured, and almost flatness was achieved with a step difference of 0.05 μm.
このようにして形成されたＰＭＳ Ｓ平坦膜上にＰＳＧ
を公知の方法で形成し、次にスルーホールを形成後、二
層目のアルミニウム配線を形成し、更に保獲層として、
１３μｍの膜厚のＰＳＧ層を形成した。次に電極取り出
し用窓開けを行なってバイポーラ素子装置を得た。この
素子は空気中５００℃の温度で１時間の加熱試験−６５
°Ｍ ｌ ５ Ｑ℃の繰り返し１０回の熱衝撃試験、８
５℃の温度で９０％ＲＨガス下で６■の印加電圧、、１
０００時間の試験後もその絶縁性その他の異常は発生し
なかった。PSG is applied on the PMS S flat film formed in this way.
is formed by a known method, and then after forming through holes, a second layer of aluminum wiring is formed, and further as a retention layer,
A PSG layer with a thickness of 13 μm was formed. Next, a window for taking out the electrodes was opened to obtain a bipolar element device. This element was tested in air at a temperature of 500°C for 1 hour -65
Thermal shock test repeated 10 times at °M l 5 Q °C, 8
Applied voltage of 6 ■ under 90% RH gas at a temperature of 5 °C, 1
Even after 1,000 hours of testing, no abnormalities in insulation or other problems occurred.
比較例
シリル化していないポリメチルシルセスオキサンを２０
ｗｔ ％の樹脂液として実施例と同様の基板上に２５
０Ｏｒｐｍ、４０秒の条件で回転塗布し、８０℃、３０
分の溶剤乾燥、３５０℃、６０分間の熱処理を行なった
。上記シリコーン樹脂の膜は、アルミ配線上でクラック
が発生した。また、１．０μｍ段差上で０．２μｍの段
差が残された。Comparative Example: 20% of non-silylated polymethylsilsesoxane
25 wt % resin liquid on the same substrate as in the example.
Spin coating at 0 rpm, 40 seconds, 80°C, 30
Solvent drying was performed for 30 minutes, and heat treatment was performed at 350° C. for 60 minutes. Cracks occurred on the aluminum wiring in the silicone resin film. Furthermore, a 0.2 μm step was left on the 1.0 μm step.
発明の詳細
な説明し）乞ように本発明によれば凹凸基板の平坦化を
歪がなく、且つ耐熱性、信頼性よく形成することができ
る。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, an uneven substrate can be flattened without distortion and with good heat resistance and reliability.
Claims (1)
．＿５）−ＳｉＲ＿３上記式中ＲはＣＨ＿３、Ｃ（ＣＨ
＿３）、Ｃ＿２Ｈ＿５もしくはＣ＿６Ｈ＿５で示される
重量平均分子量約４００００以上のシリコーン樹脂を凹
凸基板上に形成し、該シリコーン樹脂を加熱流動させる
ことを特徴とする凹凸基板の平坦化方法。 ２、前記シリコーン樹脂がシリル化ポリメチルシルセス
キオキサンであることを特徴とする特許請求の範囲第１
項記載の方法。 ３、前記加熱を３５０℃以上の温度で行なうことを特徴
とする特許請求の範囲第１項記載の方法。[Claims] 1. General formula: R_3-SiO-(CH_3SiO_1_
．． _5)-SiR_3 In the above formula, R is CH_3, C(CH
_3) A method for planarizing a textured substrate, comprising forming a silicone resin represented by C_2H_5 or C_6H_5 and having a weight average molecular weight of about 40,000 or more on a textured substrate, and heating and fluidizing the silicone resin. 2. Claim 1, wherein the silicone resin is silylated polymethylsilsesquioxane.
The method described in section. 3. The method according to claim 1, wherein the heating is performed at a temperature of 350° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149586A JPS6129153A (en) | 1984-07-20 | 1984-07-20 | Flattening method of irregular surface substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149586A JPS6129153A (en) | 1984-07-20 | 1984-07-20 | Flattening method of irregular surface substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6129153A true JPS6129153A (en) | 1986-02-10 |
| JPH0578939B2 JPH0578939B2 (en) | 1993-10-29 |
Family
ID=15478436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59149586A Granted JPS6129153A (en) | 1984-07-20 | 1984-07-20 | Flattening method of irregular surface substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6129153A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02106948A (en) * | 1988-10-17 | 1990-04-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760330A (en) * | 1980-09-27 | 1982-04-12 | Fujitsu Ltd | Resin composition |
| JPS5957437A (en) * | 1982-09-28 | 1984-04-03 | Fujitsu Ltd | Forming method for silicon oxide film |
-
1984
- 1984-07-20 JP JP59149586A patent/JPS6129153A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760330A (en) * | 1980-09-27 | 1982-04-12 | Fujitsu Ltd | Resin composition |
| JPS5957437A (en) * | 1982-09-28 | 1984-04-03 | Fujitsu Ltd | Forming method for silicon oxide film |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
| JPH02106948A (en) * | 1988-10-17 | 1990-04-19 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0578939B2 (en) | 1993-10-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |