JPS61290550A - 階層記憶制御方式 - Google Patents

階層記憶制御方式

Info

Publication number
JPS61290550A
JPS61290550A JP60131792A JP13179285A JPS61290550A JP S61290550 A JPS61290550 A JP S61290550A JP 60131792 A JP60131792 A JP 60131792A JP 13179285 A JP13179285 A JP 13179285A JP S61290550 A JPS61290550 A JP S61290550A
Authority
JP
Japan
Prior art keywords
data
memory
stored
address
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60131792A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0415494B2 (enrdf_load_stackoverflow
Inventor
Yasuhiko Matsuura
松浦　泰彦
Junichi Takuri
田栗　順一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60131792A priority Critical patent/JPS61290550A/ja
Publication of JPS61290550A publication Critical patent/JPS61290550A/ja
Publication of JPH0415494B2 publication Critical patent/JPH0415494B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP60131792A 1985-06-19 1985-06-19 階層記憶制御方式 Granted JPS61290550A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60131792A JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60131792A JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Publications (2)

Publication Number Publication Date
JPS61290550A true JPS61290550A (ja) 1986-12-20
JPH0415494B2 JPH0415494B2 (enrdf_load_stackoverflow) 1992-03-18

Family

ID=15066237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60131792A Granted JPS61290550A (ja) 1985-06-19 1985-06-19 階層記憶制御方式

Country Status (1)

Country Link
JP (1) JPS61290550A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01269142A (ja) * 1988-04-20 1989-10-26 Hitachi Ltd 計算機システム
DE4022885A1 (de) * 1989-07-18 1991-01-31 Hitachi Ltd Verfahren zum neuadressieren eines speichers und speichersystem mit einer rangordnung
JPH07121442A (ja) * 1993-10-14 1995-05-12 Internatl Business Mach Corp <Ibm> データ処理システム及び制御方法
JPH07152646A (ja) * 1993-07-15 1995-06-16 Bull Sa 記憶階層レベル間での交換のコヒーレンシー管理方法
JPH07210461A (ja) * 1993-12-28 1995-08-11 Internatl Business Mach Corp <Ibm> ストア・イン第２レベル・キャッシュ制御装置
US6240491B1 (en) 1993-07-15 2001-05-29 Bull S.A. Process and system for switching between an update and invalidate mode for each cache block

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109180A (en) * 1980-11-10 1982-07-07 Ibm Multiprocessing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109180A (en) * 1980-11-10 1982-07-07 Ibm Multiprocessing system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01269142A (ja) * 1988-04-20 1989-10-26 Hitachi Ltd 計算機システム
US5313602A (en) * 1988-04-20 1994-05-17 Hitachi, Ltd. Multiprocessor system and method of control over order of transfer of data between buffer storages
DE4022885A1 (de) * 1989-07-18 1991-01-31 Hitachi Ltd Verfahren zum neuadressieren eines speichers und speichersystem mit einer rangordnung
US5317704A (en) * 1989-07-18 1994-05-31 Hitachi, Ltd. Storage relocating method and hierarchy storage system utilizing a cache memory
JPH07152646A (ja) * 1993-07-15 1995-06-16 Bull Sa 記憶階層レベル間での交換のコヒーレンシー管理方法
US6240491B1 (en) 1993-07-15 2001-05-29 Bull S.A. Process and system for switching between an update and invalidate mode for each cache block
JPH07121442A (ja) * 1993-10-14 1995-05-12 Internatl Business Mach Corp <Ibm> データ処理システム及び制御方法
JPH07210461A (ja) * 1993-12-28 1995-08-11 Internatl Business Mach Corp <Ibm> ストア・イン第２レベル・キャッシュ制御装置

Also Published As

Publication number Publication date
JPH0415494B2 (enrdf_load_stackoverflow) 1992-03-18

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