JPS61285818A - Pulse circuit - Google Patents

Abstract

PURPOSE:To prevent a potential at a node point from passing through toward the power supply due to power noise by providing a means preventing a current flowing to a means charging a node boosted to a level over the power potential of a pulse circuit from flowing toward the power supply. CONSTITUTION:A diode comprising a transistor (TR) Q10 is provided between a TR Q1 and a power supply. When the level of a node A is a power supply level or over and a signal PHI1 is of the same level as the power supply, that is, in high floating state, and even when the power level is decreased due to noise, the level of the gate and drain of the TR Q10 are of the same level, then the TR Q10 is turned on and the level of the node E is not lowered. Thus, the conduction of the level of the node A toward the power supply through the TR Q1 due to turning on of the TR Q1 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse circuit including a node whose voltage is boosted to a power supply potential or higher.

[Conventional technology]

Conventionally, this type of pulse circuit has included a booster circuit to raise the gate level of the transistor higher than the power supply level in order to improve the transfer efficiency of the switching transistor or to sufficiently output a high level output. many.

FIG. 2 is a circuit diagram of a conventional example of this type of booster circuit using an N-channel type MOS dynamic circuit. The transistor QtlQ* is an N-channel MO8FET, the drain of the transistor Q1 is connected to the power supply, the source is connected to the node A, and the signal Δ is applied to the gate. The drain of the transistor Q is connected to the node A, the source is grounded, the signal zp is applied to the gate, and the signal Ω is applied to the node A via the capacitor CI.

is applied, and the voltage at node A is output to the next stage.

Signal Δp is high level, signal g! J, , e, is 0
At 17L/Bell, the node person is at Roku level. Next, when the signal zpl becomes low level and the signal z1 becomes high level, the node A becomes high level through the transistor Q. Further, when the signal becomes high level, the high level at node A is further boosted through capacitor C1, becomes higher than the power supply level, and is supplied to the next stage circuit.

Further, FIG. 3 is a circuit diagram of a clock generator as another conventional example.

When the signal 8p* is at a high level and the signal Ω is at a low level, the node R is at a high level and the nodes B and C are at a low level. When the signal Δ becomes low level and the signal bird becomes high level, node B becomes high level through transistor Q, and transistor q is turned on. Next, with a delay caused by the delay circuit 1, the node becomes a low level, and when the transistor false turns off, the level of the node C rises through the transistor q. The increase in the level at node C further increases the high level at node B via capacitor C3. If the threshold level of transistor q is To, then the level of node B is lower than the power supply level at threshold level V.
When the voltage rises by T04 or more, the level at node C becomes the same level as the power supply.

[Problem that the invention seeks to solve]

This clock generator has no means for maintaining the level of node B, and after a certain amount of time has passed, the level of node B will drop due to leakage from the PN junction connected thereto.

Then, node C becomes unable to maintain the same level as the power supply through the transistor due to the decrease in the level of node B, and enters a high-float state.

Furthermore, as the capacity and speed of semiconductor devices increase, it has become necessary to charge and discharge a large amount of charge in a short time, and the peak current and current rate of change are increasing. Therefore, noise due to inductance of wiring, etc. is also increasing.

Furthermore, in the conventional circuit C shown in Fig. 2, when the level at node A is higher than the power supply level and the level of signal Ω1 is maintained at the same level as the power supply, even if the power supply level decreases due to noise. Signal 2. The level of also decreases following the change in the power supply level, so transistor Q turns on and node A
The level does not pass through the transistor Ql toward the power supply. However, when the signal level is the same as the power supply level in a high-float state, the signal level will not change even if the power supply level decreases due to noise.
When the level of the power supply decreases due to noise and the difference between the level of the signal e and the power supply level becomes larger than the threshold level of the transistor Ql, the transistor Q is turned on and the level of the node A is shifted toward the power supply through the transistor Q1. It goes through.

As described above, a pulse circuit including a node whose voltage is boosted to a level higher than the conventional power supply level has a drawback in that a level higher than the power supply level of the node is leaked toward the power supply due to power supply noise.

[Means for solving problems]

The pulse circuit of the present invention includes means for preventing the current flowing through the means for charging the node whose voltage is boosted above the power supply potential from flowing in the direction of the power supply.

Therefore, the potential at the node once boosted above the power supply voltage is prevented from flowing toward the power supply even if the level of the power supply decreases due to noise.

〔Example〕

Next, in C2, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the pulse circuit of the present invention. In this embodiment, a transistor Q is connected between the transistor Q of the conventional example of FIG. 2 and the power supply. It is equipped with a diode made up of.

In this embodiment, when node A is above the power supply level and signal 01 is in a high-float state at the same level as the power supply, even if the power supply level decreases due to noise, the gate and drain of transistor Q1° are at the same level. , transistor Qt
0 will not turn on and the level of node E will not drop. Therefore, transistor Q1 is turned on and the level of node A does not pass through transistor Q toward the power supply.

[Effects of the Invention] As explained above, the present invention provides means for preventing the current flowing through the means for charging the node to be boosted from flowing in the direction of the power source to a voltage higher than or equal to the power supply potential of the pulse circuit. This has the effect of preventing the potential at the node from flowing toward the power supply due to power supply noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the pulse circuit of the present invention, and FIG.
The figure is a circuit diagram of a conventional example of a pulse circuit, and FIG. 3 is another conventional example, which is a circuit diagram of a clock generator. Q, , Q, , Q,.・・・・・・N channel M
O8FETC1・・・・・・・・・・・・・・・・・・
・・・Capacitor A, E・・・・・・・・・・・・・・・
・Node point Qkane Q! r Qp,...
・Signal agent Susumu Uchihara 1 party″°
;\,X,=- Figure 1 Figure 2

Claims (1)

[Claims] 1. A pulse circuit including a node whose voltage is boosted to a power supply potential or higher, comprising means for preventing current flowing through means for charging the node from flowing in the direction of the power supply.