JPS61285715A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61285715A
JPS61285715A JP12745285A JP12745285A JPS61285715A JP S61285715 A JPS61285715 A JP S61285715A JP 12745285 A JP12745285 A JP 12745285A JP 12745285 A JP12745285 A JP 12745285A JP S61285715 A JPS61285715 A JP S61285715A
Authority
JP
Japan
Prior art keywords
thin film
metal conductor
film layer
conductor thin
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12745285A
Other languages
Japanese (ja)
Inventor
Shintaro Matsuda
信太郎 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12745285A priority Critical patent/JPS61285715A/en
Publication of JPS61285715A publication Critical patent/JPS61285715A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To restrain the charge-up phenomenon, by forming previously the metal conductor thin film layer on the photoresist film for forming the source and the drain regions, and implanting ions from above this metal conductor thin film layer. CONSTITUTION:The metal conductor thin film layer 8 of tungsten and aluminum, etc. is formed previously on the photoresist film 4 to be used as the implantation mask. The source region 6 and the drain region 7 are selectively formed by the ion implantation 5 from above this metal conductor thin film layer 8. The electric charges of implanted positive ions are effectively neutralized by the secondary electrons emitted from the metal conductor thin film layer. Therefore, the charge-up of electric charge on the thin oxide film of the gate part of the silicon semiconductor substrate can be restrained, and the electrostatic breakdown, etc. can be satisfactorily prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特にイオン打
込み工程で発生する基板のチャージアップおよび静電破
壊を防止するようにした半導体装置の製造方法に係るも
のである。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device that prevents charge-up and electrostatic damage to a substrate that occurs during an ion implantation process. This is related to.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法におけるソース。 Source in conventional semiconductor device manufacturing methods.

ドレイン不純物領域形成工程時でのポリシリコンゲート
構造MO3−ICの断面を第2図に示す。
FIG. 2 shows a cross section of the polysilicon gate structure MO3-IC at the time of forming the drain impurity region.

すなわち、この第2図から明らかなように、において、
シリコン半導体基板1の主面上には、フィールド酸化M
2,2間にあって、薄い酸化113aおよびポリシリコ
ン暦3bからなるゲート部が形成されており、これらの
上にホトレジスト膜4をパターニングさせておき、従来
の方法においては、この状態でホトレジスト11!4を
マスクとするイオン打込み5により、ソース領域eおよ
びドレイン領域7を選択的に形成させるようにしている
のである。
That is, as is clear from this Figure 2, in
Field oxidation M is formed on the main surface of the silicon semiconductor substrate 1.
A gate portion consisting of thin oxide 113a and polysilicon layer 3b is formed between 2 and 2, and photoresist film 4 is patterned on top of these.In the conventional method, photoresist 11!4 is formed in this state. The source region e and the drain region 7 are selectively formed by ion implantation 5 using the mask as a mask.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このような従来例によるポリシリコンゲ
ート構造N0J−ICの製造方法にあっては。
However, in the conventional method of manufacturing N0J-IC with a polysilicon gate structure.

ソース、ドレインの不純物領域形成工程時に、そのイオ
ン打込みによって、基板上面がチャージアップされ、ソ
ース、ドレイン間に形成されているゲートの薄い酸化膜
3aに対して、静電破壊を生ずる慣れがあるという問題
点があった。
During the process of forming source and drain impurity regions, the ion implantation causes the top surface of the substrate to be charged up, causing electrostatic damage to the thin oxide film 3a of the gate formed between the source and drain. There was a problem.

そしてこのシリコン半導体基板上面に対するチャージア
ップ現象は、ソース、ドレイン領域の形成に際して打込
まれるイオンが、正イオン(例えば11a”、75AS
”)であるため、この電荷が基板上面に形成されている
それぞれの絶縁性薄膜、すなわちこへでは例えば酸化膜
、ポリシリコン層、ホトレジスト層上に帯電されるから
である。
This charge-up phenomenon on the upper surface of the silicon semiconductor substrate is caused by the fact that the ions implanted when forming the source and drain regions are positive ions (for example, 11a'', 75AS).
''), this charge is applied to each insulating thin film formed on the upper surface of the substrate, that is, for example, an oxide film, a polysilicon layer, and a photoresist layer.

従ってこの発明の目的とするところは、従来方法でのこ
のような問題点に鑑み、不純物領域形成工程時でのイオ
ン打込みに伴なう基板上面への電荷のチャージアップ現
象を抑制させて、特にゲート部に形成されている薄い酸
化膜の静電破壊を防止できるようにした半導体装置の製
造方法を提供することである。
Therefore, an object of the present invention is to suppress the charge-up phenomenon on the upper surface of the substrate that accompanies ion implantation during the impurity region forming process, and in particular, in view of the problems with the conventional method. An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent electrostatic damage to a thin oxide film formed in a gate portion.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するためにこの発明に係る半導体装置の
製造方法は、ソース、ドレイン領域形成用の打込みマス
クとなるホトレジスト膜上に、予め金属導体薄膜層を形
成させておき、この金属導体薄膜層上からイオンの打込
みを行なって、ソース、ドレイン領域を形成させるよう
にしたものである。
In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes forming a metal conductor thin film layer in advance on a photoresist film serving as an implant mask for forming source and drain regions, and Ions are implanted from above to form source and drain regions.

〔作   用〕[For production]

従ってこの発明方法においては、打込みマスクとしての
ホトレジスト膜上に、予め金属導体薄膜層を形成させて
からイオンの打込みを行なうために、イオン打込み時に
あって、この金属導体薄膜層からの二次電子放出により
、打込まれる正イオンの電荷を効果的に中和でき、これ
によって基板上面への電荷のチャージアップを抑制し得
るのである。
Therefore, in the method of the present invention, in order to perform ion implantation after forming a metal conductor thin film layer in advance on a photoresist film as an implantation mask, secondary electrons from this metal conductor thin film layer are removed during ion implantation. The discharge effectively neutralizes the charge of the implanted positive ions, thereby suppressing the build-up of charges on the upper surface of the substrate.

〔実 施 例〕〔Example〕

以下、この発明に係る半導体装置の製造方法の一実施例
につき、第1図を参照して詳細に説明する。
Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIG.

この第1図実施例方法は、前記第2図従来例方法に対応
して示したソース、ドレイン不純物領域形成工程時での
ポリシリコンゲート構造)IOS−ICの断面図である
。これらの各図中、同一符号は同一または相当部分を示
しており、この実施例方法においては、前記打込みマス
クとなるホトレジスト膜4上にあって、予め例えばタン
グステン、アルミニウムなどの金属導体薄膜層8を形成
させておき、この金属導体薄膜層8上からイオンの打込
み5を行なって、目的とするソース領域8およびドレイ
ン領域7を選択的に形成させるようにしたものである。
This embodiment method in FIG. 1 is a cross-sectional view of an IOS-IC (with a polysilicon gate structure) during the step of forming source and drain impurity regions, which is shown in correspondence with the conventional method in FIG. 2. In each of these figures, the same reference numerals indicate the same or corresponding parts. In this embodiment method, a metal conductor thin film layer 8 of tungsten, aluminum, etc. is formed, and ion implantation 5 is performed from above this metal conductor thin film layer 8 to selectively form the intended source region 8 and drain region 7.

従ってこの実施例方法の場合には、ソース、ドレイン領
域8,7の形成のために打込まれる正イオンが、金属導
体薄膜層8に衝接されると、この金属導体薄膜層8から
は二次電子が放出され、正イオンの電荷が中和されて、
このイオン打込みの際のシリコン半導体基板1上への電
荷のチャージアップを効果的に抑制でき、併せて同時に
このホトレジスト膜4上での金属導体薄膜層8の形成に
より、酸化膜ならびにシリコン半導体基板内への金属汚
染をも良好に素子し得るのである。
Therefore, in the case of this embodiment method, when the positive ions implanted for forming the source and drain regions 8 and 7 collide with the metal conductor thin film layer 8, the metal conductor thin film layer 8 emits two ions. The secondary electron is released and the charge of the positive ion is neutralized,
The charge-up on the silicon semiconductor substrate 1 during this ion implantation can be effectively suppressed, and at the same time, by forming the metal conductor thin film layer 8 on the photoresist film 4, the oxide film and the inside of the silicon semiconductor substrate can be suppressed. It is also possible to effectively prevent metal contamination on the device.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明方法によれば、ソース、ド
レイン領域の形成に先立って、打込みマスクとなるホト
レジスト膜上に、予め金属導体薄膜層を形成させておき
、この金属導体薄膜層上からイオンの打込みを行なうよ
うにして、ソース。
As detailed above, according to the method of the present invention, prior to forming the source and drain regions, a metal conductor thin film layer is formed in advance on a photoresist film serving as an implant mask, and a metal conductor thin film layer is formed on the metal conductor thin film layer. Source as if performing ion implantation.

ドレイン領域を形成させるので、打込まれる正イオンの
電荷を金属導体薄膜層からの二次電子放出により効果的
に中和できて、シリコン半導体基板の上面、ひいては特
にゲート部の薄い酸化膜への電荷のチャージアップを抑
制し得て、従来方法でのようなこのゲート部酸化膜の静
電破壊などを良好に防止できるのであり、しかも構造的
にも比較的簡単で容易に実施可能であるなどの特長を有
するものである。
Since a drain region is formed, the charge of implanted positive ions can be effectively neutralized by secondary electron emission from the metal conductor thin film layer, and the charge of positive ions can be effectively neutralized by secondary electron emission from the metal conductor thin film layer. It is possible to suppress charge build-up, effectively prevent electrostatic damage to the gate oxide film that occurs in conventional methods, and it is structurally relatively simple and can be implemented easily. It has the following features.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係る半導体装置の製造方法の一実施
例を示すソース、ドレイン不純物領域形成工程時でのポ
リシリコンゲート構造MO5−ICの断面図であり、ま
た第2図は従来例による同上ポリシリコンゲート構造M
O9−ICの断面図である。 l・・・・シリコン半導体基板、3aおよび3b・・・
・薄い酸化膜およびポリシリコン層(ゲート部)、4・
・・・ホトレジスト膜、8・・・・ソース領域、7・・
・・ドレイン領域、8・・・・金属導体薄膜層。
FIG. 1 is a cross-sectional view of a polysilicon gate structure MO5-IC during the process of forming source and drain impurity regions, showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. Same as above polysilicon gate structure M
It is a sectional view of O9-IC. l...Silicon semiconductor substrate, 3a and 3b...
・Thin oxide film and polysilicon layer (gate part), 4.
... Photoresist film, 8... Source region, 7...
...Drain region, 8...Metal conductor thin film layer.

Claims (1)

【特許請求の範囲】[Claims] ポリシリコンゲート構造の半導体装置の製造において、
ソース、ドレイン領域形成用の打込みマスクとなるホト
レジスト膜上に、予め金属導体薄膜層を形成させておき
、この金属導体薄膜層上からイオンの打込みを行なうよ
うにしたことを特徴とする半導体装置の製造方法。
In manufacturing semiconductor devices with polysilicon gate structure,
A semiconductor device characterized in that a metal conductor thin film layer is formed in advance on a photoresist film serving as an implant mask for forming source and drain regions, and ions are implanted from above the metal conductor thin film layer. Production method.
JP12745285A 1985-06-12 1985-06-12 Manufacture of semiconductor device Pending JPS61285715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12745285A JPS61285715A (en) 1985-06-12 1985-06-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12745285A JPS61285715A (en) 1985-06-12 1985-06-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61285715A true JPS61285715A (en) 1986-12-16

Family

ID=14960271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12745285A Pending JPS61285715A (en) 1985-06-12 1985-06-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61285715A (en)

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