JPS61283269A - Driving and controlling system for thermal head - Google Patents

Abstract

PURPOSE:To reduce an influence by an adjacent heating resistance and to realize an accurate multi-gradation record by driving independently the odd-number order and the even-number order of heating resistances in a thermal head used for such recordings as a thermosensitive recording, a thermal transfer recording, etc. at each different driving period. CONSTITUTION:In a thermal head 1 which is constituted by a heating resistance 1a arranged at the odd-number order position of the heating resistance and a heating resistance 1b arranged at the even-number order position of the heating resistance, the driving period against the 1a and the 1b is exclusively set within a recording period. Along with the control of driving, the intermittent feed of a recording paper is carried out within the recording period after the completion of the driving period of the heating resistance 1a of odd-number order and the heating resistance 1b of even-number order. By driving exclusively the heating resistance 1a of odd-number order and the heating resistance 1b of even-number order, a crosstalk is reduced without driving simultaneously an adjacent dot. Also, so that a driving pulse is impressed after an auxiliary pulse is impressed, it is possible to set temperature when the driving pulse is started to impress as target temperature and to improve quality in the multi- gradation recording.

Description

[Detailed Description of the Invention] [Summary] Odd-numbered and even-numbered heating resistors of a thermal head used for thermal recording, thermal transfer recording, etc. are driven in different driving periods to eliminate the influence of adjacent heating resistors. Accurate multi-tone recording is also possible with a small number of gradations.

[Industrial application field]

The present invention relates to a thermal head drive control system that can accurately control a thermal head made up of a plurality of heating resistors.

A thermal recording method in which a pulse voltage is selectively applied to the heating resistor of the thermal head according to recording information, and the temperature of the selected heating resistor is increased to color the thermal paper.The melted portion of the ink sheet is transferred to the recording paper. There is a melt transfer method for transferring, a sublimation transfer method for transferring the sublimated portion of an ink sheet onto a recording paper, and the like. In each method, it is desired to accurately control the amount of thermal energy applied to a heated object, such as thermal paper or ink sheet, heated by a thermal head to maintain constant recording quality.

[Conventional technology]

As a control method for the amount of heating (amount of thermal energy given to the heated object) in conventional thermal head drive methods, there is a method that controls the width of the drive pulse applied to the heating resistor and a method that controls the peak value of the drive pulse. There is a method. In both cases, the driving conditions largely depend on the temperature of the heating resistor at the time when the driving pulses and pulses are applied. For this reason, two methods are available to improve control accuracy: one is to determine drive conditions through complex calculations based on past drive data, and the other is to apply an auxiliary pulse during cooling after applying a drive pulse to erase the past history. There is a method to do this.

Further, the amount of heat applied from the thermal head to the object to be heated, such as thermal paper or ink sheet, largely depends on the driving state of adjacent dots, and this phenomenon is called crosstalk. The conventional thermal head driving method described above does not take crosstalk into consideration.

FIG. 12 is an explanatory diagram of a thermal transfer printer, in which an ink sheet 12 and a recording paper 13 are conveyed in the direction of the arrow between a thermal head 11 and a platen 14, and a thermal head 1
1 is driven according to recording information, ink is transferred from the ink sheet 12 to the recording paper 13 by the generated heat.

FIG. 13 is a cross-sectional view of the main parts of a general thermal head, where 13 is a protective layer, 14 is a lead wire, 15 is a resistor, and 16 is a
17 is a glaze layer, 17 is a substrate, and 18 is a heat sink, which indicates a heat generating portion. Heat storage in this thermal head is caused by the small time constant (on the order of milliseconds) due to the glaze layer 6 and the substrate 17. There is one with a large time constant (on the order of seconds to minutes) that includes up to the heat sink 18.

The driving conditions corresponding to the recording density at a dot position, which is caused by heat accumulation in the heating resistor of the thermal head, largely depend on the recording data immediately before that dot position. In other words, when performing binary recording of black/white, if the previous recorded data is black, this means that the initial temperature of the heating resistor is higher than when it is white, so when driven under the same conditions, Recording density increases.

Since this heat storage phenomenon in the heating resistor changes rapidly, it is generally impossible to perform feedback correction using a temperature sensor. is corrected. That is, if the immediately previous recorded data is black, this reduces the driving power compared to when the data is white.

For example, the drive pulse width is shortened or the drive pulse height is reduced.

When recording using a thermal head with a large time constant, when performing high-speed recording at a cycle shorter than the time constant, or when performing multi-tone recording, it is necessary to record not only the previous recorded data but also several lines. It becomes necessary to examine previously recorded data and perform correction calculations for driving conditions.

Furthermore, due to heat accumulation in the glaze layer 16, etc., the temperature of the entire thermal head may rise, or the temperature may rise locally in areas where high-density recording is concentrated. If this is done, the recording density will increase, causing fine patterns to collapse, white areas to darken, or differences in recording density to occur in the length direction of the thermal head. Since the heat accumulation phenomenon in this case is relatively slow, it can be corrected using a temperature detector or the like that detects the temperature of the substrate 17. That is, the drive power is reduced as the temperature of the substrate 17 rises. In addition, in order to compensate for the temperature distribution in the length direction of the thermal head, temperature detection is performed at multiple locations.
Correspondingly, the thermal head drive circuit is divided into a plurality of blocks, and the drive conditions for each block are controlled.

The time-temperature characteristics of the heating resistor are approximated by the following equation. However, t: time, and 1 = 0 when driving pulse is applied.
shall be. T(t): heating resistor temperature at time t, T
a: ambient temperature, τ: thermal time constant of heat storage in the heating resistor or glaze layer, twH drive pulse width, W: applied power, R: thermal resistance.

(a) When t w≦τ, When 0≦t≦tw, When tw≦t≦τ, + 'l' a When τ≦t≦τ+tw, When only t≧τ+twO, + T a ・ ・・ ・(1) (b) When t w≧τ, When 0≦t≦τ, When τ≦t≦tw, When tw≦t≦tw+τ, When t≧tw+τ, + T a ・・・ ・(2) The above-mentioned temperature characteristics are illustrated in FIG. 14.

Further, the relationship between the temperature of the heating resistor and the recording density Dc is given by the following equation.

・ ・ ・ ・(3) However, Do: saturation density, transfer constant of CiH ink, Q;
Ink transfer barrier potential, K; Boltzmann constant,
C1l is a constant related to heat transfer from the heating resistor to the ink sheet.

Regarding the effects of heat accumulation in substrates, etc., we can improve the accuracy of conventional technology (
(temperature detection system, control circuit system), it is possible to support multi-tone recording. However, as described below, it has not been possible to deal with heat accumulation in the glaze layer using conventional techniques.

The glaze layer has a spread, and there are multiple time constants for heat storage in the glaze layer. However, in conventional binary recording, high accuracy is not required for calculating the time-temperature characteristics of the heating resistor, so one time constant is sufficient, and this will be referred to as the main time constant hereinafter. The main time constant used in normal binary recording is often around 3 mS, and in multi-tone recording, a sufficiently accurate approximation value cannot be obtained with just one time constant, so it is generally several mS and several tens of mS. Two time constants of mS are used.

When performing multi-tone recording, the main time constant of the thermal head is set to 3.
mS, the driving pulse application period should be at least 100 mS.
It is known that the influence of heat accumulation in the glaze layer cannot be ignored unless the temperature is about mS. The main time constant component is (
1), (From Equation 21, it becomes less than 1O-5 at about 30 m5, so in this case, it can be seen that the time constant component of several tens of mS is extremely important. Therefore, the heat accumulation in the glaze layer is corrected. If not, the speed of multi-gradation recording will be extremely slow.Assuming the recording density is 8 dots/mm,
If the driving pulse application period is 100 m5, 0.00 m is recorded on A4 size (210 x 297 mm). IX8
It will take x297 = 237.6 seconds.

In conventional binary recording, from past driving conditions (1),
(21-2 was used to find the temperature of the heating resistor when the next drive pulse was applied, and from this the drive pulse conditions corresponding to the amount of heating were found. This calculation was complex, including exponential functions, etc., and the thermal head All heating resistors (A4
If the size is 8 dots/mm, it is necessary to perform this calculation for 1680 dots), so it is only possible under limited conditions.

FIG. 15 is a block diagram of a conventional example, in which recorded data 21
and the contents of the temperature memory 23, the pulse width determination calculation section 22
determines the pulse width, drives the thermal head 27 according to the recording pulse formed by the recording pulse width data forming section 25, and the recording pulse width data is added to the temperature prediction calculation section 24, and the contents of the temperature memory 23 and the recording pulse are The next line temperature data 26 is created from the width data, delayed by one line, stored in the temperature memory 23, and used for temperature prediction calculations for the next line. Therefore, the temporal change in temperature is simulated from the recording pattern and the applied pulse power, and the pulse width is controlled so that the temperature reached by the heating resistor is constant.

FIG. 16 is an explanatory diagram of a recording pattern, showing a checkered pattern recorded by the configuration shown in FIG.
The X mark indicates white. For this recording pattern, the predicted temperature, which is the temperature at the start of recording of the heating resistor corresponding to the X and Y coordinate positions, is as shown in FIG. Note that the height in the X-axis direction indicates the temperature. Further, the pulse width is as shown in FIG. 18, and the height in the Y-axis direction corresponds to the pulse width.

However, since it is designed to match only the temperatures reached by the heating resistors, it cannot be applied to multi-gradation recording, which requires highly accurate control of the temperature corresponding to the gradation level. Control is complicated and impractical.

When driving in consideration of past driving conditions, when binary recording is performed at a driving pulse application period of 5 mS, it is sufficient to refer to one or two past driving conditions. In this case, since the total number of possible combinations of driving conditions is eight at most, it is possible to prepare circuits corresponding to all combinations. In addition, when performing multi-gradation recording with a driving pulse application period of 10 m5 or less, if the number of gradations is as small as 4, there is little influence from past driving pulses, so even during fairly high-speed recording, the past 5 driving pulses Since it is sufficient to refer to the conditions, all possible combinations of driving conditions are 4'=409
It becomes 6. During the drive pulse application period of 10 m5, 168
When performing this calculation for 0 heating resistors, the calculation time per heating resistor is approximately 6 μs, which can be easily realized by using a read-only memory (ROM) or the like.

However, this is difficult to realize if crosstalk is taken into account.

However, if the number of gradations is 16, for example, the past 6 to l
Since it will be necessary to refer to the driving conditions about O times, and the above-mentioned combinations will be 167, it will be completely impossible to implement.

Therefore, instead of calculating the temperature of the heating resistor and finding the corresponding driving conditions, an auxiliary pulse is applied before and after applying the driving pulse so that the temperature of the heating resistor when the driving pulse is applied matches a predetermined value. We previously proposed a method for applying .

In this method, heating is performed using auxiliary pulses to adjust the time-temperature characteristics of the heating resistor to predetermined characteristics. The target time-temperature characteristic in this case must be equal to or higher than the characteristic when the maximum concentration was recorded. Hereinafter, the time-temperature characteristics at the time of maximum density recording will be the target characteristics. Furthermore, even when recording the same density, if the heating resistor temperature differs when the driving pulse is applied, the driving conditions and time-temperature characteristics will also differ. The time-temperature characteristics obtained when driving is performed twice are set as the target characteristics.

FIG. 19 shows the relationship between the drive waveform of the heating resistor and the temperature when the heat accumulation in the glaze layer is corrected under the conditions described above. (a) shows the time-temperature characteristics of the heating resistor, and the peak) shows the driving waveform. Also, (i) is the maximum density record, (ii), (
iii) is the case of density recording with the relationship (i) > (ii) > (iii), and < iv) is the case of minimum density recording (no drive pulse), with the maximum density recording being the target characteristic, and below that Also during density recording, auxiliary pulse 2 is applied to achieve the target characteristics shown by the dotted line.

When adjusting the time-temperature characteristics to the target characteristics, if the time-temperature characteristics are in the area of (1), (t≧tw+τ in equation 21, + 7' a, and substituting t=t'-tc, ・e -to”+
Ta...(5), and at any time t
If the temperature is made the same at point c, the time-temperature characteristics after point 2 will be the same. Therefore, from the start of application of the drive pulse and the auxiliary pulse, t
It is desirable to match the time-temperature characteristics after w+τ has elapsed, that is, after τ has elapsed from the end of each pulse application.

However, this condition is often not satisfied unless the recording period is at least two to three times larger than τ. In such a case, of course, only the time-temperature characteristics after τ has elapsed since the end of application of the drive pulse and auxiliary pulses 1 and 2 can be made to match the target characteristics, and there is an error in the heating resistor temperature when the drive pulse is applied. occurs. When performing high-speed recording where the recording period is smaller than τ, this error cannot be ignored, so the following measures must be taken.

The time point to match the target characteristics is set so that the error in recording density is minimized. In other words, the point in time to match the target characteristics is
If this is the point of application of the drive pulse, an error occurs between the target characteristics and the target characteristics after this point. Also, from the end of each auxiliary pulse application, τ
If the time is set after the elapse of time, an error will occur in the heating resistor temperature at the time when the drive pulse is applied. Therefore, there exists a point in time between the two when the error in recording density is minimized.

When considering the heating resistor of the thermal head as an isolated point,
The method using the auxiliary pulse described above can cancel thermal history with high precision, and can be applied to multi-gradation recording. However, in reality, there are 1680 dots of the heat generating part shown in FIG. 13 in the case of A4 size, 8 dots/mm, and even if the heat generating resistor is driven under the same conditions,
If both or one of the adjacent dots is driven, the second
As shown in Figures 0 (a), (bl, and (C)), the temperature at the start of recording (hereinafter referred to as base temperature) and the temperature during the transient portion (hereinafter referred to as differential temperature) are larger than in the case of independent driving. Note that the driving voltage is 19.07V.

The temperature at the center of the heating resistor was measured with a drive pulse width t w ='l, Q m S and a drive cycle of 10 mS. In (a) of the same figure, when both adjacent two dots are turned off, the base temperature is 87°C, the difference temperature shown in parentheses is 176°C, and the maximum temperature is 263°C. When turned on, the base temperature is 102℃
, the difference temperature was 188°C, and (C) was when both adjacent two dots were turned on, the base temperature was 118°C, and the difference temperature was 200°C.

FIG. 21 is a curve diagram for measuring the influence of adjacent dots. The driving voltage is 14.57 V, the driving cycle is 10 mS, and the temperatures at and a2 at the center of the heating resistor and the temperatures bl and b2 at the ends are set as follows. Change the pulse width from 1.5 mS to 4.5 mS
This shows the results measured when the temperature was changed to . Note that al, bl are a2.
b2 is for the case where adjacent dots are turned off. When adjacent dots are turned on, the temperature at the edges rises as well as the center temperature, and the difference between them becomes smaller; however, when the adjacent dots are turned off, the center temperature and the temperature at the edges become lower and the difference decreases. The difference becomes larger. Furthermore, the driving pulse width (
Since the center temperature and the temperature at the ends change depending on the temperature (mS), the prediction function becomes complicated and at the same time the error in the amount of heating increases.

Here, the increase in base temperature is affected by heat storage in the glaze layer I6, and the difference in temperature is caused by the protective layer 13 having high thermal conductivity.
This is due to detour from

Furthermore, there is almost no effect on the temperature difference from the heating resistor two dots apart, and the effect on the base temperature is also small.

The method of canceling thermal history using the previously proposed auxiliary pulse will be explained with reference to FIG. 22. curves, ii and iii are time-temperature characteristic curves,
When Ti is set as the target temperature and a driving pulse Pa having a pulse width Wa shown in (a) is applied to the heating resistor, the temperature of the heating resistor changes as shown by curve 1, decreases from temperature Ta, and reaches time t1. is assumed to be equal to the target temperature Ti.

(Drive pulse Pb with pulse width Wb (<Wa) shown in bl
When Tb is added, the temperature changes as shown by curve ii, and the temperature Tb
At time tb, the auxiliary pulse P with a pulse width Wbl decreases from the target temperature Ti.
By adding bl, the target temperature Ti is reached at time t1.

Furthermore, when a driving pulse Pc with a pulse width Wc shown in (C) is applied, the temperature changes as shown by curve iii, so that at time tc
When an auxiliary pulse Pcl having a pulse width Wcl is added to the temperature, the target temperature Ti is reached at time t1.

The driving pulses Pa, Pb, P, and c have a pulse width corresponding to the gradation level to be recorded, and the auxiliary pulse Pb
l and Pcl compensate for heat storage fluctuations due to changes in the gradation level, in other words, changes in the amount of heating the heating resistor is heated by the drive pulse. Therefore, the auxiliary pulse Pb1. Pc 1 will be referred to as a heating change compensation signal. These heating change compensation signals Pbl and Pcl are predetermined corresponding to the heat generation temperatures Tb and TC, and in the case of the heat generation temperature Ta, it can be understood that a compensation signal with a pulse width of zero is added. can.

FIG. 23 is a block diagram of a conventional example for realizing the above-mentioned method, in which 61 is a latch circuit, 62 is a recording signal generation circuit, 63 is a first compensation signal generation circuit, and 64 is a second compensation signal. A generating circuit, 65 is a driving circuit for a heating resistor, and 70 is a pulse width data generating circuit. The pulse width data generation circuit 70 generates pulse width data Pw corresponding to the gradation data Dn.
Output.

The pulse width data pw is latched by the latch circuit 61 by the data latch signal DL. Also, the recording signal generation circuit 6
2 is added with the pulse width data Pw from the latch circuit 61, the line timing signal LT, and the clock signal CL, and outputs a recording signal having a pulse width corresponding to the pulse width data pw.

The first compensation signal generation circuit 63 receives the pulse width data Pw from the latch circuit 61 and the line timing signal LT.
The clock signal CL and the output signal of the recording signal generation circuit 62 are applied, and a heating change compensation signal is outputted and applied to the drive circuit 65 for compensating for heat storage fluctuations in the heating resistor due to changes in the amount of heating.

The second compensation signal generation circuit 64 receives a recording start signal ST when the apparatus is started up or when a page is changed, and outputs a start-up standby temperature compensation signal, which is applied to the drive circuit 65. Drive circuit 6
5 is connected to one heating resistor of a thermal head (not shown). Therefore, the block 60 indicated by the dotted line is
In the case of a thermal head having 1680 heat generating resistors, 1680 blocks 60 are provided corresponding to one heat generating resistor.

FIG. 24 is a more detailed block diagram, in which the same reference numerals as in FIG. 71a, an OR circuit ORI, and a flip-flop 72a, and the first compensation signal generation circuit 63 includes counters 71b, 71c and an OR circuit O
R2°OR3 and flip-flop 72 b, 42 c
The second compensation signal generation circuit 64 is composed of a monostable multi-bi break 64a, and the drive circuit 6
Reference numeral 5 is composed of an OR circuit OR4 and a transistor Tr, and one heating resistor 73 in the thermal head is driven by the transistor Tr of the drive circuit 65. Further, the pulse width data generation circuit 70 is a read-only memory 70.
a, 70 b, and 70C.

In addition, R in each part is a reset terminal, D is a data terminal,
C is a clock terminal, Q and d are output terminals, A is an address terminal, DT is a data terminal, T is a trigger terminal, EN is an enable terminal, CY is a carry terminal, and L is a preset terminal.

Information corresponding to the gradation data Dn is stored in the read-only memory 7
0a, 70b, and 70c (hereinafter abbreviated as ROM). For example, the ROM 70a stores pulse width information of the recording signal, and the ROM 70b stores heating change compensation information after heating by the recording signal is completed. Time information until the start of signal application is stored, and pulse width information of the heating change compensation signal is stored in the ROM 70c.

ROM read out using gradation data Dn as an address signal
Data from 70a, 70b, and 70c are transferred to back and forth circuit sections 61a and 61, respectively, by data latch signal DL.
b, 61c.

In addition, the counters 71a, 71b, and 71c have the outputs of the latch circuits 61a, 61b, and 61c applied to the terminals DT, the line timing signal LT to the terminals, the clock signal CL to the terminal C, and the flip-flop (hereinafter referred to as FF) to the terminal EN. The outputs of the terminals Q of the terminals 72a, 72b, and 72C (abbreviated as "") are added to each, the outputs of the latch circuit sections 61a, 61b, and 61c are set by the line timing signal LT, and the count is down counted by the clock signal CL. Then, the signal from terminal CY is OR circuit ORI, OR2
, FF72a, 72b via OR3.

It is applied to the reset terminal R of 72c.

When the line timing signal LT is applied to the terminal C of the FF72a, since "1" is added to the terminal, the terminal Q becomes 1", and is applied to the gate of the transistor Tr via the OR circuit OR4, and is also applied to the counter It is applied to the terminal EN of FF71a. Also, the FF72 is applied to the terminal C of FF72b.
When a "1" output is added to the terminal d of the FF72b, the terminal Q of the FF72b becomes "1" and is added to the terminal EN of the counter 71b. Connect terminal d of FF72b to terminal C of C.
When the output of 11" is added, "1" is added to the terminal, so the terminal Q of FF72C becomes "1",
It is applied to the terminal EN of the counter 71c and also applied to the gate of the transistor Tr via the OR circuit OR4.

When the recording start signal ST is applied, a startup waiting temperature compensation signal S1 with a predetermined pulse width is output from the monostable multivibrator (hereinafter abbreviated as MM) 64a, and the OR circuit OR
4 to the gate of the transistor Tr. Since the power supply voltage vIllD is applied to the drain of the transistor Tr, a pulse is applied to the heating resistor 73 according to the output of the OR circuit OR4.

FIG. 25 shows a time chart of a conventional example, and shows an example of signals of each part in FIG. 24. Recording start signal ST
is applied, the startup waiting temperature compensation signal S1 with a pulse width WO is output from the MM64a, and the OR circuits ORI and OR
2. The FFs 72a, 72b, and 72c are reset via OR3. The startup waiting temperature compensation signal S1 is an OR circuit O
A pulse current is applied to the gate of the transistor Tr as an output signal S5 of R4, and a pulse current is supplied to the heating resistor 73 via the transistor Tr, thereby increasing the temperature. In that case, the pulse width WO is the pulse width of the heating resistor 73 at the recording start time t1.
The temperature of Ti is set so that the temperature of Ti is as described above.

Next, when the line timing signal LT is applied, the outputs of the latch circuit sections 61 a, 6 l b, 61 c are set to the counters 71 a, 7 l b, 71 c, and the signal S2 at the terminal Q of the FF 72 a becomes “ 1”
Therefore, a signal S2 of "1" is sent to the terminal EN of the counter 71a.
is added to the clock signal CL, the counter 71a receives the clock signal CL.
Start counting down according to the following. Naori Unta 7]
, b, 71c, the terminal Q of FF72b, 72c is “0”
Therefore, even if the clock signal CL is applied, no counting operation is performed.

When the content of the counter 71a becomes 0 by down-counting, a signal of "1" is output from the terminal CY, and the FF7
2a is reset. Therefore, the signal S2 from the terminal Q of the FF 72a has a pulse width W1, and this becomes a recording signal corresponding to the gradation data Dn.

When FF72a is inverted and its terminal d becomes “1”, F
F72b is inverted and the signal S3 from its terminal Q is “1”
Then, the counter 71b starts counting down.

When the content of the counter 71b becomes O, “1” is output from the terminal CY.
” signal is output, FF72 b is reset. When FF72 b is reset, its terminal d becomes “
1", the FF 72c is inverted and the signal S4 from its terminal Q becomes "1", and the counter 71c starts counting down. When the content of the counter 71c becomes 0, a signal of "1" is output from the terminal CY. is output, and the FF72C is reset.The signal S from the terminal Q of this FF72C
4 is the heating change compensation signal, and its pulse width W2
is defined by the pulse width W1 of the recording signal S2.

Therefore, a pulse current is supplied to the heating resistor 73 by the recording signal S2 of pulse width W1, and at time t2 when the next line timing signal LT is inputted by the heating change compensation signal S4 of pulse width W2, the heating resistor 73 73 is compensated so that it becomes the target temperature Ti.

The next line timing signal LT is input at time t2,
Assuming that the level of the gradation data Dn instructed at that time is lower than the level of the gradation data of the information recorded immediately before, the recording signal S2 output from F It also has a small pulse width Wll. Therefore, the temperature of the heating resistor 73 is low, and the pulse width W21 of the heating change compensation signal S4 to match the target temperature Ti is generated wider than the immediately preceding pulse width W2.

That is, the pulse width W2. The heating change compensation signal S4 of W21 compensates for heat storage fluctuations in the heating resistor caused by changes in the pulse width of the recording signal S2 applied to the heating resistor 73, in other words, changes in the amount of heating for the heating resistor. The temperature of the heating resistor at the recording start time of the recording cycle is set to a constant target temperature Ti. Note that the data latch signal DL
is input manually prior to the line timing signal LT, so the gradation data Dnp recorded on line p is
The pulse width data Pw (p) must be input before the data latch signal DL of line p-1) and output before the line timing signal of line p.

[Problem that the invention seeks to solve]

The conventional thermal head driving method and the previously proposed thermal head driving method using auxiliary pulses do not compensate for the effects of crosstalk caused by adjacent dots, so when recording multiple gradations, it is difficult to achieve the desired result. It was difficult to record gradation levels.

It is an object of the present invention to reduce crosstalk and improve the quality of 1.2-level recording, and to easily control multi-gradation recording with high precision.

[Means for solving problems]

The thermal head drive control method of the present invention will be described with reference to FIG. The drive period for the heated resistor 1b is set exclusively within the recording period. In addition to performing such drive control, the recording paper is intermittently fed within the recording period after the driving period of the odd-numbered heating resistors 1a and the even-numbered heating resistors 1b ends.

Also, a first driving period for driving the odd-numbered heating resistors 1a among the plurality of heating resistors configuring the thermal head I, a second driving period for driving the even-numbered heating resistors 1b, and a second driving period for driving the even-numbered heating resistors 1b. a first auxiliary pulse application period for applying an auxiliary pulse corresponding to the drive pulse of the first drive period of the line;
The order of the second auxiliary pulse application period in which the auxiliary pulse corresponding to the drive pulse of the second drive period of the immediately preceding line is applied is determined as follows within the recording cycle: first auxiliary pulse application period, first drive period, The second auxiliary pulse application period and the second drive period are set consecutively and exclusively, and furthermore, the second auxiliary pulse application period and the first auxiliary pulse application period of the next line are set consecutively and exclusively. In between, the recording paper is fed intermittently.

[Effect]

By exclusively driving the odd-numbered and even-numbered heating resistors, adjacent dots are not driven simultaneously, and crosstalk can be reduced. Furthermore, by intermittent feeding of the recording paper upon completion of one line of recording operation, stiffening can be prevented even when performing high-speed recording.

In addition, since the drive pulse is applied after the auxiliary pulse is applied, the temperature at the start of the drive pulse application can be set as the target temperature, making it possible to record with highly accurate density and achieve multi-gradation. The quality of recording can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 100 is a reference clock generation circuit, 110 is a frequency dividing circuit, 120 is a stage signal generation circuit, 130 is a pulse width data generation circuit, 140 is a latch circuit, and 150 is a Pulse generation circuit, 16
0 is an auxiliary pulse generation circuit, 170 is a heating resistor drive circuit, and 200 is a block.

The reference clock generation circuit 100 applies the reference clock MCK to the frequency dividing circuit 110 and the pulse generation circuit 150 when the recording start signal ST is inputted immediately after the device is started or after a page break. Recording start signal S of 1 pulse per page of page break
T is added, and the recording end signal ED for one page is added.
Accordingly, the output of the reference clock MCK is stopped.

The frequency dividing circuit 110 divides the reference clock MCK to generate a stage generation signal XPCNT and a stage generation lock X.
PCLK is output to the stage signal generation circuit 120, the data launch signal DL and the recording row identification signal Y00 are output to the latch circuit 140, and the head drive permission signal DRV is output to the stage signal generation circuit 120. It is output to the second auxiliary pulse generation circuit 160 and the heating resistor drive circuit 170.

In the stage signal generation circuit 120, the stage generation signal
Based on PCNT, a stage switching signal STCHG, a drive pulse/auxiliary pulse switching signal X5STO1, an even numbered dot/odd numbered dot switching signal X5STI, and a printing/non-printing switching signal X5ST2 are generated, and the latch circuit 140.
In the pulse width data generation circuit 130 that outputs to the pulse generation circuit 150 and the heating resistor drive circuit 170, the heating resistor positions 2i and 2i-1 (i=0
．． 1, 2, 3. ...839) gradation data Dn
(2i, p+1), Dn (2i+1.p+1)Cn is the gradation level] corresponding to the pulse width data Pw (Pw
(2i, p+1.m), Pw (2i.

p+1. s) l Pw (2i +L'p+l,
m) and Pw (consisting of 2i+1.p+1.s))
is output to the lie circuit 140.

The launch circuit 140 receives a recording start signal ST, a data latch signal DL, a reference clock MCK, and a recording row identification signal Y0.
0, drive pulse/auxiliary pulse switching signal X5STO1 Even-numbered dot/odd-numbered dot switching signal X5STI and pulse width data pw are input, and data latch signal DL is output during a period when printing/non-printing switching signal When the latch circuit 140 receives the pulse width data pw, the latch circuit 140 temporarily stores the pulse width data pw. This stored data is erased by the recording start signal ST.
When the period in which the non-printing switching signal X5ST2 is "1" ends, the printing period (XSST2="
O”).

In the printing period, the pulse width data of the auxiliary pulse for odd-numbered dots pw (2i+l, p+s) and the pulse width data of the drive pulse for odd-numbered dots Pw (2i
+1. p+1. m), pulse width data of the auxiliary pulse of even-numbered dots Pw (2t, p + 1, m),
Pulse width data Pw (
2i, p+l, m) in the pulse generating circuit 15.
Output to 0. In this pulse generation circuit 150, every time the stage switching signal 5TCHG is input, the latch circuit 1
The heating resistor drive circuit 1 takes in the pulse width data pw output from 50 and uses the reference clock MCK to generate drive pulses and auxiliary pulses with a pulse width corresponding to the pulse width data Pw.
Output to 70. It is also initialized by a recording start signal ST.

The above-described recording start signal ST is input to the second auxiliary pulse generation circuit 160 and outputs a startup standby temperature compensation signal to the heating resistor drive circuit 170. Heat generating resistor drive circuit 17
0 is connected to two adjacent heating resistors of the thermal head (not shown), and is connected to the pulse generating circuit 150.
and the drive pulse, auxiliary pulse, and start-up temperature compensation signal output from the second auxiliary pulse generation circuit 160, and the even-numbered dot/odd-numbered dot switching signal X5STI and printing/non-printing output from the stage signal generation circuit 120. The switching signal X5ST2 is input, and the printing period (X S S
At T 2+“0”), adjacent heating resistors are exclusively driven. That is, the drive signal OD for the odd-numbered heat generating resistors and the drive signal EV for the even-numbered heat generating resistors are exclusively output. Therefore, block 20
0 is provided corresponding to two heating resistors, and if the thermal heater has 1680 heating resistors, 860 blocks 200 will be provided. Also block 2
For circuit configurations other than 00, 1 regardless of the number of heating resistors.
It's good to have one.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate examples of the same signals. One recording cycle is divided into a printing period (“0”) and a non-printing period (“1”) indicated by the printing/non-printing switching signal X5ST2. The paper feed request signal RQ for intermittently feeding the recording paper is
It is formed based on the data latch signal DL output from the frequency dividing circuit 110, and is output during the non-printing period.

The printing period includes a period (“1”, period E) in which the even-numbered heating resistor of the thermal head is driven by the even-numbered dot/odd-numbered dot switching signal X5STI;
The period for driving the odd-numbered heating resistors is O”
, period O). This is hereinafter referred to as staggered drive. Furthermore, the period is 0. E is the period during which the auxiliary pulse is applied (“
0”, period S) and the period for applying the drive pulse (“1”
, period M).

The order of the period S and the period M is different from that described with reference to FIG. 22 of the conventional example with respect to the line timing signal LT. That is, in FIG. 22, period M starts in synchronization with the line timing, and period S is set immediately before the line timing of the next line. These two line timings are considered as one recording cycle, and the period is 0. In E, if the heating resistor is driven in the order of periods M and S, the time interval from the end time of auxiliary pulse application to the start of application of the next line drive pulse becomes large, and the effect as an auxiliary pulse is lost. . In that case, if the paper feeding period is further set in the same manner as in the present invention, the effect as an auxiliary pulse will become even smaller. Therefore, when performing staggered driving, it is necessary to set each period in the order shown in FIG.

In addition, in order to facilitate the generation of signals X5STO to X5ST2, a reference clock MCK having a period obtained by dividing the line period into l□Xn (which can be further simplified by setting n#100°n=2N) is used. Stage generation signal XPCNT
and generates a line timing signal LT. At this time, a decimal counter is used to generate the stage generation signal XPCNT. This causes the signals X5STI, X5ST
2 is the stage generation signal XPCNT (4-bit configuration)
It is sufficient to use one bit of the signal X5.
STO can also be generated with a simple gate circuit.

Period S of period 0 is period ■, period M of period 0
Assuming that the period is ■, the period S of the period E is the period ■, the period M of the period E is the period ■, and the non-printing period is the period ■, then ■
, ■, ■, ■, ■ are arranged exclusively and continuously within one recording cycle.

The following operations are performed in each period.

Period (2): An auxiliary pulse is applied to the odd-numbered heating resistors 1a. The pulse width data on line p is the gradation data Dn(p
-1), and the pulse width data Pw (2i+1.p-1,s
).

Period (2): A driving pulse is applied to the odd-numbered heating resistors 1a. The pulse width data of the drive pulse on the line P corresponds to the gradation data Dnp, and is the pulse width data Pw (2i+1.p, m) latched on the line (p-1).

Period ■: An auxiliary pulse is applied to the even-numbered heating resistors 1b. The pulse width data of the auxiliary pulse on line p corresponds to the gradation data Dn(p-1) recorded on line <p-1), and
-2) latched pulse width data Pw (2i,p
−1,s).

Period (2): A drive pulse is applied to the even-numbered heating resistors 1b. The pulse width data of the drive pulse on line p corresponds to the grayscale data Dnp, and is the pulse width data PW (2i, p, m) latched on line (p-1).

Period ■: Non-printing period, during which paper feed and pulse width data Pw (2i+1.p+1.m), Pw (
2i+1. p+l, s), Pw (2i, p+l, m)
, Pw (2i+p+l,s) are latched.

Furthermore, when the thermal head is driven without using the auxiliary pulse, one recording period is formed by the period (2), the period (2), and the period (2).

FIG. 4 is a block diagram of the frequency dividing circuit of the reference clock generation circuit 1. The oscillator 101 of the reference clock generation circuit 100 generates the original clock CLK, and the flip-flops (FF) 102 and 103 are used for recording. Start signal ST
Based on the recording end signal ED, the clock outputs a busy signal BSY synchronized with UY.
1 outputs the reference clock MCK only while the busy signal BSY is "1".

Further, the counter 111 of the frequency dividing circuit 110 receives the reference clock M
Stage generation lock XPCL that divides CK by 8, for example.
Output K. The counter 112 is, for example, a decimal counter, and counts the stage generation lock XPCLK.
The stage generation signals XPCNT of 4 pins a, b, c, and d are output from the output terminal Qo-Q3. Further, the most significant bit d of this stage generation signal XPCNT is output as a data latch signal DL.

Also, the busy signal BSY is applied to the data terminal of FF1.
The data latch signal DL inverted by the inverter fNVO is applied to the clock terminal C of No. 14, and the head drive enable signal DRV delayed by one line is output from the output terminal Q. Further, each time the data latch signal DL inverted by the inverter INVO rises, the FF 115 performs an inverting operation and outputs the recording row identification signal YOO.

FIG. 5 is a block diagram of the stage signal generation circuit, including NOR circuits N0R1, N0R2, NOR3 and an AND circuit AN.
D2. AND3. AND4. AND5. It is composed of AND6. Stage generation signal XPC from frequency dividing circuit
NT, stage generation lock XPCLK and head drive enable signal DRV are input, and AND circuits AND3 to AN
From D6, drive pulse/auxiliary pulse switching signal X5STO
1 Even numbered dot/odd numbered dot switching signal X5STI
, a print/non-print switching signal X5ST2, and a stage switching signal 5TCHG are output.

FIG. 6 is a block diagram of a pulse width data generation circuit and a latch circuit, and the pulse width data generation circuit 130 is a ROM
130a and 130b, which are the same as the ROMs 70a and 70c in the conventional example shown in FIG. The latch circuit 140 includes latch circuit sections 141a to 144.
a, 141b to 144b and data selector 145a to
147a, 145b to 147b, 148 and AND circuit A
ND7. It is composed of an AND8, an inverter INVI, and an exclusive OR circuit EOR1. At the current line p and during the printing period, p (p=21, 1=0.1.2, 3.
...) is an even number (YOO=10''), the launch circuit sections 141 to 144a have Pw (2i,
21. m), Pw (2t, 2N, s), P
w (2i+1.21.m) and PW (2i+1.21.m)
．． 5") is latched. Also, the latch circuit section 141b
~144b, Pw (2i, 21-1.m
), Pw (2i, 21-1, s), Pw (2i+1
, 212-1. m) and Pw (2i+1.2ffi-
1, s) is latched.

As mentioned above, the gradation data Dn of line (21-1)
The drive pulse for line (21-1) is
), but the auxiliary pulse corresponding to the same data is applied on line (2N), resulting in a double latch configuration. Note that when applied to a system that does not use auxiliary pulses, a single launch configuration may be used.

Also, two AND circuits AND7. AND8 and inverter I
The NVI controls the latch clock, and when the printing period for the current line p (p = 242) ends,
Although the data latch signal DL is input, the launch circuit section 1
Since the pulse width data used in the next line (p=2A+1>) is stored in 42a and 144a, the data launch signal DL is sent to the latch circuit sections 141b to 144b.
is input.

Data selectors 145a, 146a, 145b, 146
In b, drive pulse/auxiliary pulse switching signal X5STTO
Accordingly, one of the pulse width data of the drive pulse and the pulse width data of the auxiliary pulse is selected. Further, two data selectors 147a and 147b select one of the pulse width data of the even numbered dots and the pulse width data of the odd numbered dots in accordance with the even numbered dot/odd numbered dot switching signal X5STI. Finally, the data selector 148 selects one of the double latches based on the selection signal determined by the exclusive OR circuit EOR1,
Pulse width data Pw'' of the pulses applied during periods ① to ① in FIG. 3 is output.

FIG. 7 shows the pulse generation circuit 150 and the auxiliary pulse generation circuit 1.
60 and a drive circuit 170, the pulse generation circuit 150 includes NOR circuits N0R4, N0R5, and FF1.
51, 152, 154, and a counter 153,
The auxiliary pulse generation circuit 160 includes FFs 161, 162, M
M163, inverter INV2, NOR circuit N0R6, AND circuit AND9. The drive circuit 170 includes transistors Tri, Tr2, and AND circuit A.
ND 11 to AND 13, inverter INV3, IN
V4 and /7 circuits N0R7 and N0R8, and this drive circuit 170 drives the heating resistors 181 and 182 of the thermal head.

FF151. by the recording start signal ST. The FF154 is initialized, and every time the stage switching signal STCHG is input, the data load signal LD of the counter 153, which is 1'' for one period of the reference clock MCK, is applied to the terminal of the counter 153. The stage switching signal 5TCHG rises and the time (T) determined by the pulse width data Pw' and the period (TMCK) of the reference clock MCK
After MCKx (Pw' +1)), a carry signal is output from terminal CY.

The terminal Q of the FF 154 is set to "1" at the rise of the stage switching signal 5TCHG, and based on the recording start signal ST or the carry signal of the counter 153, the terminal Q of the FF 154 is sent to the NOR circuit N0R.
It is reset by the reset signal generated at 4.

The terminal Q output of the FF 154 is connected to the heating resistor drive circuit 17.
0 and is also input to the enable terminal E of the counter 153. As a result, the counter 153 stops counting until the next stage switching signal 5TCHG is input.

FF161. The FF162 and the NOR circuit N0R6 generate a signal that becomes "1" only during the printing period of the second line, and the inverter INV2 and the two AND circuits A
ND9. By ANDIO, the MM163 is triggered only during the auxiliary pulse application period of the second line. When triggered, the MM 163 applies a startup standby temperature compensation signal with a constant pulse width to the drive circuit 170.

The inverter INV3 and the AND circuit ANDII form a gate signal of the pulse signal, and the pulse signal collected by the NOR circuit N0R7 is opened and closed by the NOR circuit N0R8. Finally, inverter TNV4 and two AND circuits AND1
2. By AND13, adjacent heating resistors 181,1
Only one of 82 is driven.

FIG. 8 shows a time chart of the reference clock generation circuit 100, which shows a recording start signal ST, a recording end signal ED, an original clock CLK from the oscillator 101, a busy signal BSY from the FF 103, and a reference clock MCK. The reference clock MCK is output from the recording start signal ST to the recording end signal ED.

9 and 10 show time charts of the frequency dividing circuit, and FIG. 9 shows the stage generation lock XPCLK output from the counter 111 and this stage generation lock based on the recording start signal ST and reference clock MCK. rock xpc
LK and a stage generation signal XPCNT generated by the busy signal BSY. Also, Figure 10 shows
Stage generation lock XPCLK and stage generation signal X
It shows a data latch signal DL, a recording row identification signal YOO, and a head drive permission signal DRV generated by PCNT and a busy signal BSY.

FIG. 11 shows a time chart of the stage signal generation circuit 120, in which the stage generation signal XPCNT, the head drive permission signal DRV, and the drive pulse/auxiliary pulse switching signal X5
STO, even numbered dot/odd numbered dot switching signal X5
It shows the relationship between ST1, printing/non-printing switching signal X5ST2, and stage switching signal 5TCHG.

In the above embodiment, if no auxiliary pulse is used,
It is sufficient to simplify the stage signal generation circuit 120 and the latch circuit 140, omit the second auxiliary pulse generation circuit 160, and omit periods (1) and (2) in FIG.

〔Effect of the invention〕

As explained above, the present invention significantly reduces the influence of the recording pattern in the arrangement direction of the heating resistors by exclusively driving all the adjacent heating resistors of the thermal head. Therefore, it becomes possible to control the amount of heat applied from the thermal head to an object to be heated, such as thermal paper or an ink sheet, with high precision and at high speed. Therefore, there is an advantage that not only binary recording but also multi-gradation recording can be performed at high speed and with high quality. In addition, since the odd-numbered heat generating resistors 1a and the even-numbered heat generating resistors 1b are exclusively driven, this corresponds to divided drive, and the scale of the drive circuit can be reduced, and the peak of drive power can be reduced.
There is an advantage that the drive power source can be made small and inexpensive.

In addition, when applying an auxiliary pulse, as shown in Figure 3,
a first auxiliary pulse application period ■ in which an auxiliary pulse corresponding to the drive pulse of the first drive period ■ of the immediately preceding line is applied;
A second auxiliary pulse application period ■ in which an auxiliary pulse corresponding to the drive pulse of the second drive period ■ of the immediately preceding line is applied is represented by ■, ■, ■.

By applying auxiliary pulses corresponding to the drive pulses of the immediately preceding line in the order of It can be made highly accurate.

Furthermore, by feeding the recording paper within the recording cycle after the end of the first drive period and the second drive period, it is possible to prevent sticking even during high-speed recording and to perform high-quality recording. There are advantages.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
Figure 4 shows the reference clock generation circuit. A block diagram of the frequency dividing circuit, Fig. 5 is a block diagram of the stage signal generation circuit, Fig. 6 is a block diagram of the pulse width data generation circuit and latch circuit, and Fig. 7 is a block diagram of the pulse generation circuit, auxiliary pulse generation circuit, and drive circuit. The block diagram of FIG. 8 is the time chart of the reference clock generation circuit, and FIGS.
Figure 0 is a time chart of the frequency dividing circuit, Figure 11 is a time chart of the stage signal generation circuit, Figure 12 is an explanatory diagram of the thermal transfer printer, Figure 13 is a sectional view of the main parts of the thermal head, and Figure 14 is the heating resistor. Explanatory diagram of time-temperature characteristics of the body, No. 15
Figure 16 is a block diagram of a conventional example, Figure 16 is a diagram explaining recording patterns, Figure 17 is a diagram explaining predicted temperature, Figure 18 is a diagram explaining pulse width, and Figure 19 is an explanation of drive waveform and temperature of the heating resistor. Figure 20(a). (b) and (C) are influence measurement diagrams of adjacent dots, FIG. 21 is an influence measurement curve diagram of adjacent dots, FIG. 22 is an explanatory diagram of the operation of the conventional example, FIG. 23 is a block diagram of the conventional example, and FIG. The figure is a detailed block diagram of the conventional example, and FIG. 25 is a time chart of the conventional example. 1 is the thermal head, 1a is the odd heating resistor, 1b
100 is a reference clock generation circuit, 110 is a frequency dividing circuit, 120 is a stage signal generation circuit,
130 is a pulse width data generation circuit, 140 is a launch circuit, 150 is a pulse generation circuit, 160 is an auxiliary pulse generation circuit, 170 is a heating resistor drive circuit, ST is a recording start signal, ED is a recording end signal, DL is a data latch Signal, Dn
is the gradation data, YOO is the recording line identification signal, DRV is the head drive permission signal, X5STO is the drive pulse/auxiliary pulse switching signal, X5STI is the even numbered dot/odd numbered dot switching signal, X5ST2 is the printing/non-printing switching signal, 5T
CHG is a stage switching signal, OD is a drive signal for odd-numbered heat generating resistors, and E is a drive signal for even-numbered heat generating resistors.

Claims (4)

[Claims] (1) In a thermal head drive control method in which recording is performed by pulse-driving the thermal head (1), heating resistors (1
The thermal head (1) is characterized in that the driving period of each of the heating resistor (1b) arranged at an even numbered position is set exclusively within the recording period to drive the thermal head (1). Head drive control method. (2) In a thermal head drive control method in which recording is performed by pulse-driving the thermal head (1), heating resistors (1
a) and the heating resistor (1b) placed at the even numbered position are set exclusively within the recording cycle to drive the thermal head (1), and the heating resistor (1b) placed at the odd numbered position The intermittent feeding of the recording paper is carried out within a recording cycle after the end of the drive period of the heat generating resistor (1a) arranged at the even numbered position and the drive period of the heat generating resistor (1b) arranged at the even numbered position. Thermal head drive control method 1. (3) In a thermal head drive control method 1 in which recording is performed by pulse-driving the thermal head (1), heating resistors (
1a); a second driving period for driving even-numbered heating resistors (1b);
a first auxiliary pulse application period in which an auxiliary pulse corresponding to the drive pulse of the first drive period of the immediately preceding line is applied;
A second auxiliary pulse application period in which an auxiliary pulse corresponding to the drive pulse of the second drive period of the immediately preceding line is applied is set as the first auxiliary pulse application period, the first drive period, and the second auxiliary pulse application period within the recording cycle. 1. A thermal head drive control method characterized in that a second auxiliary pulse application period and a second drive period are set continuously and exclusively in this order. (4) In a thermal head drive control method in which recording is performed by pulse-driving the thermal head (1), heating resistors (1
a), a second drive period to drive the even-numbered heating resistors (1b), and an auxiliary drive pulse corresponding to the drive pulse of the first drive period of the immediately preceding line. A first auxiliary pulse application period in which a pulse is applied, and a second auxiliary pulse application period in which an auxiliary pulse corresponding to the drive pulse of the second drive period of the immediately preceding line is applied,
Continuously and exclusively set in the order of the first auxiliary pulse application period, the first drive period, the second auxiliary pulse application period, and the second drive period within the recording cycle, and the second drive period A thermal head drive control method characterized by performing intermittent feeding of recording paper between the first auxiliary pulse application period of the next line and the first auxiliary pulse application period of the next line.