JPS6128221A - Method and apparatus for oversample coding - Google Patents

Abstract

PURPOSE:To attain high accuracy of linear coding and to simplify high speed digital operation circuit by separating a forecast integration processing operated at the 1st sampling frequency into the cyclic integration processing and a non- cyclic correcting processing so as to apply non-cyclic thinning to the non-cyclic correcting processing and a band limit processing for reducing sampling frequency altogether. CONSTITUTION:The address of ROM2221-2223 is designated by an output of a counter 221 to output coefficients h17, h16, h15...h0. The correspondence between an address of each ROM and a stored coefficient is shifted mutually by M=6. An output of the ROM222i is given to an ASU (addition subtraction unit) 223i, added to an output of a register 224i or subtracted from an output of the register 224i. Whether the ASU adds or subtracts depends on a binary quantized output given through a signal line 5 from a high speed A/D converter 10. The output of the ASU223i is given to a switch 225i to change over whether it is to be fed to the register 224i or a signal line 6'.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to digital conversion of analog signals, especially simple FI
The present invention relates to a method and apparatus for oversampling encoding to obtain high-precision encoding using an A/D (analog/digital) converter.

(Prior Art) FIG. 4 shows a configuration of an oversampling encoder based on a known technique. Coding using oversampling techniques requires prediction (
A method using a predictive encoder, a method using a noise shaping encoder, and a method combining the two are known. The encoder shown in FIG. 4 is an example that uses both prediction and noise shaping functions. For the entire oversample encoding technique, see the following document (1):
The following document (2) describes a format called an interpolation type encoder that uses shuffled prediction and noise shaping.
The technical details are disclosed in .

[Reference 1] IE Transactions Association on Circuit Transactions and Systems (TEE
ETRAN8ACTIONS ON CIRCUITS
``Oversampled, Linear Predictive and Noise Shaping Coders Op Order N''
>1 (Oversearned, Linear P
rediclive and No1se -8hap
ing Coders of 0rder N > 1
) ” [Reference 2] IEE Journal Φop Solid State Circuit) (IEE
F! JOURNAL OF 5OLID-8TATF!
CIRCTJITS) SC-15, No. 6 (December 1980), pp. 1014-1021, the paper “An Intercollaborative PCM Codec with Multibreasted Digital Filters (
An Interpolatlve PCMC0DBC
wi Heavy Multiplexed Digit
al Filters)” oversampled encoder is
After coarsely quantizing the analog signal at a high sampling frequency,
It is converted into a high-precision quantized signal at the Nyquist sampling frequency by digital calculation, which simplifies the analog circuit for A/D conversion and eliminates or simplifies the analog filter before A/D conversion. There are characteristics that can be transformed into

The functions and operations of FIG. 4 will be explained below with reference to FIG. 5 as well.

Analog input signal Fi applied to signal line 1 (1
), it is assumed that the signal is a low-frequency signal with a band of /n Hz'J. This analog input signal is passed through a sampling switch 11 that operates at a sampling frequency /HCH2] much higher than the Nyquist sampling frequency 2 x /n (Hz), and becomes a sample value sequence of h [samples 7 seconds]. .Subtractor 127
' subtracts the locally decoded signal analog value on the signal line 2 from this input signal sample value and outputs an error signal on the signal line 3. This error signal is then integrated by a noise shaping integrator 13. A subtracter 14 subtracts the local decoded signal analog value on the signal line 2 from the integrator output and outputs it on the signal a4. Signal $
The signal on the signal line 4 is judged to be positive or negative in the binary signifier 15, and if it is positive, +△ is output to the signal line 5, and if it is negative, -△ is output to the signal line 5. This binary quantized output is integrated by a predictive integrator 16 and outputs a locally decoded signal digital value onto a signal line Z. This local decoded signal digital value is passed through a D/A converter 17 to be output as a local decoded signal analog value. Integrator 13
and Ilj, and the sampling interval is T=1//H [seconds] Z
= exp(sT), then 1/(
1-z-1) and 2"-'7/(1-Z""1), and the adders 131, 161 and 1
A sample time delay circuit 132°162KX is realized.

Z converter for analog input signal sample value series X (Z)
, let y (z) be the Z transform of the locally decoded signal sequence, and let Q (Z) be the Z transform of the quantization noise sequence added additively in the binary quantizer, then in the circuit of Fig. 4, Y(Z)=
Z-1-X(Z)+ (1-Z-') Z-' Q(Z
) fil relationship is derived. Since z-1 simply has a delay of one sample, if this is ignored, the locally decoded signal Y
It can be seen that (Z) contains the input signal X (Z) as it is, and the quantization noise of the binary quantizer is multiplied by (1-Z-'). FIG. 5(2) shows a simulated sub-Fram of the locally decoded signal y(z). The frequency of (1-z-') is (1-exp(-
jωT)) and its amplitude characteristic is 5in2! ! , the quantization noise tends to be pushed out of the signal band. This shaping of the noise characteristics is due to the effect of the noise shaping integrator 13. If the output of the subtracter 12 is input directly to the binary quantizer 15 and the noise shaping integrator is not used, Y(Z )=Z″” −X(Z)+Z−′ −Q(Z
), the effect of pushing the quantization noise out of the signal band is significant. This is a configuration called a first-order predictive encoder.

Next, it is necessary to convert the encoded signal of 7 seconds obtained on the signal line 2' into a signal of the Nyquist sampling frequency/8=2.times.H. fs-71 (if the relationship f1□=Kxfs is selected as an integer ratio, the conversion of the sampling frequency is a thinning operation that extracts one sample from each successive sample of a signal of 9 [samples 7 seconds]). However, before this decimation operation, it is necessary to pass the signal through a digital filter for the following two purposes.The first purpose of using a digital filter is to limit the signal band.

Normally, when performing A/D conversion, the analog input signal is band-limited to 1/2 or less of the sampling frequency to prevent aliasing distortion due to sampling. In oversampling encoding, the first sampling is performed at a very high frequency, so an analog filter before A/D conversion may be unnecessary, or it may be extremely simple. Accurate band limiting to /B (ITZ) can be done after digitization. As a result, the analog signal to be encoded is not necessarily /n (Hz)
Even if the band is limited as follows, it is possible to eliminate aliasing distortion when it is finally converted into a 7g (7 second sample) digital signal.

The second purpose of using digital filters is to reduce quantization noise. The quantization noise included in the local decoded signal 4 Y (Z) is distributed over the entire band as shown in FIG. 5 (2) K,
Moreover, due to the noise shaping effect, there is a large deviation outside the signal band. If the thinning operation is performed in this state, quantization noise outside the signal band will fall into the signal band.

If the band is limited to fs([1zJ) before the thinning operation, most of the quantization noise will be removed, so the quantization noise after the thinning operation will be slightly reduced.The signal-to-noise ratio (8/N) will be improved.

Digital FIR filter 18, resampling switch 19, digital IIR filter 20 . and a resampling switch 21 are used for the above purpose. Instead of directly reducing the speed of the signal of /H [sample 7 seconds] to fsC samples/second], in Fig. 4, a two-step sampling rate reduction method is used in which the sampling rate of -tan [sample 7 seconds] is passed through the middle. is used.

is chosen such that /H>fM>/a, and both /Hz--M and /M/fs=N take integer values.

The role of the digital F'l'R filter 18 is % (sample 7
Before reducing the sampling rate of the signal to [seconds], quantization noise components around frequencies that are integral multiples of 7M are removed in advance. The characteristics of this filter need only be as shown in FIG. 5(3), and can be easily realized as an FIR filter. Re-sampling switch 1 for output of digital FIR filter 18
9 to a speed of 7M (sample 7 seconds), the spectrum of the digital signal after thinning has repetitions every 7M (H2), as shown in Figure 5 (4).The noise within the signal band is the same as before thinning. However, the noise outside the signal band is increased because the quantization noise in the portion where the attenuation amount of the digital FIR filter 18 is slightly lower is folded back and superimposed.

To keep the required order of the FIR filter small, monotonic decay within the signal band may be allowed. This is due to the fact that the spectrum of the signal component in FIG. 5 (4) is not drawn as flat.

Digital IIR filter zo#'i/u (sample 7 seconds)
It is a low-pass filter with a band width of /n (Hz) that operates at a sampling frequency of , and achieves the characteristics shown in FIG. 5(5)K.

Digital IIR filter 20#-i, digital FI
Together with the R filter 18, it is designed so that the signal band characteristics are flat. When passed through this filter, more than 9 fbi
-/B (H2) Signal components and quantization noise components are sufficiently attenuated. Therefore, when the output of this filter is passed through the resampling switch 21 and converted into an fsC sample 7 seconds times multiple, a spectrum K as shown in FIG. 5(6)K is obtained.

FIG. 6 shows an example of the configuration of the digital FIR filter 18. The signal given to the signal line 2' is sent to the one-sample delay circuit 81.
．． , 81. , . . . , 81M are sequentially delayed one sample at a time. Multiplier 82
°, 82. ,..., coefficient h6+ h++ by 82L
..., hL, and the multiplication result is sent to the adder 83. , 83
．． , . . . , 83L and outputs the result to the signal line 6. Sequence of coefficients (hOp”I+...+hr,)
is the impulse response of this filter, and the Z transformation wheel Z)-ΣhiZ~i of this impulse response is a system function of the filter where i=Q. It consists only of acyclic terms and has a cyclic term. Its frequency change H(e j”)−
It is given by Σhle−Jmoe.

I-0 7th drawing digital 1I11. 3 is an example of a general force configuration of the filter 20. An operation determined by a system function is performed on the signal applied to the signal line 7, and the result is outputted to the signal line 8. In the above formula, z-Ml, j sampling period is 1//
It corresponds to t7 that M=M·(]//u).

The input signal on the signal line 7 is not changed and is input to the multiplier 91o by a constant a.
After being multiplied by ol, the multiplier 91. ．． 912. Add (decrease)
Calculator 92. , 92. , and delay circuit 93. , 93
．． Due to the feedback loop consisting of
K corresponding cyclic term operations are performed, and then multiplier 91 .
, 914 and the adder (subtractor) 92, . 92. The circuit consisting of (1-+-a, , Z-cho a2.Z-BO) performs the operation of the acyclic term corresponding to BO.
If the order is higher than the following, the same denominator/numerator quadratic sections as above may be connected vertically and shifted.

(Problems with the Prior Art) As explained above with respect to the Overjanzor encoder shown in Fig. 4, it is possible to perform coarse quantization A/D conversion using analog borrowing at a sampling frequency much higher than the signal band. After that, digital band-limiting and sampling rate reduction provide a highly accurate quantized encoded output. The analog parts required to realize this circuit are a low-resolution D/A converter, an integrator, etc., and especially a quantizer and a polarity comparator for the Vi2 value. Everything else is realized by digital circuits. Therefore, it is possible to realize a high precision & A/D converter without being affected by noise contamination or element deviation.

Furthermore, digital circuits are more suitable than analog circuits for LSI, especially for VT and 81, where microfabrication will become more and more advanced in the future.

Therefore, such a coverover sample encoder is T,SI
/Vl, ST It is consistent with the development trend of nuclear technology, and there is no doubt that its importance will increase in the future.

However, even if LSI, VT, and SI technology are implemented, it will be necessary to simplify analog circuits (and digital circuits as well) in order to reduce chip area, power consumption, and cost. It is necessary to reduce the number of calculations per unit time and to simplify the required calculations themselves. To this end, it is desirable that the arithmetic unit that operates at a high sampling frequency be functionally simplified as much as possible, and that the complex processing be performed at a low sampling frequency.

In the example of FIG. 4, the predictive integrator 16 and the digital F
IR and filter 18 are high-speed calculation units. Since the predictive integrator 16 has a function of simply accumulating the output (±△) of the binary quantizer 5, it can be easily realized by a so-called up-down counter (reversible counter). On the other hand, the digital FIR filter 18 generally has the configuration shown in FIG. 6 and includes a multiplier, making the circuit complex.

In the conventional example shown in Document 2, an accumulator is used that simply adds input M (=/H//M) times in order to avoid complicating the circuit. This corresponds to setting T to M in the FIR filter in Fig. 6, and setting all coefficients (1=O~!, ) to 1, which is around an integer multiple of fM(nz). The attenuation of the frequencies is not always sufficient and strong, and the proportion of quantization noise mixed into the signal band becomes large due to thinning. The conventional example is a nonlinear PC known as μ law or ViA law.
Since the application purpose was to encode to M code, the D/A converter 17 is given non-linearity or weight, so that the quantization is made coarser in places where the signal amplitude is thicker and finer in places where the signal amplitude is thicker. The use of the above-mentioned simple & FIR filter is possible due to the fact that the quantized shoe sound generation value itself at the time of amplitude can be suppressed to a low value, and that the final required precision can be 13-bit linear coding. It was possible.

However, if the signal passing within the signal band is not just a single audio signal, but two or more types of audio signals or data signals that are used for band division, the occurrence of cross modulation due to nonlinear distortion can be suppressed to a minimum. High precision linear encoding is required. The required accuracy exceeds 13 bits,
Increasingly, 14 to 16 bits are required.

On the other hand, in order to improve the ease of circuit implementation and to suppress the increase in power consumption, the sampling frequency /n (llz″
J-η If you don't keep it as low as possible, it won't work. In applications where such conditions are imposed, the digital FIR filter 1
8Fi is a simple accumulator, and it is useless unless it can take the coefficient value of the appointed official. If the coefficient value is 1 or other than 1, but is not a power of 2, multiplication is required and the circuit becomes complicated. Therefore, the cost increases, the size increases, and the power consumption increases. Further, when linear encoding is required, it is difficult to achieve high precision by using a simple accumulator as an FIR filter. These are the drawbacks of the conventional method.

(Objective of the Invention) The present invention improves the drawbacks of the conventional method, and uses oversampling encoding that can significantly reduce the overall circuit complexity while providing the digital FiR filter with desirable attenuation characteristics. A method and apparatus are provided.

A first object of the present invention is to provide a method and decoupling method for Mevazanzor encoding that can also realize high-precision force linear encoding.

A second object of the present invention is to provide an oversample encoding method and apparatus that can simplify a high-speed digital operator circuit.

A third object of the present invention is to provide an oversampling encoding method and equipment that can be implemented in an LSI, and can be reduced in cost, size, and power consumption.

A fourth object of the present invention is to determine whether to use a digital circuit or an analog circuit when realizing a predictive integrator, and accordingly, it is necessary to use a multi-bit (mulHbit) D
An object of the present invention is to provide a method and apparatus for encoding using an oversample technique, which allows the selection of whether the use of a /A converter is necessary or unnecessary to be left to a circuit designer, separated from the system decision.

(Structure of the Invention) According to the present invention, A/D conversion is performed by performing at least first-order predictive integration processing and performing binary quantization at a first sampling frequency higher than the Nygist frequency. An oversampling encoding method for obtaining a high-precision code sequence from a binary output from the A/D at a second sampling frequency that is 1/N (N is an integer) of the first sampling frequency, the method comprising: A predictive integration process that operates at one sampling frequency is separated into a cyclic integration process that operates at a second sampling frequency and an acyclic correction process that operates at the first sampling frequency, and the acyclic correction process The processing and the band limiting process for reducing the sampling frequency are integrated as an acyclic thinning process, and the acyclic thinning process is performed using k×N taps, where the number of taps is k (an integer) times the N. According to the binary output from the A, /D conversion, Kk sets are accumulated in an additive or subtractive manner, and the accumulation result of 1 is outputted at the first sampling frequency. Oversampling is performed by increasing every N sample points, and the high-precision code sequence is obtained by performing the cyclic integral processing on the signal subjected to the acyclic thinning processing. method is obtained.

Further, according to the present invention, there is provided an A/D converter that includes at least a first-order predictive integrator and performs binary quantization at a sampling frequency higher than the Nyquist sampling frequency; a plurality of sets of accumulators whose additions and subtractions are controlled in accordance with value conversion outputs; a read-only memory that supplies pre-subtracted and accumulated data to the plurality of accumulators; and said plurality of accumulators. The device is characterized in that it is configured by itself with a switch that sequentially extracts all accumulated outputs and clears the accumulated value to O, and an integrator that integrates the outputs of the plurality of sets of accumulators obtained from the switch. An oversampled encoding device is obtained.

(Operation/Principle of the Present Invention) The present invention substantially eliminates the need for multiplication required to reduce the sampling speed by limiting the input of the digital F/R filter to two values of ±1. In a digital encoder having a prediction function, it is necessary to use the signal before the prediction integrator in order to convert the input of the digital FIR filter into a binary value.

Z converter of the output signal of the binary cup/child converter 15, W (Z+
According to the definition of each part signal mentioned above, W(2,)=(1-Z-')X(Z)+(1-Z''''S2Q(Zl) . Therefore, from this signal
In order to obtain the encoded value of (Z), it is necessary to multiply the value by 1/(1-Z) in the process of reducing the sampling speed. This is no different from extracting a signal from the output of the predictive integrator 16, and it is equivalent to making the input of the digital FIR filter for reducing the sampling rate into a binary value of ":1".Therefore, after the digital FIR filter, It is conceivable to perform the calculation 1/(1-Z-〇).In this way, the digital F
The input of the IR filter is only ±1, so there is no need for multiplication, but instead, all calculations of the filter are performed using fl ([sample 7 seconds]
Therefore, we cannot expect to reduce the amount of computation in this part by reducing the speed to 7 seconds.

Furthermore, in the present invention, the predictive integration function to be included in the sampling rate conversion process is realized with a two-stage configuration of a high-speed acyclic part and a low-speed cyclic part, and the high-speed acyclic part is used as a digital F for reducing the sampling rate.
By combining it with the IR filter, calculations in the high-speed section are simplified. Therefore, the present invention has 1
/(1-Z-Use the fact that the transfer function of the integrator with the force can be transformed as shown on the right-hand side of equation (1).The right-hand side of equation (1) is a polynomial in Z-1, Specimen/Specimen 7 movement]
M-tap digital FIR filter (acyclic term)
It is. On the other hand, equation (1) is a polynomial with the denominator term Z-" on the right side, and its reciprocal, 1/(1-Z-M), is /H
The transfer function pressure of the integrator whose sampling frequency is /M-n is equal to the cyclic term. Therefore, operation 1 of this cyclic term
/(1-Z-Town /MC the signal sequence of /H (sample 7 seconds)
This can be done after the MC specimen has been reduced by 7 mm.

Furthermore, by convolving the molecules on the right side of equation (1) with the transfer function of the digital FIR filter 18 for reducing the sampling rate shown in FIG. 4 in advance, it can be reconstructed as a single digital FIR filter. Digital FIR in Figure 4
When the glue length of the filter 18 is (L+1), M
By convolving with the right-hand side molecules of equation (1) corresponding to the filter of taps, a composite digital FIR filter of (M+I,) taps is obtained. Therefore, the output of the binary filter 15 is passed through this synthetic digital FIR filter to reduce the sampling rate to /M (sampling time: 7 seconds), and then the sampling rate is reduced to 1/(1-Z-M).
7! The fourth
The same signal obtained on signal line 7 in the configuration shown in the figure is obtained on signal line 7 in FIG.

In the present invention, the number of taps (M+L) of the synthetic digital FIR filter is further determined by the sampling frequency thinning ratio/H//
Select so that M = an integer multiple of M. That is, this means that the tap length (L+1) of the digital FIR filter 18 for sampling frequency thinning is designed to be an integral multiple of M. The number of taps (M+L) here has a coefficient value;
It may contain a tap of 0 and it may be an edge. The coefficients of such a composite digital FIR filter with (M+L) taps are h(0), h(1), ..., h
(M+L-1), and the input signal sequence is x(n),
If the filter output is y(n), the output y(nl is given by the following equation by convolution of the input x(n) and the filter's impulse response h(n).

Since this filter output is decimated by 17MK, it becomes y(n)': There is no need to calculate for all n, but every M value of n, that is, y(01, y(goods), y
(2M).

..., y (mM), ... can be calculated. Here, if mm=M+L, it is shown that y(0) and y(mM) can be calculated by the same hardware. The required force input sample value to find y(0) is X(→f−L
+1).

x(-M-L+2), ... #X(-1), value O) of (
It can be seen from equation (2) that there are M+T,). Similarly y
(mM)'f = required hiko input sample value to find x(tl
, x(21* ...* x (M+L) of (M
+L), and these two sets of input sample values overlap and are continuous. Therefore, if there is hardware that calculates the sum of products of (M+L) terms as shown in equation (2), y(o) can be obtained by repeatedly using it.

y(rrM), y(2mM), - can be calculated. Other y (goods).

y(M+mM), y(M+2mM), -yay(2M)*
y(2M+mM).

. . . Since it is also necessary to find the second grade, it is sufficient to use a total of m sets of product-sum calculation hardware and synthesize the outputs of these. As mentioned above, since it is a binary value of x (nld officer △), △=1
By considering this, the product-sum calculation in equation (2) can be replaced with simple accumulation.

(Embodiment) FIG. 1 shows an embodiment of the present invention based on the above-mentioned principle. Reference numerals 1, 5, 7, 8, 9, 20°21 in FIG. 1 correspond to the same numerals in FIG. 4 and have a similar childish feel.

In addition, the high-speed A/D converter 10 in FIG. 1 has l' in FIG. Subtractor 1
2.14. Sampling rate converter 22 has the above-mentioned (M+L) tap synthesis digital filter function and 111 [sample 7 seconds] [sample 7 seconds]
It also has the function of a resampling switch that performs sampling frequency conversion to
read-only memory) 222, , 222□, 222. ,
ASU (addition/subtraction unit) 223□.

2232, 223. , register (one sample time delay circuit) 224, , 224, 224. , switch 2
It is composed of 251, 2252, and 2253.

The ROM 2221 (i=1.2.3) stores filter coefficients of (M+L) taps.

The ASU 223i, the register 2241, and the switch 2251 (i=1, 2.3) constitute an accumulation circuit, and the ROM 222. Accumulate the output of Here (M+
An example in which three sets of accumulation circuits are used is shown assuming that L)=3XM.

The entire operation of FIG. 1 will be explained with reference to FIG.

The signal line 220 has a 7'H (bit/bit) signal as shown in FIG. 2 (1).
seconds] clock pulse is applied, and the frequency is divided by (M+L) by the counter 221. Figure 2 (2) shows (M+L)
-18, the count value of the counter 221 is 0, 1, 2 .・・・
・, 17 were shown. ROM 222. , 2222.22
2. is addressed by the output of counter 221,
Coefficient h17 e h16 + of synthetic digital filter
"11..., outputs ho.

The correspondence between each ROM address and storage coefficient is M(-6
). That is, when n0M222+ outputs ho, ROM 222. is ho, also ROM2
ROM 222.222 outputs ho. Gaho
, K ROM 222s is included. When outputting R
OM 222. outputs "he'f". Figure 2 (3) ~
(5) shows this relationship.

It corresponds to the subscript k of the numbers Fihk in FIG. 2 (3) to (5).

ROM 222. The output of A 8 TJ (addition/subtraction unit) 2231K is added to the output of register 2241 or subtracted from the output of register 224I.

FIG. 2 (6) to (8) show the output of the register 224i. 1'10 When the output of M222i is hay, register 2
The output of 241 is always 0. Should it be added using ALU?
Whether or not to perform subtraction is determined by the binary quantized output provided from the high-speed A/D converter 10 through the signal line 5. 2
The output of the value quantizer 15 (see FIG. 4) is shown in FIG. 2 (9) K.
As shown, it is binary (±Δ), and when +△, it is added, and -
When Δ, subtraction is performed. ASU (addition/subtraction unit)
223. The output of is given to the switch 2251, which supplies the output to the register 224i, or the signal line 6'
Switches whether to supply output to.

Figure 2 00~(121 is switch 2251~2253
This indicates the operating status of the register 224I when @1”.
10'' on the side indicates that it is connected to the signal line 6' side. When outputting the ROM 2221, the corresponding switch 2251 is connected to the signal line 6' side. Therefore, at this time, the register 224I has a value of 0. is input, so the next time slot is l (, OM 222. is hl
? At the time of outputting , the register 2241 often outputs 0. After all, ROM222. , A 8 U
223. , the circuit consisting of the register 2241 and the switch 2251 is Jη・x (n-17) +h(t@-x
(n-16)+-+h(0)・x(nl operation (18
(sum of products of terms) in rows and outputs the result on signal line 6'. However, x(n-k) is a binary signal given on the signal line 5, and is handled as ±IK standardized on the circuit. The above calculation is the same as Equation (2), and as described above, all necessary calculation processing can be performed by three sets of force circuits. Figure 2 (0) shows the combined output from the three sets of circuits that is obtained on the signal line 6'.

The output of 7M (sample 7 seconds) obtained on the signal line 6' is then given to the digital integrator 23.
3 performs the calculation of 1/(1-Z-') in equation (1), and includes an adder 231 and a delay circuit 2 of t/fy (seconds).
It is composed of a 32° multiplier 233. This multiplier multiplies the coefficient α by 233 times, and has the function of setting the transfer function of the signal lines 6' to 7 to 1/(1-αz −M). When .alpha.-1, the input 11 to the digital filter 20 has the same power in principle in both the configurations shown in FIG. 1 and FIG. 4. However, it is generally desirable to set the value of α to be slightly smaller than 1. This is because when α=1, the influence of the initial value in the delay circuit 232 remains forever. If α is set to a value slightly smaller than 1, the influence of the initial value becomes smaller over time and becomes negligible. The effect of α=1 on the characteristics is first effective as the integral characteristics are affected in the low frequency region near DC. 1. Taking a telephone signal as an example, the passband is 300Hz to 3400Hz, so it is normal that very low frequency regions are rarely included in the signal band, so even if the integral characteristic is lost in the low frequency region, This is problematic.Also, the numerator term on the right side of equation (1) is 1+αz−1+α”Z−2+−0,+α(M−1)7.
-(M-1) and 1+Z""+Z"-+-...+
If we leave it as is, fM (
The transmission zero at a frequency that is an integer multiple of Hz] is 1/(1-α
However, this effect is not completely canceled by the pole of fpt
It mainly occurs near integer multiples of [r], and has almost no effect on the integral characteristics at frequencies within the signal band.

By choosing α-1-2-m (m is an integer), the multiplication of α can be easily expressed as 'p by digit shifting and subtraction of binary codes. When the order of the digital filter 2° is full order, the first-order factor and the transfer function 1/(1-αZ″′M) of the digital integrator are combined to form a set of 2
It is also possible to configure it as the next section.

By overlapping the above description of the sampling rate converter 22 and digital integrator 23 with the description of the conventional configuration shown in FIG. It is clear that the result can be obtained by high-precision encoding.

By the way, the sampling rate converter 22 shown in FIG. 1 can be modified in various ways within the range of ordinary circuit techniques.

For example, as shown in FIG. 3, it is also possible to use one ROM and one A 8 U (addition/subtraction unit). In Fig. 3, ROM 222o counter (CT) 22
The count value in Figure 3B (5) obtained by dividing the /H (bits/second) clock pulse (Figure 3B (1)) by (M + L) through 1° is given as an address. ×／
1. The count value shown in FIG. 3B (4) obtained by dividing the frequency of the [bit/second] clock by three is also given as an address. Therefore, the output of 110 M2220 is (3X/H)
-' changes every second and outputs the filter coefficient hk as shown in FIG. 3B (6). In short, the ROM 222 in FIG.
, 2222°222, is equivalent to time division multiplexing of the outputs.

The address capacity of the ROM 222o is 3X(M+L) words, and the address capacity of the ROM 222o in FIG. , 222.
, 222. is equal to the sum of the capacities of multiple ROMs.
Since there is only one, the circuit is simplified. ROM 22
The same result can be obtained by using a capacity 'i(M+L) word with a capacity of 2o, and instead preparing three sets of address generation circuits, time-division multiplexing the three sets of address signals, and thereby specifying the address of the ROM222o. can get.

A 8 U (Addition/subtraction unit 1.) 233. So 110
M222. output and the switch 22 shown in Figure 3B (7)
The output from 5o is added or subtracted according to the binary digitization signal on signal line 5-. The binary quantized signal on the signal line 5 is /H (sample 7 seconds) as shown in FIG. 3B(8) and is constant for three time slots.A S tJ 223
The output of o changes every 3 x hθ-1 seconds as shown in Figure 3B (9).The required K A 8 U 223n ld 1
The operation of A8U223+, 2232-2233 in the figure is realized by time division multiplexing.

The output of A 8 U223o is the three-phase clock pulse (1) shown in FIG. 3B (bits/second).

(2), (3) register (RF G)
2263.2261.

226, will be read more. Each register holds its data for /I71 seconds. The data retained is gross),
(Gl 227. ((Through this, the direction is output to the switch 225o.

Each gate receives timing signals (1), (2), (
31 is conductive only when it is 11", so the output of each register is time-division multiplexed through the gate. Switch 225
o is I (0M222o outputs b+yk only when timing buffer (Bl falls to 228 side A S U2
Output to 23o is OK.

In the timing buffer (B) 228, the time position of the input data fluctuates within ±(3x fH')-'CtJ)'J, so the fluctuation is absorbed and leveled and the input data is sent to the signal line 6'.
The sampling speed converter 22 shown in FIG. 3 described above is similar to the sampling speed converter 22 shown in FIG. The functions are exactly the same.

(Effects of the Invention) According to the present invention, the sampling speed can be reduced without requiring complicated multiplication operations, regardless of the required filter characteristics. As shown in the explanation of FIG. 5, it is also possible to use a two-step sampling rate reduction, but from
It is also possible to directly reduce the sampling speed to (sampling time: 7 seconds). In that case, the range from 0 to about /B (FIZ) is considered to be within the band, and the range from about fIl [■Z] or more is considered to be outside the band, and the in-band gain is FI whose deviation is sufficiently small and out-of-band attenuation is sufficiently large.
R filter is required. In this way, the number of taps of the FIR filter is very large and the coefficients are simple, making it powerful.
Even in that case, according to the present invention, no multiplication is necessary, and it is sufficient to perform additions (□□□ operations) corresponding to the number of taps in 1/f8 [seconds].

In the present invention, when reducing the sampling rate, arbitrary filter characteristics for compressing quantization noise outside the signal band can be realized without increasing the circuit burden. Realization [7 obtained.

Furthermore, in the present invention, since the high-speed digital arithmetic circuit is extremely simplified, it is easy to implement LaI, and as a result, a low-cost, small-sized, and low-power encoder can be realized.

Furthermore, in the present invention, the predictive integrator 16 included in the feedback loop of A/D conversion does not necessarily need to be realized digitally, and by replacing it with an analog integrator, the D/human converter 17 can be made unnecessary. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram explaining the operation of the sampling rate converter shown in FIG. 1, and FIG. 3 is a diagram showing another example of the sampling rate converter used in the present invention. This is a configuration example. Fig. 4 is a diagram showing a configuration example of an oversample encoder based on a known technique, Fig. 5 is a diagram explaining the principle and operation of oversample encoding technology, and Figs. 2 is a diagram showing an example of the configuration of a digital FIR filter and a digital IIR filter used in an encoder. FIG. In the figure, a high-speed A/D converter with a 10-digit prediction function, 22 a sampling rate converter, 23 a digital integrator, 201t digital IIR filter, 2111 resampling switch, 221 #'i counter , 222t~2
22, ROM (read-only memory), 223. ~22
33 is an addition/subtraction unit), 224. 2243 is a unit delay circuit. G floor O 5 Figure OfM27M O 6 Figure Of,''t!Ts

Claims (2)

[Claims] (1) Perform A/D conversion by performing at least first-order predictive integration processing and binary quantization at a first sampling frequency higher than the Nyquist frequency, and convert the binary output from the A/D into the An oversampling encoding method for obtaining a high-precision code sequence at a second sampling frequency of 1/N (N is an integer) of the first sampling frequency, the method comprising predictive integration processing operating at the first sampling frequency. is separated into a cyclic integral process that operates at the second sampling frequency and an acyclic correction process that operates at the first sampling frequency, and the acyclic correction process and the band limit for reducing the sampling frequency. The processing is integrated as an acyclic thinning process, and the acyclic thinning process is k×N, where the number of taps is k (an integer) times the N.
Accumulation of k sets is performed additively or subtractively according to the binary outputs of the A/D conversions, and the cumulative results of the k sets are output at the first sampling frequency. An oversampling encoding method, characterized in that the high-precision code sequence is obtained by extracting every N sample points, and performing the cyclic integral processing on the signal subjected to the acyclic thinning processing. (2) An A/D converter that includes at least a first-order predictive integrator and performs binary quantization at a sampling frequency higher than the Nyquist sampling frequency, and an A/D converter that performs addition and subtraction according to the binary quantization output of the A/D converter. a plurality of controlled accumulators; a read-only memory that supplies data calculated and accumulated in advance to the plurality of accumulators; and a read-only memory that sequentially extracts and accumulates accumulated output from the plurality of accumulators. 1. An oversampling encoding device comprising: a switch that clears a calculated value to 0; and an integrator that integrates outputs of the plurality of accumulators obtained from the switch.