JPS61281653A - Frequency synthesizing device - Google Patents

Abstract

PURPOSE:To obtain a phase continuous output signal by using an orthogonal modulator and synthesizing the frequency. CONSTITUTION:A clock signal Ick supplied to an input terminal 2 is phase-shifted to 90 deg. by a phase-shifter 10, and the clock signal Ick itself, the clock signal Ick phase-shifted to 90 deg. by the phase-shifter 10, an output analog signal from a digital/analog converting device (DAC) 8 and an output analog signal from a digital/analog converting device (DAC) 9 are all supplied to an orthogonal modulator 11, and as a carrier, the clock signal Ick and the clock signal Ick phase-shifted to 90 deg. are synthesized after the amplitude modulation is executed by the output signal from digital/analog converting devices (DAC) 8 and 9, and outputted from an output terminal 12. By using the orthogonal modulator 11, for an output clock signal Ock, the phase is continuous and the frequency can be changed little by little, and even when an input signal Ick is changed over to synthesize the frequency from the condition that the input signal Ick is a clock signal, the output clock signal Ock, in which the phase is continuous, can be obtained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a frequency synthesizer used in a decoder, etc., which separates signals obtained by time-division multiplexing multiple channels of information signals with different transmission lock signal frequencies. In particular, the present invention relates to a frequency synthesizer that initially maintains the phase and frequency of an input signal and then obtains an output signal whose phase is continuous and whose frequency gradually changes gradually with respect to the input signal frequency.

(Background of *Technology and Invention) When trying to obtain an output signal whose phase is continuous and whose frequency gradually changes gradually on the PPM order with respect to the input signal frequency, for example by using a PLL circuit, It has been difficult to obtain a signal in which the phase is continuous and the frequency is gradually changing slightly due to loss of lock.

On the other hand, when time-division multiplexing information signals of multiple channels with different transmission lock signal frequencies, the highest frequency or higher frequency among the sampling frequencies or clock signal frequencies of the information signals of the multiple channels is set to correspond to the multiple channels. The information signals of the plurality of channels are rearranged in the form of time division multiplexing using a reference clock signal with a frequency multiplied by the frequency, and a dummy signal is inserted into a portion where the information signal is insufficient to obtain a continuous time division multiplexed signal. One of the applicants has proposed a time division multiplex transmission system.

For example, when decoding multiplexed data obtained by the above-mentioned time division multiplex transmission method based on a PCM audio signal in satellite broadcasting, a clock signal is regenerated from the multiplexed data by a clock regeneration circuit 20 as shown in FIG. . The reproduced clock signal is used as the data write clock signal Wck for one selected channel in the multiplexed data (the channel here corresponds to the video channel of satellite broadcasting) and is sent to the PCM multiplex demultiplex decoder 21.
The data are sequentially stored in the frame memory 22 within the frame memory 22. -' On the other hand, the read clock frequency control circuit 23 generates the read clock signal RCK based on the reproduced clock signal, and this is used as the data read clock signal to sequentially read out the data stored in the frame memory 22. We are getting data.

However, as mentioned above, in order to obtain continuous time-division multiplexed data on the transmitting side, a dummy signal is inserted into the portion where the information signal is insufficient. When it is detected that dummy data inserted by
The reproduction data of continuous pit streams can be reproduced by sequentially lowering the frequency of the read clock signal RCK and increasing the frequency of the read clock signal RCK to return it to the original frequency before the timing of writing to the frame memory 22 that is being read is matched. The applicant has filed a separate application to obtain the same.

In such a case, when the phase of the read clock signal RcK is continuous and the frequency changes only slightly, the sound quality of the audio signal during reproduction is improved. Therefore, it is desired that the frequency of read clock signal RCK changes little.

(Object of the Invention) The present invention has been made in view of the above, and an object of the present invention is to provide a frequency synthesizer capable of obtaining an output signal whose phase is continuous and whose frequency gradually changes sequentially with respect to the input signal frequency. purpose.

Another object of the present invention is to provide a frequency synthesizer that can be digitally controlled in addition to the above.

(Structure of the Invention) The present invention provides a first
, and second and third storage means each storing data at each time point obtained by dividing one cycle of a sine wave and a cosine wave. The input signal is divided by the frequency division ratio read from the first storage means by the variable frequency divider,
This frequency-divided output is counted by an address counter, and stored data is read from the second and 39th storage means based on the counted value. Data read from the second and third storage means is converted into analog. On the other hand, the input signal is supplied to a phase shifter that shifts the phase by 90 degrees.

The input signal and the output signal of the phase shifter are orthogonally modulated by the signals read from the second and third storage means and converted into analog signals in a quadrature modulator to obtain a frequency-synthesized output signal.

In the invention configured as described above, the signals obtained by converting the data read from the second, third, and third storage means into analog signals are sine waves and cosine waves. Furthermore, the frequency of the sine wave and cosine wave changes depending on the frequency division ratio stored in the first storage means, assuming that the storage capacity of the second and third storage means, that is, the number of division points in one cycle, is constant. The input signal and the output signal of the phase shifter are orthogonally modulated by the sine and cosine waves whose frequencies are changed.

As a result, an output signal is obtained in which the phase is continuous and the output frequency changes gradually and sequentially in response to changes in the frequency division ratio stored in the first storage means.

(Example of the invention) The present invention will be explained below using examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

1 is a variable frequency divider that generates the address clock signal A0, and the clock signal ■ is supplied to the input terminal 2. For example, in the example of the multiplexed data decoder, the write clock signal WeX is frequency-divided by the variable frequency divider 1 to generate the address clock signal ACIC. Frequency division ratio data N of the variable frequency divider 1 is stored in the ROM 3 in advance, is read out by the output of an address counter (not shown) that counts a predetermined clock signal, and is supplied to the variable frequency divider 1. .

The generated address clock A- is supplied to the address counter via the AND gate 4 and counted.

The control signal INK applied to the input terminal 13 is also supplied to the AND gate 4 as an input, and the opening/closing of the gate of the AND gate 4 is controlled.

On the other hand, ROMs 5 and 6 store data at each point in time obtained by dividing one cycle of a unit sine wave (here, the unit means amplitude "1"; the same applies hereinafter) and a unit cosine wave, respectively.

The addresses of ROMs 5 and 6 are specified by the output of the address counter which counts the address clock signal AB. The data read from the ROMs 5 and 6 by this address designation is converted into analog signals by digital/analog converters (DACs) 8 and 9, respectively.

The black signal 1c supplied to input terminal 2 is connected to phase shifter 1.
The clock signal rcx itself is phase-shifted by 90 degrees at 0, and the clock signal ICE' is phase-shifted by 90 degrees at phase shifter 10.
, the output analog signal from the digital/analog converter (DAC) 8 and the digital/analog converter (
The output analog signals from the DAC) 9 are both supplied to a quadrature modulator 11 to produce a clock signal Ick and a 90 degree phase-shifted clock signal ■. ” as a carrier wave
The output signals from analog converters (DACs) 8 and 9 are amplitude-modulated and combined, and then output from an output terminal 12.

Now, the clock signal I0 is 5inx, and its frequency is fl.
cK, the output signal of the phase shift circuit 10 becomes cos x. Here, x=2πfleet.

Clock signal■. is divided by N by the variable frequency divider 1, and counted by the address counter 7 when the control signal INN is at a high potential. As a result, ROM5 and 6 are addressed by the address count value, and ROM5
The data in and 6 is read. This read data is converted into analog signals by digital/analog converters (DACs) 8 and 9. The converted analog signals are unit sine waves and unit cosine waves, respectively. The frequency of this unit sine wave and unit cosine wave is RO
It is determined by the capacity of M5.6 and the frequency f ACK of address clock signal ACK, and the capacity of ROM5.6 is determined by M5.6.
Then, f Ac*/M. As a result, the frequency of the unit sine wave and unit cosine wave output from the digital/analog converters (DACs) 8 and 9 can be controlled by changing the frequency f ACX of the address clock signal AC. can be done by changing the division ratio N of the variable frequency divider l, which is R
This can be done by setting the frequency division ratio data stored in the OM3 in advance.

Digital/analog converter now! The unit sine wave output from (DAC) 8 and 9 is 51 nys, and the unit cosine wave is expressed as cos y.

Here, 3F=2π(f acx/M) t. Therefore, the output terminal 1 is amplitude modulated by the quadrature modulator 11.
The clock signal Ock output from 2 is 5in (x-
y) or cos(x-y). However, by changing the frequency division ratio given to the variable frequency divider 1, the address clock signal A
By changing the frequency of CK to (f ACK + ΔfAcK), the unit sine wave 5iny becomes 5inO' + θ,
), the unit cosine wave cos y is changed to cos(y+01). Here (y+θ+)=(2π ((fa
cK+Δf xcx)/M)t). As a result, the clock signal Ock becomes sin[x(y〇, )] or c
os(X(y+θ,))], and for example, in the example of the multiplexed data decoder, the clock signal Ock becomes the read clock signal Rck.

Therefore, by setting small changes in the frequency division ratio data stored in adjacent addresses between the frequency division ratio data stored in advance in the ROM 3, the input clock signal IC
It is possible to obtain an output clock signal OCK that sequentially changes slightly with respect to K.

As explained above, according to one embodiment of the present invention, by using the quadrature modulator 11, the output clock signal OcK has a continuous phase, and the frequency can be changed slightly, and the input signal ①.

It is also possible to obtain a phase-continuous output clock signal OCR even when switching from using the clock signal as a clock signal to performing frequency synthesis.

(Effects of the Invention) As explained above, according to the present invention, since frequency synthesis is performed by a quadrature modulator, it is possible to obtain an output signal with continuous phases.

Further, since the modulation signal frequency supplied to the quadrature modulator is obtained from the transmission lock signal frequency, the output signal is synchronized with the transmission lock signal, and no adjustment for synchronization is required.

Furthermore, since the modulation signal frequency supplied to the quadrature modulator is controlled by the frequency of the address clock signal, it can be varied from DC, and the address clock signal frequency is determined by the variable frequency divider ratio (N). Since this frequency division ratio (N) is set in the ROM, it is possible to obtain an output signal whose frequency is slightly changed. Furthermore, there is an effect that the degree of freedom for changing the output signal frequency is large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a decoder for multiplexed data. ■--Variable frequency divider, 3.5 and 6--ROM. 7 --- Address counter, 8 and 9 --- DA
Cllo--Phase shifter, 11--Quadrature modulator.

Claims (1)

[Claims] a first storage means that stores a frequency division ratio; a variable frequency divider that divides the input signal by the frequency division ratio read from the first storage means; and each time point at which one period of the sine wave is divided. a second storage means that stores data at each point in time when one period of the cosine wave is divided; an address counter that specifies the read address of the third storage means; first and second conversion means that convert the read data from the second and third storage means into analog signals; and a quadrature modulator that modulates the input signal and the output of the phase shifter with the outputs of the first and second conversion means.