KR19990035533U - Parallel data transfer device using multi-carrier method - Google Patents

Abstract

The present invention relates to a parallel data transmission apparatus using a multi-carrier scheme, and it is an object of the present invention to provide a parallel data transmission apparatus using a multi-carrier scheme in which the most important problem in data transmission is how much data is transmitted per unit time, Conventional parallel data transmission is performed by serial transmission, so that parallel data is converted into serial data at a transmission rate, so that the speed is reduced by the number of parallel data. In addition, unnecessary bits for synchronization, that is, There is a problem that the amount of data to be transmitted increases significantly as the stop bit is added.

Therefore, in order to solve the above-mentioned problems, the present invention has been made to solve the above-mentioned problems by using a multi-carrier parallel data The present invention provides an efficient transmission method by improving the speed of data to be transmitted and preventing addition of unnecessary data by configuring a transmission system.

Description

Parallel data transfer device using multi-carrier method

The present invention relates to a parallel data transmission apparatus, and more particularly, to a multi-carrier scheme for parallel data demodulation and data transmission, thereby improving the speed of data transmitted and preventing unnecessary data from being added The present invention relates to a parallel data transmission apparatus using a multi-carrier scheme, and more particularly, to a parallel data transmission apparatus employing an efficient transmission scheme.

As shown in FIG. 1, the conventional parallel data transmission apparatus is synchronized with an applied parallel clock signal Clock_P and a serial clock signal Clock_S to generate N parallel data D ₀ , D ₁ , D ₂ , Serial (S: Serial) converter 1 for converting the serial bit data D _-1 to D- _N-1 into serial bit data of a line, An S / P converter 2 for converting the serial bit data converted by the P / S converter 1 into N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 , ).

The operation of the conventional parallel data transmission apparatus constructed as above will be described below.

First, when a parallel clock signal Clock_P is applied to the P / S converter 1, the P / S converter 1 synchronizes with the applied parallel clock signal Clock_P, ₀ , D ₁ , D ₂ , ..., D _N-1 ) into the shift register at the same time.

Then, the P / S converter 1 generates the start bit and then outputs the parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 through the serial data line as serial bit data Respectively.

That is, the P / S converter 1 sequentially shifts N parallel data D ₀ , D ₁ , D ₂ , ..., D _{N-1 in} one bit according to a serial clock signal Clock_S applied thereto, Bit data.

When the N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 are transmitted as serial bit data, the P / S converter 1 generates a stop bit The parallel clock signal (Clock_P) must be generated after N times as in the case of the clock signal (Clock_S) of "Clock_P> N × Clock_S".

On the other hand, in the S / P converter 2, after the start bit is removed from the serial data transmitted by the serial bit by the P / S converter 1, the shift register is shifted by one bit and the data is synchronized with the serial clock signal (Clock_S) .

At this time, in the S / P converter 2, N serial data are input and N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 are input to t ₀ ≥ N × As shown in FIG.

Here, there may be a case where a clock is required for data transfer synchronization and a clock for transferring parallel data depending on the type of the converter.

That is, when there is no external clock input of the receiving side S / P converter 2, a clock is generated using the clock generator in the S / P converter 2.

However, the most important problem in data transmission is how much data is transmitted per unit time, how much data is transmitted in a unit time, how far it is stably transmitted, and how efficiently the transmission line is designed. In the conventional parallel data transmission, The parallel data is converted into the serial data at the transmission rate, so that the speed of the parallel data decreases. In addition, since the unnecessary bits for synchronization are added, that is, the start bit and the stop bit are added, .

Accordingly, the present invention has been made to solve the above problems, and it is an object of the present invention to provide a multi-carrier method in which parallel data is demultiplexed into a multi-carrier system and N parallel data is transmitted in parallel through a single line It is an object of the present invention to provide an efficient transmission scheme by improving the speed of data to be transmitted and preventing unnecessary addition of data.

1 is a block diagram showing a configuration of a conventional parallel data transmission apparatus.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a parallel data transmission apparatus.

FIG. 3 is an internal block diagram of a P / S conversion encoder in a parallel data transmission apparatus using the proposed multi-carrier method.

FIG. 4 is an internal block diagram of an S / P conversion decoder in a parallel data transmission apparatus using the proposed multicarrier scheme.

5A to 5E are data flow diagrams of the P / S conversion encoder in the present invention.

6A to 6C are sine-modulated waveforms of the storm data viewed from the time axis of the P / S conversion encoder in the present invention.

7A to 7C are cosine (cos) modulation waveforms of the radix data viewed from the time axis of the P / S conversion encoder in the present invention.

8A is a waveform diagram of a multi-carrier frequency viewed on the frequency axis of a P / S conversion encoder to which a high-level clock signal is applied in the present invention, and a frequency of a P / S conversion encoder to which a low- Waveform diagram of multi - carrier frequency on axis.

9A and 9B are demodulated waveform diagrams of the even and odd data by the S / P conversion decoder in the present invention, and c is an extraction waveform diagram of data extracted by the multiplication of FIGS. 9A and 9B.

The parallel data transmission apparatus using the multi-carrier according to the present invention for achieving the above object, as shown in FIGS. 2 to 4,

(P) for modulating N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 into serial data of different carrier frequencies in a multicarrier manner according to a clock signal of a constant level, ) / Serial (S: Serial) conversion encoder 10;

The serial data of the different carrier frequencies modulated by the P / S conversion encoder 10 in the multicarrier manner according to the clock signal of the constant level is converted into the N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 ) and outputs the demodulated signal; .

The P / S conversion encoder 10 converts the even and odd data D ₀ (G ₀ , G ₁ , G ₂ , ..., G _N-1 ) _N LPFs (Low Pass Filter) (LPFs) for eliminating the high frequency components of the signals D ₁ , D ₂ , ..., D _N-2 (D ₁ , D ₃ , 11);

(D ₀ , D ₂ , ..., D _N-2 ) (D ₁ , D ₃ , ..., D _N-1 ) in which high frequency components are removed by the first LPF 11, In Sine Wave ( ) And cosine wave ( N) first frequency assigning sections 12 which multiply each of the frequency bands of the first and second frequency bands, respectively, and then perform frequency domain operation on the different carrier frequency f (t) _even , f (t) _odd ;

(T (t) _even , f (t) _odd ) multiplied by the N first frequency allocation units 12 to orthogonally synthesize them and modulate them into the serial data f A data synthesis section 13 for outputting the data to the S / P conversion decoder 20 by one line; And a plurality of light emitting diodes (LEDs)

The S / P conversion decoder 20 converts the serial data f (t) modulated by the P / S conversion encoder 10 into a single line and outputs the sine wave (f ) And cosine wave ( N) second frequency assigning sections (21) for performing frequency hopping operations to multiply the first and second carrier frequencies (f (t) _even , f (t) _odd )

N second LPFs 22 for removing high frequency components of different carrier frequencies f (t) _even , f (t) _odd , frequency-domain-extracted by the N frequency allocation units 21;

The carrier frequency f (t) _even , f (t) _odd in which the high frequency component is removed by the second LPF unit 22 according to the clock signal of a constant level is _divided into _odd and odd data D ₀ and D _{2 N} , ..., D _N-2 ) (D ₁ , D ₃ , ..., D _N-1 ). The present invention is characterized in that it comprises:

The N digital parallel data D ₀ , D ₁ , D ₂ , ..., G _n passing through the gates G ₀ , G ₁ , G ₂ , ..., G _{N-1 are} supplied to the P / S conversion encoder 10. , D _N-1) the data of the even and odd number _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., Hi, or a clock having a low level to be separated by a D _N-1) A first clock signal generator (not shown) for generating a signal;

The N digital parallel data is separated to solid and the radix data _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., D N-1) by a portion of the first clock signal generator ( D ₀ , D ₁ , D ₂ , ..., D _N-1 ) to an analog signal;

And a high / low level clock signal generated by the first clock signal generator so as to reduce the frequency band of the sine wave ) And cosine wave ( ) Is excellent in the second or odd-numbered data binary multiplying _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., a first data selection unit for selecting any one of the D _N-1) (Not shown); Is added,

(D ₀ , D ₂ , ..., D _N ) having different carrier frequencies f (t) _even and f (t) _odd from which high frequency components have been removed are supplied to the S / P conversion decoder 20, _{-2) (D 1, D 3} , ..., the second clock signal generating portion (not shown for the sampler 23 is high or generates a clock signal of a low level to be so separated by the D _N-1)) as;

The second data of the solid and the rider separated from the sampler (23) according to a high or a clock signal of a low level is generated from the clock signal generation unit _{(D 0, D 2, ...} , D N-2) (D 1, D ₃ , ..., D _N-1 );

To reduce the band of the frequency used in the first half of the second solid or odd-numbered data of the inverse transform by the second inverter _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., D N- _{A first} data selection unit (not shown) for selecting any one of the first data selection unit and the second data selection unit; Is added.

The operation of the parallel data transmission apparatus using the present inventive multi-carrier will be described as follows.

5, when N digital parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 are input to the P / S conversion encoder 10, the P / S conversion encoder 10 generates N parallel data D ₀ , D ₁ , D ₂ , and D ₃ input in a multi-carrier manner in accordance with a clock signal having a predetermined level generated by the first clock signal generator, And outputs the serial data f (t) to the S / P conversion decoder 20 on one line after modulating the data D _-1 , ..., D _N-1 with different carrier frequencies.

In other words, when a high-level clock signal is generated in the first clock signal generator, the N parallel data D ₀ , D ₁ , D ₂ , ..., D _{N -1} , the data (D ₀ , D ₂ , ..., D _N-2 ) The first clock signal generator generates a low-level clock signal through the _N gates G ₀ , G ₂ , ..., G _N-2 , The odd _- numbered data D ₁ , D ₃ , ..., D _{N-1 in the} parallel data D ₀ , D ₁ , D ₂ , Gates G ₁ , G ₃ , ..., G _N-1 .

At this time, the N gates _{(G 0, G 1, G} 2, ..., G N-1) solid has passed through the second and the odd-numbered data _{(D 0, D 2, ...} , D N-2) (D 1 , D ₃ , ..., D _N-1 ) are inverted analogously by the first inverter 14 and input to the N first LPFs 11 as shown in FIGS. 5c and 5d, The LPF 11 multiplies the odd _- numbered and odd _- numbered data D ₀ , D ₂ , ..., D _N-2 (D ₁ , D ₂ , ..., D _N ) that have passed through _N gates (G ₀ , G ₁ , G ₂ , ₁ , D ₃ ,..., D _N-1 ) and outputs the high frequency components to the N first frequency allocation units 12.

Then, the N first frequency-dividing sections 12 receive the odd / even-numbered data D ₀ , D ₂ , ..., D _N-2 (D ₁ , D ₃ , ...) D _N-1 ) to the even-numbered data D ₀ , D ₂ , ..., D _N-2 by the sine wave signal in the first frequency- And the odd-numbered data D ₁ , D ₃ , ..., D _N-1 are multiplied by the cosine wave (T) _even , and f (t) _odd ) of the carrier frequency p (t).

That is, when generating the high-level clock signal in the first clock signal generating unit, as shown in FIGS. 6 and 7, in the first frequency assigning unit 12,

Wow,

(2ω ₀ <ω ₁ , 2ω ₁ <ω ₂ , 2ω ₂ <ω ₃ , ...)

(T) _even and f (t) _odd of the equations (1) and (2), respectively, as shown in FIG.

At this time, since, as perpendicular to each other as above, each of the carrier state Paju _{(f (t) even, f} (t) odd) being added is shown in Figure 8, without causing any interference, especially as because sine and cosine are separated from each other The data is synthesized through the data synthesizer 13 without being canceled and compensated due to the absence of one or more components of the frequency and then modulated into the serial data f (t) to produce N compression effects on one line And is transmitted to the S / P conversion decoder 20 at the same time.

Here, in accordance with the high or low level clock signal generated by the first clock signal generator, the first data selector selects the sine wave ) And cosine wave ( (D ₀ , D ₂ , ..., D _N-2 ) (D ₁ , D ₃ , ..., D _N-1 ) obtained by multiplying the frequency of the used frequency The band was cut in half.

On the other hand, in the S / P conversion decoder 20, different carrier (s) modulated by the P / S conversion encoder 10 according to the high or low level clock signal generated by the second clock signal generator Frequency serial data f (t) is demodulated and transmitted again to N parallel data D ₀ , D ₁ , D ₂ , ..., D _N-1 .

In other words, in the N second frequency division parts 21 included in the S / P conversion decoder 20, the serial data f (t)

Sine Wave )Wow

Cosine Wave ( (T) _even , f (t) _odd ), and outputs the result to the N second LPFs 22, so that the second LPF 22 22), the high frequency components of the different carrier frequencies f (t) _even and f (t) _odd extracted by the frequency conversion are removed.

The carrier frequencies f (t) _even and f (t) _odd from which the high frequency components have been removed by the second LPF 22 are supplied to the _odd and odd data D ₀ , D ₂ , ..., D _N-2 ) (D ₁ , D ₃ , ..., D _N-1 ).

That is, the sampler 23 divides the serial data f (t) input according to the high or low level clock signal generated by the second clock signal generator into the odd and odd data D ₀ , D ₂ , ..., D _N-2 ) (D ₁ , D ₃ , ..., D _N-1 ) and will be described as an example with reference to the multiplication law of the sinusoidal function shown in FIG. Respectively.

First, the sine wave multiplication law,

Here, if A = B, then by Equations (3) and (4)

And a number of sampled frequency signal _{(ω x-1, ω x} , ω x + 1) plus the frequency axis, as shown in Figure 9, so as to multiply the ω _x in, a different frequency also appears circle much signal ω _x ( _X) component is canceled and appears as a direct current (DC) component, which is filtered by a low-pass filter (LPF).

Therefore, by multiplying the random data sine wave (sinω ₀ t) to know the (D _0), the random data (D ₀₎ of the serial data (f (t)) input from the S / P conversion decoder 20 ,

_{f (t) even × sinω 0} t = (D 0 sinω 0 t + D 2 sinω 1 t + D 4 sinω 4 t + ...) × sinω 0 t

= D ₀ + sin ₂ ? ₀ t + ...

, The value of the equation (7) = D ₀ + sin ₂ ? ₀ t + ... Is passed through the second LPF 22, the second LPF 22 generates the second harmonic of the DC component in the range satisfying the condition (fc <f ₀ ) of the cut-off frequency The data D ₀ of the data D0 is extracted.

Therefore, if the above-described process is repeatedly performed, the sampler 23 of the S / P conversion decoder 20 can receive the serial data of different carrier frequencies modulated by the P / S conversion encoder 10 in the multi- (f (t)) the back superior second and odd-numbered data _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., D N-1) becomes separated by, the sorting the solid-th and odd-numbered data _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., D N-1) N parallel data through the (D _0, D _1, D ₂ , ..., D _N-1 ) are demodulated and transmitted.

Here, the first 2 LPF (22) of the even or odd number that has passed through the data _{(D 0, D 2, ...} , D N-2) (D 1, D 3, ..., D N-1) is both a DC component digital The logic of the sampler 23 becomes "0" or "1", so that information of 1 bit can be extracted by only a certain threshold value.

The data D ₀ , D ₂ , ..., D _N-2 (D ₁ , D ₃ , ..., D _N-1 ) of the odd or even number separated by the sampler 23 are input to the second inverter 24 ) in was such that the inverse transform to the digital, wherein the solid inverted by the second inverter 24, a second or odd-numbered data (D _0, D _2, ..., D _N-2) (D _1, D ₃ by, ..., D _N-1 ) is selected by the second data selector to reduce the frequency band of use frequency by half.

As described above, according to the present invention, a parallel data transmission system using a multi-carrier scheme in which parallel data is demultiplexed in a multi-carrier manner and N pieces of parallel data are transmitted in parallel through one line, It is possible to prevent unnecessary addition of data and to provide an efficient transmission method.

Claims (5)

A P / S conversion encoder for modulating the N parallel data in the far carrier system according to a clock signal of a constant level into serial data of different carrier frequencies and outputting the serial data; An S / P conversion decoder for demodulating serial data of different carrier frequencies modulated by the P / S conversion encoder in accordance with a clock signal of a constant level into N parallel data, and outputting the serial data again; And a parallel data transmission unit for transmitting the parallel data. The apparatus as claimed in claim 1, wherein the P / S conversion encoder comprises: N first LPFs for removing high frequency components of an odd and odd data passing through N gates; N first frequency band-dividing units for multiplying sine wave signals and cosine wave signals, which are sinusoidal wave signals, respectively, with high frequency components removed from the high frequency components by the first LPF, and additionally frequency-combining the sine wave signals with different carrier frequency bands; A data synthesizer for synthesizing orthogonally different carrier frequencies multiplied by the N first frequency band allocation parts, modulating the orthogonal data into serial data, and outputting the serial data to a S / P conversion decoder as a single line; And a parallel data transfer unit for transferring the parallel data. The semiconductor memory device according to claim 2, further comprising: a first clock signal generator for generating a high or low level clock signal so that N digital parallel data passing through the gate can be separated into data of odd and odd numbers; A first inverter for inversely converting N digital parallel data separated by the first clock signal generator into an excellent data and an odd data; A selector for selecting any one of odd-numbered or odd-numbered data obtained by multiplying a sine wave and a cosine wave according to a high / low level clock signal generated by the first clock signal generator so as to reduce a band of the used frequency by half; 1 data selector; Wherein the parallel data transmission method is a parallel data transmission method using a multi-carrier scheme. 2. The apparatus as claimed in claim 1, wherein the S / P conversion decoder is configured to perform a frequency combining operation so as to extract a different carrier frequency by multiplying sine wave and cosine wave by serial data modulated by a P / N &lt; / RTI &gt; N second LPFs for eliminating high-frequency components of different carrier frequencies extracted by frequency-summing by the N frequency-frequency assigning units; N samplers for separating the carrier frequency in which the high frequency component is removed by the second LPF unit according to a clock signal of a constant level into the odd and odd data; And a parallel data transfer unit for transferring the parallel data. The apparatus of claim 4, further comprising: a second clock signal generator for generating a high or a low level clock signal to the sampler so that different carrier frequencies from which high frequency components have been removed can be divided into data of odd and odd numbers; A second inverter for digitally inverting the data of odd and odd numbers separated by the sampler according to a high or low level clock signal generated by the second clock signal generator; A second data selector for selecting either the odd-numbered or odd-numbered data inversely transformed by the inverter so as to reduce the band of the used frequency in half; Wherein the parallel data transmission method is a parallel data transmission method using a multi-carrier scheme.