JPS61276265A - Insulated gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To inhibit the generation of impact ionization of an insulated gate type field-effect transistor and the generation of a parasitic bipolar effect with the generation of the impact ionization by constituting a section between a source and a drain and a section between a drain and a substrate by a semiconductor having predetermined forbidden band width and electron affinity. CONSTITUTION:A P-type semiconductor is used as a substrate 1 while a semiconductor having forbidden band width smaller than the substrate 1 and electron affinity larger than the substrate is employed as a source 2 and a semiconductor having forbidden band width larger than the substrate 1 and electron affinity smaller than the substrate is used as a drain 3, and high-concentration N-type regions are constituted. On the other hand, a region 4 connecting the substrate 1 and the drain 3 is composed of a semiconductor, forbidden band width of which changes continuously and monotonously. The combination of substances such as Ga0.28IN0.72P0.4As0.6 as the substrate 1, substances such as Ga0.47IN0.53As as the source 2 section, substances such as InP as the drain 3 section and substances such as GaxIn1-xPyAs1-y(0<=x<=0.28,0<=y<=0.4,y=1.429x) is possible as said each semiconductor, and these semiconductors are formed through a method such as a selective epitaxial growth method.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor, and in particular to an insulated gate field effect transistor that suppresses the occurrence of impact ionization and the parasitic bipolar effect that accompanies it. 0 Related to Transistors [Prior Art] In an insulated gate field effect transistor, impurities of a conductivity type opposite to that of the substrate or well are introduced into a semiconductor substrate such as silicon to form source/drain regions. It has a structure in which an insulating layer is formed thereon and a gate electrode is formed thereon. Therefore, in this type of transistor, the source and drain regions are necessarily made of the same semiconductor as the substrate. [Problems to be solved by the invention] As mentioned above, the conventional insulated gate type It has been taken for granted that field-effect transistors are constructed of the same semiconductor as the upper and lower substrates of the source and drain regions, but when a high drain voltage is applied to these transistors, impact ionization occurs within the drain-substrate junction depletion layer. This phenomenon causes the problem that the potential inside the substrate increases due to the generated carriers, and the source Φ substrate junction becomes forward biased, causing parasitic bipolar breakdown. , by Sze, John-Wi
“Physics o” published by Ley & Son.
f Sem1conductorDevices 5e
It is described in P2S5-483 of cond Edition'.

[Means for solving problems]

In the insulated gate field effect transistor of the present invention, the source portion is made of a semiconductor with a narrower bandgap width and a much larger electron affinity than the substrate, and the drain portion is made of a semiconductor with a wider bandgap width and smaller electron affinity than the substrate. Further, the substrate and the drain portion are made of a semiconductor whose forbidden band width changes continuously and monotonically.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a vertical cross-sectional view schematically showing an embodiment of the present invention, in which 1 is a semiconductor substrate, 2 and 3 are source and drain chain acids, respectively, and 4 is a semiconductor substrate for connecting the substrate 1 and the drain 3. It is an area. In this example, a P-type semiconductor is used for the substrate 1, a semiconductor with a smaller forbidden band width (φ) and a larger electron affinity than the substrate 1 is used for the source 2, and a semiconductor with a larger forbidden band width φ) than the substrate 1 is used for the drain 3. The entire high-concentration n-type region is constructed using a semiconductor having a large electron affinity and a small electron affinity. On the other hand, the region 4 connecting the substrate 1 and the drain 3 is made of a semiconductor whose forbidden band width changes continuously and monotonically. In the figure, 8 is a gate electrode, 9 is an insulating film, 10° and 11 are source and drain electrodes, and 12 is a substrate electrode.

As each of the semiconductors, for example, Ga0.28I is used on the substrate 1.
nO, 72Po, 4 As0.6, Ga0.47InO, 53As in the source 2 part, InP in the drain 3 part, Gax In in the drain-substrate connection part 4.
1-x PyAs 1-y (0≦X≦0.28, 0≦
Considering the combination of y≦Q, 4, y==1.429x, these are formed by, for example, selective epitaxial growth. Of course, other configurations of all combinations fL of ternary to quaternary mixed crystals cannot be considered.

The second factor is the energy band structure diagram when a drain voltage is applied on a line along the insulating film substrate interface of the semiconductor device shown in FIG. 1. In the figure, B1 indicates the band structure of the substrate 1, 82 indicates the band structure of the source 2, BS indicates the band structure of the drain 3, and B4 indicates the band structure of the connecting portion 4 between the drain 3 and the substrate 1. Also, D is the depletion layer between the source and substrate, and B6 is the medium electric field drift region, %D? indicate the depletion layer between the drain and the substrate, respectively. Furthermore, E, B
S ” to l EfmB(yc) indicates the entire forbidden band width of each semiconductor of the substrate 1, source 2, drain 3, and substrate/drain connection portion 4, and in particular, Ef(b) continuously changes depending on the position X. .

As can be seen from this figure, when a positive voltage is applied to the gate electrode 8, the barrier potential in the source-substrate depletion layer decreases,
Electrons are injected from the source 2 into the substrate l by diffusion.

These electrons move toward the drain side through the medium electric field drift region D6 due to the lateral electric field between the source and the drain.

When the electrons reach the depletion layer between the drain and the substrate, they are rapidly accelerated by the high electric field in the same region and reach the drain 3. At this time, when the gate voltage and drain voltage are changed, the slope of the energy band of the source-substrate depletion layer, the bitter barrier potential, and the medium electric field drift region changes, and the current between the source and drain changes. do.

Figure 3 (2) shows the semiconductor of the substrate 1 and the drain 30, respectively.
The energy band structure is shown before full contact with the semiconductor ((A) in the same figure) and after (■ in the same figure). In the figure, XB
*Xo is the electron affinity of each semiconductor of the substrate and drain, respectively.
Similarly, ECM and ECD are the lower end of the conduction band, Erg p
EFD is the 7-Eluminum level, Ef! 1*EfD is forbidden band width,
Eyl s EyD indicates the upper end of the valence band.

Further, EF is the Fermi level when the substrate 1 and the drain 3 are in contact with each other, and ΔX is the difference in contact potential when the same semiconductor as the drain 3 is used for the substrate 1 as well. Furthermore, the box in the figure is the lower end of the conductor when the same semiconductor as the drain 3 is used for the substrate l, and B is the lower end of the conductor when a different semiconductor according to the present invention is used.

As you can see from these figures, the n
The barrier potential felt by electrons at both ends of the PN junction is smaller than A so far by ΔX. This situation is exactly the same when a voltage is applied across the Pn junction, and especially when the reverse bias is set to nm, the internal voltage decreases by the amount of the positive contribution. On the other hand, when the substrate and drain are connected by a semiconductor whose total forbidden band width changes continuously and monotonically as in the present invention, there is no step at the lower end of the conduction band as shown in B in the figure. When electrons move in the depletion layer, the effect of reducing the barrier potential by ΔX gradually adds to the effect of making it easier for p1 electrons to move. The value of ΔX is approximately given by the following equation.

Δx=Eyo-Era On the other hand, in order for electrons to be accelerated by a high electric field and cause impact ionization, the electrons must have energy greater than the required threshold energy, but this threshold energy and forbidden band #A
In general, the larger the forbidden band width, the more likely impact ionization will occur, and the lower the electric field, the less likely impact ionization will occur. Therefore, if the configuration of the present invention described above is used,
The forbidden band width becomes larger on the drain side, and the electric field within the drain-substrate junction is reduced compared to when the same semiconductor substrate as the drain is used, making it difficult for impact ionization to occur.

Next, it will be explained that it is effective to suppress the parasitic bipolar effect by using a semiconductor for the source 2 that has a narrower forbidden band width and greater electric affinity than the substrate 1.

In the case of FIG. 2, when the amount of holes generated by impact ionization is large, they begin to accumulate on the source side of the portion 83 of the substrate 1 and are directed in the direction of the source-substrate bond forward bias. here,
The ratio of electron current to hole current at the source-substrate junction is given by the following equation.

However, Dn (electron diffusion coefficient in the substrate semiconductor): Hole diffusion coefficient in the semiconductor of the source portion Ln: Electron diffusion length Lp in the substrate semiconductor Two hole diffusion length Pl in the semiconductor of the source portion: Hole concentration at thermal equilibrium Ns: Electron concentration at thermal equilibrium in the semiconductor of the source portion mpl: Effective mass of holes in the substrate semiconductor rnlB:
Effective mass of electrons in the substrate semiconductor mirror m, 8: Effective mass of holes in the semiconductor of the source portion mn3: Effective mass of electrons in the semiconductor of the source portion R: Boltzmann constant T: Key factor that determines the value of temperature r The parameters are N31Pal・E
Assuming that yB EyB and N3 e Pal fe are given, the value of r is approximately determined by EyB - Eys. In the case of the configuration of the present invention described above, s Efs bf
Since B<O, γ is 1.0 Therefore, even if the Pn junction between the source and the substrate is forward biased, most of the current that flows is a hole current, and most of the electrons are Do not inject. This suppresses conductivity rate modulation and increase in impact ionization due to injected electrons, making breakdown due to parasitic bipolar effects less likely to occur.

Note that although the example of an n-channel surface conduction type was described in the previous example, the present invention can be similarly applied to a P-channel type or a bulk conduction type insulated gate transistor. Further, it is also possible to replace the semiconductor with a structure in which a single layer of a superlattice or a strained superlattice having an equivalent energy level difference in all parts is laminated in the lateral direction.

〔Effect of the invention〕

As explained above, in the present invention, the source is made of a semiconductor that has a smaller bandgap and larger electron affinity than the semiconductor used for the substrate, and the drain is made of a semiconductor that has a larger bandgap and smaller electron affinity than the semiconductor used for the substrate. Furthermore, since the gap between the drain and the substrate is made of a semiconductor whose forbidden band width changes continuously and monotonically, collision ionization of an insulated gate field effect transistor and the parasitic bipolar effect associated with this are avoided. It has the effect of suppressing the occurrence.

[Brief explanation of drawings]

FIG. 1 is a longitudinal sectional view schematically showing an entire embodiment of the present invention, FIG. 2 is a diagram of the energy band structure when drain voltage is applied on a line along the valve surface of the insulating film substrate of the transistor of FIG. 1,
FIGS. 3(B) and 3(B) are diagrams of the energy band structure before and after the substrate semiconductor and drain semiconductor are brought into contact, respectively. 1...Substrate, 2...Source, 3...
...Drain, 4...Substrate/drain connection part, 8...Gate electrode, 9...Insulating film,
10... Source electrode, 11... Drain electrode. Agent: Susumu Uchihara, patent attorney. Hemorrhoids 3rd WJ A: Hanne 91 Kudrei words Hei Ke γ same one and a half ■ Ite 2 case including the prostration - L mama 11; Me harm i

Claims (1)

[Claims] 1. A source is formed on a substrate made of the semiconductor of 1 with a semiconductor having a narrower bandgap width and larger electron affinity than the semiconductor, and a source is formed of a semiconductor with a larger bandgap width and smaller electron affinity than the semiconductor of 1. An insulated gate field effect transistor characterized by forming a drain and further connecting the substrate and the drain with a semiconductor whose forbidden band width changes continuously and monotonically.