JPS61273650A - Magnetic disk controlling device - Google Patents

Abstract

PURPOSE:To attain the transfer of data with high efficiency and at high speed in a reading mistake mode by controlling the transfer of data according to the cache operation designating information consisting of a transfer start cache address, etc. CONSTITUTION:A disk access request is held by a hard disk control circuit HDC 21 and read out by a microprocessor 27 and stored in a work memory 29. At the same time, the processor 27 sets a seeking command produced according to the access request to the circuit HDC 21. The HDC 21 controls a magnetic disk device 10 to seek a designated track. While the processor 27 supplied the disk block number and the direct memory address corresponding to the area of the device 10 to a circuit 25 according to the access request to start the circuit 25. A direct memory/searching circuit 35 performs a directory searching action with the block number defined as a target and holds the result of this searching action. The processor 27 produces the cache operation designating information in response to said held result and the access request contents and stacks the information to an address stack memory 36.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a magnetic disk control device having a built-in cache memory.

[Technical Background of the Invention] In this type of magnetic disk control device, when a disk access request is received from a host system, a directory search is performed to check whether a specified disk area exists in a cache memory. The disk is then accessed based on the results of this search and the contents of the disk access request.

Data transfer is performed between cache memories, between disks and host systems, and between cache memories and host systems. For example, if the read filler is +- (cache filler 1 or more at the time of a discrete request), no disk access occurs, and the contents of the cache memory area corresponding to the specified disk area are transferred to the host system.
Data transfer speed can be increased.

[Problems with Yellow Steel Technology] Now, in the magnetic disk control device described above, in the case of a read miss (cache miss at the time of a discrete request), disk data is transferred in cache block units to the newly registered cache block in the cache memory. It is necessary to write. Therefore, in the case of a read miss, the magnetic disk controller must also read data from disk areas that are not requested by the host system, and the data read from the disk must be commonly transferred to the host system and cache co-memory. It was necessary to control the data and to control the transfer only to the cache memory.

Therefore, magnetic disk control with cache memory'
1 devices are required to be able to efficiently execute data transfer control, especially in the case of a read error.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide a magnetic disk control device that can efficiently control data transfer, especially in the case of read misses, and is also capable of high-speed transfer. be.

[Summary of the Invention] The present invention provides cache operation specification information storage means for storing cache operation specification information consisting of a transfer start cache address, the number of transfer sectors, and a data transfer direction control code, and in the case of a read miss, the TD of the disk at that time. Sector number reading means for reading the sector number in the field, and cache operation specification information generation for generating the cache operation specification information and storing it in the cache operation specification information storage means based on the content of the disk access request from the host system and the directory search result. and data transfer means for sequentially retrieving cache operation designation information stored in the cache operation designation information storage means from the beginning and performing a data transfer operation based on the information. In the case of a read miss, the cache operation specification information generating means divides the cache block to be rewritten into the sector following the sector number read by the reading means and the first sector and last sector of the disk area to be transferred to the host system. Then, the above-mentioned cache operation specification information is generated for each segment tilted, and the cache operation specification information group whose head is the cache operation specification information in which the cache address corresponding to the above number of sectors is the transfer start cache address is generated as the cache operation specification information. The information is configured to be stored in the storage means.

[Embodiment of the Invention] FIG. 1 shows a block configuration of a magnetic disk control device 20 according to an embodiment of the present invention, and 21 is a hard disk control circuit (hereinafter referred to as HDC) for controlling the magnetic disk device 10. It is.

The HDC 21 has a first bus 24 consisting of a data line 22 and a control line 23, a driver/receiver (
It is connected to a host system (not shown) via a D/R (hereinafter referred to as D/R) 25. HDC21 is the second bus 2
6 is also connected. The bus 26 includes a microprocessor 27 that controls the entire magnetic disk control device 20, a program memory 28 that stores a control program (microprogram) for the microprocessor 27, a work memory 29 that forms a work area for the microprocessor 27, and a magnetic A buffer memory 30 is connected to absorb the difference in transfer speed between the disk device 10 and the host system.

31 is the third bus. Bus 31 is connected to second bus 26 via D/R 32. The bus 31 includes a cache control circuit 34 that mainly performs data transfer control including control of the cache memory 33, a directory memory/search circuit 35 containing a directory memory and research circuits (all not shown), and an address stack. A memory 36 is connected to the address stack memory 36.The address stack memory 36 stores the contents of the cache operation in cache operation specification information consisting of three parameters: a transfer start cache address a, the number of transfer sectors C, and a data transfer direction control code C. This is a FIFO stack that stores address stack memory 36.
Address port A has a stack address counter 37.
The output of the counter 37 is connected to the second bus 26, and the input of the counter 37 is connected to the second bus 26.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to FIGS. 2 to 4.

Disk access requests from the host system are handled by D/
R25, is transmitted to HDC21 via bus 24, and HD
It is held in a command register (not shown) in C21. The disk access request in the command register is read by the microprocessor 27 and stored in a predetermined area of the work memory 29. When the microprocessor 27 stores a disk access request (from the host system) in the work memory 29, it issues a seek command and sets it in the HDC 21 in accordance with the request. As a result, HDC2
1 controls the magnetic disk device 10 to seek a designated track. In addition, in accordance with the disk access request, the microprocessor 27 sends the disk block number and memory address (column address) from memory address 1 to memory address (column address) corresponding to the area (disk area) of the magnetic disk device 10 to be accessed to the bus 26 and D/R3.
2 and bus 31 to the directory memory/search circuit 35, and activates the circuit 35.

As a result, the directory memory/search circuit 35 performs a directory search targeting the disk block number. The results of this directory search are held within the directory memory/search circuit 35.

When the directory search result is held in the directory memory/search circuit 35, the microprocessor 27
Depending on the result and the content of the disk access request, one or more pieces of cache operation designation information are generated and stacked in the address stack memory 36 via the bus 26, D/R 32, and bus 31.

The cache operation designation information includes the transfer start cache address a1, the number of transfer sectors 2, and the data transfer direction control code C, as described above. In this embodiment, five types of control codes C are prepared, c=1 to c=5. The contents of control code C are shown below with reference to FIG.

(2) c=1 Used during read hit (cash hit in discrete request state). In this case, Fig. 2(a)
As shown in FIG. 3, the contents of the cache memory 33 are transferred to the host system, and the magnetic disk device 10 is not accessed.

■ c=2 Used in case of read miss (cache miss in discrete request state). In this case, the magnetic disk device 10 is read accessed as shown in FIG. 2(b),
The read data is transferred to the host system via the buffer memory 30 and written into the cache memory 33 at the same time.

■ c=3 Used in case of read miss (cache miss in discrete request state). In the case of a read miss, in order to write data to the cache memory 33 in units of cache blocks, it is necessary to also read data in disk areas that are not requested by the host system.

In this case, instead of the c=2 control code, c=3
The control code is used, and the glued data from the magnetic disk drive 10 is only written to the cache memory 33 as shown in FIG. 2(C) and is not transferred to the host system.

(2) c=4 Used during write hit (cash hit in disk write request state). In this case, write data from the host system is transferred to the magnetic disk device 10 via the buffer memory 30 and simultaneously written to the cache memory 33 as shown in FIG. 2(d).

■ C=5 Used at write miss (cache miss in disk write request state). In this case, the data of the host system etc. is stored in the buffer memory 3 as shown in FIG. 2(e).
0 is written only to the magnetic disk device 10, and is not written to the cache memory 33.

Here, regarding the generation of cache operation specification information, a disk access request from the host system is sent to sector number 1.
A case in which a cache miss, that is, a read miss occurs when there are 0 to 6 sectors of discrete data will be specifically explained. One track of the disk consists of 64 sectors with sector numbers O to 63, and the cache memory 33
It is assumed that one block (cache block) is also 64 sectors.

When the microprocessor 27 determines a read error based on the directory search result of the directory memory/search circuit 35, it first reads the ID field of the disk (
The sector number in the ID field latched in the ID register (not shown) in the HDC 21 is read.

When the microprocessor 27 reads a sector number, the microprocessor 27 divides the cache block to be rewritten into the next sector of the sector number and the first sector and last sector of the disk area to be transferred to the host system, and writes the cache block for each divided area. Generates cache operation specification information. Assuming that the currently read sector number is 4, the cache block consists of area A (corresponding to the disk area) with sector numbers O to 4, area B with sector numbers 5 to 9, as shown in FIG. It is divided into four areas: area C with sector numbers 10-15 and area C with sector numbers 16-63. In this case, it will be understood that if data is transferred in the order of areas B, C, D, and A, efficient data transfer without waiting time is possible.

Therefore, the microprocessor 27 first generates cache operation designation information for area B (that is, the area starting from the sector next to the read sector number), and
/ Stored in the top area of address stack memory 36 via R32 and bus 31. The cache operation specification information for area B is based on the start address of area B
z If the number of transferred sectors is 2B, then as shown in Figure 3, transfer start cache address a B % Number of transferred sectors 2B
and a data transfer direction control code C with c=3.

Next, the microprocessor 27 generates cache operation designation information for area C, and the address stack memory 36
Store in the subsequent area. The cache operation specification information for area C is as shown in FIG. 3, where the start address of area C is aC, the number of transfer sectors is fic, the transfer start cache address aC, the number of transfer sectors βC, and the data transfer direction control for C=2. Consists of code C.

Next, the microprocessor 27 generates cache operation designation information for the area, and writes the address stack memory 3
Stored in the subsequent area of 6. The cache operation specification information for the area is as shown in Figure 3, assuming that the start address of the area is a D s The number of transferred sectors is no, the transfer start cache address a D % Number of transferred sectors Qo and the data of c = 3 It consists of a transfer direction control code C.

Finally, the microprocessor 27 generates cache operation designation information for area A, and
Stored in the subsequent area of 6. Assuming that the start address of area A is a A, the number of transfer sectors is 2A, the cache operation specification information for area A is as shown in FIG. It consists of a transfer direction control code C.

When the microprocessor 27 finishes generating the cache operation designation information and storing the same information in the address stack memory 36, the microprocessor 27 generates a discrete area of five sectors starting from sector number 5 for the HD C2'l, that is, corresponds to area B. Specify the discrete area from the first sector of the disk area to the last sector of the corresponding track. The microprocessor 27 also has an address stack memory 36.
The start address of is set in the stack address counter 37, and the cache control circuit 34 is activated.

In response to a discrete instruction from the microprocessor 27, the HDC 21 reads data in a designated disk area from the magnetic disk device 10, and sequentially buffers the read data (discrete data) in the buffer memory 30 via the bus 26.

The HDC 21 has a built-in DMA circuit (not shown). When one sector or more of discrete data is buffered in the buffer memory 30, the DMA circuit communicates with the host system and the cache control circuit 3.
4, issues a transfer request. Then, upon receiving a positive response from the host system and cache control circuit 34,
The DMA circuit in the HDC 21 reads the data stored in the buffer memory 30 into its storage via the bus 26, and transfers it to the bus 24.
data line 22. Note that this read operation is performed in time division with the buffering operation to the buffer memory 30 described above.

Now, when the cache control circuit 34 is activated by the microprocessor 27, it receives the first cache operation designation information, that is, the designation information for the region B as shown in FIG. 3, from the area of the address stack memory 36 indicated by the stack address counter 37. Take it out. Then, as described above, when an affirmative response is returned to the request from the DMA circuit in the HDC 21 and the above-mentioned data transfer by the DMA circuit is started, the cache control circuit 34 synchronizes with the above-mentioned data transfer. Performs control operations according to cache operation specification information. That is, if the cache operation designation information is for area B as in this example, the cache memory control circuit 34 transfers the data sent from the HDC 21 (the DMA circuit therein) onto the data line 22 to the specified area B of the cache memory 33. Write sequentially to

In addition, the cache control circuit 34 is a D/R25
to inhibit the transfer of data on data line 22 to the host system.

When the cache control circuit 34 finishes writing to area B, it controls the stack address counter 37 to retrieve the next cache operation specification information, that is, the cache operation specification information for area C, from the address stack memory 36, and executes the specified control operation. Let's do it. In this case, the cache control circuit 34 controls the HDC 21 (DM
The data sent out from circuit A) onto the data line 22 is sequentially written into the designated area C of the cache memory 33, and at the same time, the D/R 25 is controlled to transfer the data on the data line 22 to the host system. When the cache control circuit 34 finishes writing to area C, it performs the control operation specified by the next cache operation designation information, that is, the cache operation designation information for the area.

As a result, writing to the designated area of the cache memory 33 is performed. Data transfer to the host system is also prohibited.

The HDC 21 has 59 discrete sectors starting from sector number 5 specified by the microprocessor 27, that is, areas B and C as shown in FIG.

When reading of the disk area corresponding to D is completed, an interrupt is issued to the microprocessor 27.

When the microprocessor 27 detects an interrupt from the HDC 21, it instructs the HDC 21 to discrete five sectors starting from sector number O, that is, to discrete the disk area corresponding to area A. As a result, the HDC 21 reads data from the disk area specified by the magnetic disk device 10, that is, the disk area corresponding to area A as shown in FIG. 4, and buffers it in the buffer memory 30.

The data buffered in the buffer memory 30 is
As mentioned above, the DMA circuit in HDC21
21 to the data line 22, and is sent to the cache memory 33 under the control of the cache control circuit 34.
is written to area A of . At this time, transfer of data on data line 22 to the host system is prohibited.

[Effects of the Invention] As detailed above, according to the present invention, data transfer is controlled according to the cache operation designation information consisting of the transfer start cache address, the number of transfer sectors, and the data transfer direction control code, so that the host system in particular Data transfer can be performed efficiently in the case of a read miss in which unrequested data also needs to be written to the cache memory. Moreover, according to this invention, data can be transferred from the first readable sector in the discrete in the case of a read error, so there is no need to wait for the rotation of the disk.
High-speed transfer becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a magnetic disk control device according to an embodiment of the present invention, FIG. 2 is a diagram explaining the operation contents indicated by the data transfer direction control code C applied to the control device, and FIG. 3 4 is a diagram illustrating a specific example of cache operation designation information generated at the time of a read miss, and FIG. 4 is a diagram illustrating a discrete operation in the example of FIG. 3. DESCRIPTION OF SYMBOLS 10... Magnetic disk device, 20... Magnetic disk control device, 21... Hard disk control circuit (1''DQ), 25.32... Driver/receiver (D/R), 21... Micro Processor, 30...
・Buffer memory, 33... Cache memory, 34
. . . cache control circuit, 35 . . . directory memory/search circuit, 36 . . . address stack memory. Applicant's agent Patent attorney Takehiko Suzue□, Bi A, -31□ Commissioner of the Japan Patent Office Michibe Uga 1, Indication of case Patent Application No. 1988-115918 2, Title of invention Magnetic disk control device 3, Make amendments Related patent applicant (307) Toshiba Corporation 4, agent 6, amended specification 7, contents of amendment and scope of claims in attached document. 2. Scope of Claims (1) In a magnetic disk control device with a built-in cache memory, there is provided: a determination means for determining, and a cache operation designation information storage means for storing cache operation designation information consisting of the number of lids, data transfer direction, and host system. and sector number reading means for reading the sector number stored in the ID field of the sector that is read earliest at that time when a read request is received from the host system and a read error is determined by the determination means. ,
Means for generating the cache operation designation information based on the contents of the disk access request from the host system and the determination result from the determination means and storing the generated cache operation designation information in the cache operation designation information storage means, in the case of a read miss; The cache block to be rewritten is divided into the first sectors of the disk area to be transferred to the stem corresponding to the sector next to the sector number read by the sector number reading means, and the cache block is operated for each divided area. Cache operation specification information j1 that generates specification information and includes, as a transfer start cache address, a cache address corresponding to the sector next to the sector number read by the sector number reading means. a cache operation specification information generation means for sequentially storing the cache operation specification information in the cache operation specification information storage means; and a data transfer means for sequentially retrieving the cache operation specification information stored in the cache operation specification information storage means from the beginning and performing a data transfer operation based on this information. A magnetic disk control device comprising: Not done. It will be done.

Claims (1)

[Claims] In a magnetic disk control device having a built-in cache memory, cache operation specification information storage means for storing cache operation specification information consisting of a transfer start cache address, the number of transfer sectors, and a data transfer direction control code;
A sector number reading means for reading the sector number in the ID field of the disk at that time in the case of a read miss, and generating the cache operation specification information based on the contents of the disk access request from the host system and the directory search results, and specifying the cache operation. A means for storing information in an information storage means, which, in the case of a read miss, stores a cache block to be rewritten with the sector next to the sector number read by the reading means and the first sector and last sector of the disk area to be transferred to the host system. The cache operation designation information is generated for each divided area, and the cache operation designation information whose transfer start cache address is the cache address corresponding to the sector next to the sector number read by the reading means is the first cache operation designation information. cache operation specification information generation means for storing a group of cache operation specification information in the cache operation specification information storage means; and cache operation specification information generation means for storing a group of cache operation specification information such as: 1. A magnetic disk control device comprising: data transfer means for performing a data transfer operation.