JPS61272801A - Output limiting method for thermal power plant - Google Patents

Abstract

PURPOSE:To prevent the response delay by holding an output control signal in a set value though a repeating command exceeds a set output upper or lower limit and controlling the output control signal immediately from a set value position when the repeating command is restored between upper and lower limits again. CONSTITUTION:If a repeating command 1 falls to exceed an output lower limit set value 9, a subtractor 4 outputs a minus signal 5 of the difference because the repeating command 1 is smaller than an output control signal 3, and the output control signal 3 from an integrator 2 falls at a required change rate as shown by a dotted line thereby. Consequently, a lower limit operation switch 15 is switched to the sidfe of a contact a' by a turn-on signal 21 from a high signal selector 11 when the output control signal 3 exceeds the output lower limit set value 9. Then, an earthed '0' signal 18 larger than the minus signal 5 is selected by the high signal selector 19 and is inputted to a multiplier 6. Thus, a signal 8 from the multiplier 6 becomes '0', and the integrator 2 is held in the value of the output control signal, namely, the output lower limit set value 9. If the repeating signal 1 resins in this state, the holding state is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output limiting method in a thermal power plant.

[Conventional technology]

In recent thermal power plants, in order to balance the load on the system, the load band is divided into H band/L band and the system is operated, and output is restricted in accordance with this system operation.

Figure 3 shows an example of a conventional output limiting circuit, in which a central power supply command (hereinafter referred to as "intermediate supply command") (1) or a station command is input, and an output control signal (3) from an integrator (2) is input. A subtracter (4) is provided which performs subtraction, and an output change rate setting value (7) is applied to the command deviation signal (5) resulting from the subtraction by the subtracter (4) via a multiplier (6). An output control signal (3) having a desired rate of change is outputted via an integrator (2) by the command deviation change rate correction signal (8) obtained by the multiplication. The output control signal (3) is also controlled by a high signal selector αυ for inputting the output lower limit set value (9) and holding the output command (11) so that it does not become smaller than that value, and an output upper limit set value a. A low signal selector α is used to input the output command aI and hold it so that it does not become larger than that value.
1, so that the upper and lower limits of the output command α1 are limited.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional system has the following problem in control, which causes a delay in response.

Fig. 4 is a diagram illustrating the conventional method of limiting output in the case of the output lower limit.The intermediate supply command (1) (solid line) changes in steps as shown in the figure, and this intermediate supply command + 1 ) decreases beyond the output lower limit setting value (9), the output control signal (3) (dotted line) also decreases at the required rate of change in accordance with the intermediate feed command (1). If the output control signal (3) exceeds the output lower limit setting value (9) and falls, the intermediate feed command (1) will again change to the output lower limit setting value (9).
), the output control signal (3) will increase at the required rate of change from the lowest position, so the output control signal (3) will exceed the output lower limit setting value (9) and the output will not actually be output. There is a problem in that there is a time delay by the required time (t) before the command a1 is increased. Also, when the intermediate feed command (1) rises above the output upper limit set value az and then falls, a delay in control response occurs as described above.

The present invention has been made in view of the above circumstances, and when the intermediate supply signal fluctuates beyond the set upper or lower limit of the output, the output control signal is held at the set value, and the intermediate supply signal changes to the set value. The purpose is to prevent delay in control response by immediately controlling the output control signal from the held set value when the set value returns to within the set upper and lower limits. The invention attempts to solve the above technical problem,
When outputting an output control signal via an integrator using a signal obtained by multiplying the change in the increase or decrease signal based on fluctuations in the intermediate feed command by the output change rate setting value via a multiplier, the intermediate feed When the command exceeds the set upper or lower limit of the output, the signal from the multiplier is set to 0, the output control signal from the integrator is held at the set upper or lower limit value, and the intermediate feed signal is An output limiting method in a thermal power plant, characterized in that the output control signal is controlled from a hold state by immediately returning the signal from the multiplier when the output returns to within the set upper and lower limits. It is.

[For production]

Therefore, in the present invention, the output control signal is held at the set value even if the intermediate feed command exceeds the set upper or lower limit of output, and the output control signal is set when the intermediate feed command returns to within the upper and lower limits. By controlling immediately from the value position, delay in control response can be prevented.

〔Example〕

FIG. 1 shows an embodiment of the present invention applied to the output limiting circuit shown in FIG. 3, and parts given the same reference numerals in the figure represent the same parts.

As shown in the figure, a hold circuit I is provided between the subtracter (4) and the multiplier (6). The hold circuit a◆ converts the command deviation signal (5) from the subtracter (4) to the lower limit contact (α
) and (b) to the multiplier (6), and also inputs the signal (5) from the subtracter (4) respectively, and also inputs the 0 (zero) signal from the ground αD. It is equipped with a high signal selector a9 and a low signal selector (to) which are respectively input to the high signal selector a9, and the output of the high signal selector α■ is input to the lower limit operation switch (to) through a contact chamber or The output of the low signal selector (to) is connected to the contact point (b) of the upper limit operation switch QE9.
) so that they can be connected to each other. Further, the lower limit operation switch α outputs an ON signal when the output control signal (3) becomes smaller than the set value (9) in the high signal selector αυ and the set value (9) is selected; Switching is performed by inputting a switching operation signal 0υ that outputs an OFF signal when the output control signal (3) rises and is selected, and the upper limit operation switch αG is also connected to a low A switching operation signal 4 from the signal selector 0 is input to perform switching.

If the output control signal (3) is output as the output lower limit setting value (9), the lower limit operation switch α is turned off and the upper limit operation switch
19 are switched to the contact (α) and (6) sides (solid line state), respectively, so the signal (5) from the subtracter (4) is directly introduced to the multiplier (6) to set the output change rate. The command deviation change rate correction signal (8) is multiplied by the value (7), and the output control signal (
3) is output.

In this state, as shown in Figure 2, the intermediate supply command (1) is issued.
If the value exceeds the output lower limit setting value (9) and falls, the subtractor (4) outputs a negative signal (5) for the difference because the intermediate feed command (1) is smaller than the output control signal (3). Therefore, the output control signal (3) from the integrator (2) falls at the required rate of change as shown by the dotted line.

When the output control signal (3) exceeds the output lower limit set value (9), the lower limit operation switch α1 is switched to the contact open side by the ON signal Qυ of the high signal selector I. Then, the high signal selector selects the grounded 0 signal α, which is larger than the negative signal (5), and 8 is input to the multiplier (6) for the 0 signal. As a result, the signal (8) from the multiplier (6) becomes 0, so the integrator (2) is the value of the output control signal (3) at that time, that is, the output lower limit setting value (9).
◇From this state, the intermediate supply signal (1
) rises stepwise as shown in Figure 2, this time the intermediate feed signal (1) is larger than the output control signal (3), so the subtractor (4) calculates the positive signal of the difference. (5)
For this purpose, the high signal selector (11) selects the positive signal (5) that is greater than the 0 signal (11) and outputs it to the multiplier (6), so the integrator (2) immediately increases the output control signal (3) from the held state.At the same time, since the high signal selector αυ selects the output control signal (3), its OFF signal cjD increases the lower limit operation. The switch α1 is switched to the original contact (,) side.In this way, the output command operator is controlled without causing a response delay.

In addition, although the case of output lower limit limit has been explained above, in the case of output upper limit limit, the low multiple ゛′ selector (
1), upper limit operation switch (1e and switching operation signal (to)
Similarly, it is possible to prevent response delay from occurring.

〔Effect of the invention〕

As described above, according to the output limiting method in a thermal power plant of the present invention, even if the intermediate supply command fluctuates beyond the set upper limit or lower limit, the output control signal is set to the output upper limit set value or the output lower limit set value. When the intermediate feed command returns to the upper and lower limits, the output control signal is immediately controlled from the set value position, thereby eliminating control response delays and improving controllability. It can produce excellent effects.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an output limiting circuit showing an embodiment of the present invention, FIG. 2 is a graph showing the case of output lower limit limitation according to the present invention, and FIG. 3 is an example of a conventional output limiting circuit. The explanatory diagram shown in FIG. 4 is a graph showing the case of output lower limit restriction according to the conventional method. (1) is the intermediate feed command, (2) is the integrator, (3) is the output control signal, (4) is the subtractor, (5) is the command deviation signal, (6
) is a multiplier, (7) is an output change rate set value, (8) is a command deviation change rate correction signal, (9) is an output lower limit set value, (II
is the output command, αυα9 is the high signal selector, α is the output upper limit set value, (13 (1) is the low signal selector, I is the hold circuit, a is the lower limit operation switch, αQ is the upper limit operation switch, (Iη is ground, or 0 signal, and Qυ(2) is 0, which indicates switching operation signal.

Claims (1)

[Claims] 1) When outputting an output control signal via an integrator using a signal obtained by multiplying the change in the increase and decrease signals based on fluctuations in the intermediate feed command by the output change rate setting value via a multiplier, When the intermediate feed command exceeds the set upper or lower limit of the output, the signal from the multiplier is set to 0, the output control signal from the integrator is held at the set upper or lower limit value, and the intermediate feed An output limiting method in a thermal power plant, characterized in that when the signal returns to the set upper and lower limits, the signal from the multiplier is immediately returned to control the output control signal from a hold state.