JPS6127190Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial field of application] The present invention relates to a charge transfer device, and particularly to a so-called charge transfer device that stores and transfers information charges in the bulk of a storage medium.
BCCD (Bulk Charge Coupled Device)
Regarding.

[Conventional technology]

A typical charge transfer device is a CCD device with a MOS structure.In this device, charges containing information are accumulated and transferred at the interface between an oxide film and a silicon semiconductor layer, so the charge transfer device is based on a charge that exists at the interface between the oxide film and the silicon semiconductor layer. This decreases the transfer efficiency and causes noise. In order to eliminate such drawbacks, a so-called BCCD device has been proposed in which information charges are stored and transferred in the bulk of a semiconductor crystal.

FIG. 1 shows a partial cross section of the device. As shown in the figure, a high-resistance P-type epitaxial semiconductor layer 2 is provided on a low-resistance N-type semiconductor substrate 1, and after growing an oxide film 3 thereon, a plurality of gate electrodes G ₁ are formed. , G ₂ , ... are arranged in an array. For example, two layers φ as shown in FIG.
Transfer of majority carriers or holes is effected in the epitaxial layer 2 by applying clocked voltages of ₁ and φ ₂ to the gate electrodes, respectively.

An outline of the operating principle in this case will be explained with reference to FIGS. 3 and 4. For example, when a predetermined gate electrode (G ₁ ) is in an unbiased state, that is, at a low level (L)
As shown in the schematic diagram in Figure 3A, the energy band in this state is the potential distribution when there is a fixed negative charge and a positive free carrier in the P-type layer in a thermal equilibrium state. It is shown in FIG. 7A. Here, Vbi is a built-in potential difference (diffusion potential difference) at the PN junction, and depending on the concentration of P type, the SiO ₂ film and the silicon interface are in a depleted state or a state close to it.

Next, when a high level (H) bias is applied to the gate electrode (G ₁ ), the oxide film. The silicon interface is strongly depleted, and holes, which are free carriers, are pushed away from the interface, and majority carriers are driven into the bulk. Therefore, more electrons, which are minority carriers, appear at the interface, and the energy band at the silicon interface bends downward, while the concentration on the N-type silicon substrate side is high, so there is no bias effect, so the energy band becomes It will bend as shown in Figure 3B. Therefore, when a positive free charge is deliberately injected into the bulk, potential energy is tracked and stored at a minimum location, ie, a location at a depth of W from the interface. The potential distribution at this time is shown in FIG. 4B. As a result, by applying a two-phase clocked voltage as shown in FIG. 2, the potential distribution along the channel region, which is the accumulation region corresponding to the depth of W from the oxide film-silicon interface, can be changed as shown by the dotted line in FIG. 4
It becomes possible to accumulate positive free charges, which are majority carriers, in the deep part of the valley as shown in the figure. Therefore, charge is transferred by shifting these peaks and valleys.

[Problem that the invention attempts to solve]

In such a BCCD, there tends to be a region around the gate electrode that is not sufficiently affected by the gate bias, and the change in potential cannot be large enough, so that the charge that should be transferred escapes from these peripheral regions. , which is a cause of a decline in transfer efficiency.

[Means for solving problems]

An object of the present invention is to provide a charge transfer device with good transfer efficiency by eliminating the escape route for charges due to the portions around the gate electrode that are not affected by bias.

The charge transfer device of the present invention includes a semiconductor substrate, a semiconductor layer provided on one main surface of the substrate and forming a PN junction with the substrate, and a separate storage area in the semiconductor layer for carrying carriers representing predetermined information. This is a so-called BCCD device including a gate electrode provided on the main surface of a semiconductor layer to control transfer along the information carrier, and a gate electrode provided on the main surface of the semiconductor layer to control transfer along the information carrier. The present invention is characterized in that a row of recesses is formed, and a gate electrode is buried in this row of recesses.

[Example of idea]

The present invention will be explained below with reference to the drawings.

FIG. 5 shows the structure of one embodiment of the present invention, where A is a sectional view taken along line A-A in plan view C, and B is a cross-sectional view taken along line A-A in plan view C.
B is a sectional view taken along line C, and C is a plan view. For example, high concentration N
A low concentration P-type silicon layer 2 is formed on the negative main surface of a type silicon substrate 1 by epitaxial growth,
On the main surface of this epitaxial layer 2, there are two approximately parallel rows of vertical holes, that is, recesses 11 to 15 and 2.
1 to 25 are each formed by a well-known etching method. Then, an oxide film of a predetermined thickness is formed on the surface including the recessed portions to form the gate insulating film 3. After that,
A common gate electrode _G1 is deposited within adjacent and opposing recesses of both rows of recesses, for example, the recesses indicated by 11 and 12, and on the surface of the silicon layer between these recesses. Recesses 12 and 22, 13 and 23, 14 and 2
Similarly, common gate electrodes G ₂ , G ₃ , G ₄ , .

In such a configuration, the silicon layer 2 immediately below each recess is always in a completely depleted state regardless of the gate bias state shown in FIG. 2, and therefore free charges cannot escape from that part. . Therefore, the storage and transmission region is surrounded by the peaks of potential between the two rows of opposing recesses and the PN junction surface, making it possible to transfer almost all of the stored charge, thereby improving transfer efficiency.

FIG. 6 shows a plan view when the present invention is applied to a BBD (bucket brigade device) structure, and parts equivalent to those in FIG. 5 are designated by the same reference numerals. In the figure, highly concentrated P-type impurity regions 5, 6, 7, and 8 reaching the channel depth are formed in the epitaxial layer between each gate electrode to serve as source/drain regions. The operating principle is the same as that shown in FIG.

In the above, the substrate is N type and the shrimp layer is P type.
However, the conductivity types may be opposite to each other, and the number of gate electrodes and the number of recesses are not limited to those in the embodiment. Furthermore, it is also possible to have a so-called continuous groove structure instead of individual recesses.

[Effect of idea]

As described above, according to the present invention, it is possible to significantly improve the transfer efficiency of a so-called BCCD device in which the storage and transfer region is in the bulk, the noise margin is also increased, and a high-performance charge transfer device can be obtained. .

[Brief explanation of the drawing]

Figure 1 is a partial sectional view of a conventional BCCD, Figure 2 is a gate bias waveform diagram for the device shown in Figure 1, and Figure 3 is a diagram of the gate bias waveform for the device shown in Figure 1.
The figure is a schematic energy band diagram for explaining the operation of the device in Figure 1, where A is a non-biased state and B is a non-biased state.
4 is a potential distribution diagram for explaining the operation of the device shown in FIG. Figure 5 is a diagram showing an embodiment of the present invention, and A is A in the plan view C.
-A sectional view, B is a BB sectional view of plan view C,
C is a plan view, and FIG. 6 is a plan view of another embodiment of the present invention. Explanation of symbols of main parts, 1...Semiconductor substrate, 2
...Epitaxial layer, 3...Oxide film, 11-1
5, 21-25... recess, G... gate electrode.

Claims (1)

[Scope of utility model registration request] a semiconductor substrate, a semiconductor layer provided on one main surface of the semiconductor substrate and forming a PN junction with the substrate, and a carrier representing predetermined information to be transferred along storage regions separated from each other in the semiconductor layer. A charge transfer device including a gate electrode provided on a main surface of the semiconductor layer, the charge transfer device being provided substantially parallel to each other on the main surface of the semiconductor layer with the storage region sandwiched between the ends of the gate electrode. 1. A charge transfer device comprising two rows of recesses each comprising one or more recesses, the gate electrode being buried in each row of recesses.