JPS61270915A - Off gate circuit of gto - Google Patents

Off gate circuit of gto

Info

Publication number
JPS61270915A
JPS61270915A JP60112107A JP11210785A JPS61270915A JP S61270915 A JPS61270915 A JP S61270915A JP 60112107 A JP60112107 A JP 60112107A JP 11210785 A JP11210785 A JP 11210785A JP S61270915 A JPS61270915 A JP S61270915A
Authority
JP
Japan
Prior art keywords
gto
gate
capacitor
turn
pulse transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60112107A
Other languages
Japanese (ja)
Inventor
Yukinori Tsuruta
幸憲 弦田
Kosaku Ichikawa
耕作 市川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60112107A priority Critical patent/JPS61270915A/en
Publication of JPS61270915A publication Critical patent/JPS61270915A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/73Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents

Landscapes

  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To set a dynamic frequency high in frequency range by providing plural circuits to discharge a stored charge in a capacitor and to make flow an off-gate current of a gate turn-off thyristor (GTO), and attaining alternate operation. CONSTITUTION:When an input signal S1 is supplied, an FF10 is inverted, a terminal S2 goes to an H level and a transistor (TR) 5a is turned on for a prescribed time via a waveform shaping circuit 9a, and the electric charge charged in a capacitor 4a is discharged through an input winding N2a of a pulse transformer. Thus, an off-gate current is fed to the gate of the GTO 1 via diodes 7a, 7b from the output winding of the pulse transformer to turn off the GTO 1. The electric charge in the capacitor 4a is discharged by supplying the input signal S1 after the GTO 1 is turned on the turn off the GTO 1, plural off-gate circuits are provided to apply alternate driving thereby allowing sufficient charging time of the capacitor, the the off-gate current is supplied stably and the dynamic frequency can be set at a high frequency range.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、ゲートターンオフテイリスタ(以下、GTO
と略す)を制御するオフゲート回路の改良(二係り、特
(二、オフゲート電流を供給するコンデンサの充電のた
め(二要する時間から決まる動作周波数の限界を回路の
多重化(二より、上昇させる効果のあるGTOのオフゲ
ート回路(=関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field of the invention] The present invention relates to a gate turn-off tiller (hereinafter referred to as GTO).
Improvement of the off-gate circuit (2) to control the off-gate current (2), especially (2) the effect of increasing the operating frequency limit determined by the time required for charging the capacitor that supplies the off-gate current (2) A certain GTO off-gate circuit (= related to.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

GTOのオフゲート回路として、従来よシ、パルストラ
ンスを使用したオフゲート回路として、第4図(:示す
回路が用いられている。GTO素子素子l−パルストラ
ンス2久2 ートへ接続され、他端は、ダイオード7−、7bを介し
て、そのカソード(二接続される。ゲート電源3は、ダ
イオード6を介して、パルストランス2の1次巻線N1
の一端(二接続され、ゲート電力を供給する。1次巻腺
Nlの他端は、1次巻線N,の一端およびコンデンサ4
の一端と接続される。1次巻線Ntの他端は,トランジ
スタ5を介して、コンデンサ4の他端、ゲート′蝋源3
のマイナスat=接続される。第5図ia)は、第4図
の回路の動作時(二おける谷部波形である。(I)は、
コンデンサ4の両端の電圧波形、(II)はパルストラ
ンス2の2次巻線N3より出力するオフゲート電流; 
(1)は1.GTO素子lのゲート・カソード間電圧波
形である。時刻t0よシ、トランジスタ5(二ペース信
号が供給されると、トランジスタ5がオンするととこよ
り,コンデンサ4の図示極性■。。に充電された電荷は
、パルストランス2の1次巻線N1,トランジスタ5を
介して放電し、2次巻線N、 I:電圧を鋳起Tる。 
2次巻線Nsからの出力電流IQffは、図示しない゛
オンゲート回路のオンゲート電流の流れ込みを防止する
ダイオード7、.7bを介して、 GTO素子素子力ソ
ードからゲートへ負の電流として出力される。時刻to
からtx tでの時間TOffの間、トランジスタ5に
ベース信号が与えられ、トランジスタ5はオンしている
。時間TOFF経過後、トランジスタ5が時刻11でオ
フすると、パルストランス2の励磁電流は、時刻t8か
ら時刻tよまでの時間T6の間、ゲート電源3のプラス
側、ダイオード6.1次巻線N。
Conventionally, as an off-gate circuit of GTO, the circuit shown in Fig. 4 (:) is used as an off-gate circuit using a pulse transformer. is connected to its cathode (two) via diodes 7- and 7b.The gate power supply 3 is connected to the primary winding N1 of the pulse transformer 2 via the diode 6.
The other end of the primary winding Nl is connected to one end of the primary winding N and the capacitor 4.
connected to one end of the The other end of the primary winding Nt is connected via the transistor 5 to the other end of the capacitor 4 and to the gate' wax source 3.
minus at=connected. Figure 5 ia) is the trough waveform at the time of operation of the circuit in Figure 4 (2). (I) is
The voltage waveform across the capacitor 4, (II) is the off-gate current output from the secondary winding N3 of the pulse transformer 2;
(1) is 1. It is a voltage waveform between the gate and cathode of GTO element 1. At time t0, the transistor 5 (when the two-pace signal is supplied, turns on the transistor 5, and the electric charge charged in the capacitor 4 is transferred to the primary winding N1 of the pulse transformer 2, It discharges through the transistor 5 and generates a voltage in the secondary windings N and I.
The output current IQff from the secondary winding Ns is passed through diodes 7, . 7b, a negative current is output from the GTO element power source to the gate. time to
During the time Toff from txt to txt, the base signal is applied to the transistor 5, and the transistor 5 is turned on. After the time TOFF has passed, the transistor 5 is turned off at time 11, and the exciting current of the pulse transformer 2 is applied to the positive side of the gate power supply 3, the diode 6, and the primary winding N during the time T6 from time t8 to time t. .

、コンデンサ4、ゲート″[源3のマイナス側の電路で
流れ、コンテン?4の再充電を行う。この時の等価回路
を第5図(b) t:、示す。   ゛近年、GTOを
使用した変換装置で、PWM制御等のGTOのスイッチ
ング周波数を高くするニーズがめる。この場合、前記し
たオフゲート回路のコンデンナ充電時間T6とオフ電流
出力時間−の時間で動作周波数の限界があった。又、コ
ンデンサの充電が完了しないうち6二、オフ電流出力信
号がでて、トランジスタ5がオンすると、充分なゲート
電流Iouが出力されず、GTO素子素子力−ンオフ失
敗で破損するという故障も発生する。
, the capacitor 4, the gate"[flows in the negative side circuit of the source 3, and recharges the content 4. The equivalent circuit at this time is shown in Figure 5(b). ゛In recent years, GTO has been used. In the converter, there is a need to increase the switching frequency of the GTO for PWM control, etc. In this case, there is a limit to the operating frequency due to the capacitor charging time T6 of the off-gate circuit and the off-current output time. If the off-current output signal is output and the transistor 5 is turned on before charging is completed, sufficient gate current Iou will not be output, and a failure may occur in which the GTO element fails to turn on or off and is damaged.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記点(二mみてなされたものであシ
、オフゲート回路の一部又は、全部を多重化して構成す
ること(二より、動作周波数の限界を上昇させることが
出来るGTOのオフゲート回路を提供することにある。
The purpose of the present invention is to construct a part or all of the off-gate circuit by multiplexing the above-mentioned point (2). The purpose is to provide an off-gate circuit.

〔発明の概要〕[Summary of the invention]

本発明は前述のオフゲート回路を少なくと%2組以上設
け、順次駆動して、所定の出力周波数を得るようC二し
たもので、前記した、コンデンサの充電時間ζ;よる動
作周波数の限界が1回路動作の従来例の2倍に出来るよ
うにしたものである。
In the present invention, at least two or more sets of off-gate circuits are provided, and they are sequentially driven to obtain a predetermined output frequency. The circuit operation is twice that of the conventional example.

〔発明の実九例〕[Nine examples of inventions]

第1図(二本発明の一実j例を示す。IJ14図と同一
あるいは同相当部分C;は、同一符号と酢字a。
Figure 1 (2) shows an example of the present invention. Portions C that are the same or equivalent to those in Figure IJ14 are the same reference numerals and the letter a.

bを付して区別し、その説明を省略する。クリップフロ
ップlOは入力信号S、を出力(N号Sza * So
b l二振〕分け、波形整形回路91t 9.、を二よ
り、信号S。。
b is added to distinguish them, and the explanation thereof will be omitted. The clip-flop lO outputs the input signal S (N number Sza * So
waveform shaping circuit 91t 9. , from the second, the signal S. .

Ssbを出力し、トランジスタ5□l 5bを1800
位相をずらせて駆動するように構成している。
Output Ssb and set transistor 5□l 5b to 1800
It is configured to drive with a phase shift.

次C二、本発明の作用を第1図および動作時の各部波形
と48号のタイムチャートを示す第2図を参照して説明
する。クリップフロップ10の入力信号Stとして、G
TOのスイッチング周波数(=対応するクロックパルス
が供給される。7リツプ70ツブlOの出力は、Sea
 * 13*b 11−示す反転信号となり、波形整形
回路9at9bの入力信号となる。波形整形回路9□9
bの出力は、Ssa+Ssbのオフゲートパルス幅を決
める方形波パルスを出力し、その位相は互い(二180
’ずれたパルス信号となる。信号Ssaはトランジスタ
51、信号Ssbはトランジスタ5bのベース信号とな
υトランジスタを駆動する。互い(=180°ずれた位
相で駆動されたトランジスタ5atSbのスイッチング
ζ二よシ、互い(二、ダイオード7、。
Next, the operation of the present invention will be explained with reference to FIG. 1 and FIG. 2 showing waveforms of various parts during operation and a time chart of No. 48. As the input signal St of the clip-flop 10, G
The switching frequency of TO (=corresponding clock pulse is supplied. The output of 7 lip 70 lip IO is Sea
*13*b 11- becomes an inverted signal and becomes an input signal of the waveform shaping circuit 9at9b. Waveform shaping circuit 9□9
The output of b outputs a square wave pulse that determines the off-gate pulse width of Ssa+Ssb, whose phases are mutually (2180
'The pulse signal will be shifted. The signal Ssa drives the υ transistor, which is the base signal of the transistor 51, and the signal Ssb is the base signal of the transistor 5b. Switching ζ of transistors 5atSb driven with phases shifted by 180° from each other, diodes 7, .

7b * 8@e 8bを介して、並列(二結線された
パルストランス2..2bの出力巻線Nsa + NR
b巻線から合成してGTO1のゲートへ供給されるオフ
ゲート電流l0ffの出力周波数は、位相が180′ず
れた駆動をする2重化回路C;よシ、1回路のコンテン
?41.および4゜の充*1=要する時間の3A(二と
ることができるため、従来の2倍まで動作周波数を上昇
させることができる。
7b * 8@e Through 8b, the output winding Nsa + NR of the parallel (two-wired pulse transformer 2..2b)
The output frequency of the off-gate current l0ff, which is synthesized from winding B and supplied to the gate of GTO1, is the content of one circuit in duplex circuit C, which drives with a phase shift of 180'. 41. And 4° charge * 1 = required time of 3A (2) can be taken, so the operating frequency can be increased to twice that of the conventional one.

2重化して構成する回路を、パルストランスを1体化し
て第3図のよう(=構成してもよい。動作は、第1図と
同様である。この場合、パルストランス2は、単一回路
の構成時よりも、印加される電圧時間積がpa71Fl
するため、コンデンサ4at41iが過充電さnるため
、充電電圧を抑制するように、第3図ダイオード12.
 、12.、を谷々、コンデンサも。
The circuit configured by duplication may be configured as shown in Fig. 3 by integrating the pulse transformer.The operation is the same as in Fig. 1.In this case, the pulse transformer 2 is configured as a single circuit. Compared to when the circuit was configured, the applied voltage time product is pa71Fl.
Therefore, since the capacitor 4at41i is overcharged, the diode 12. in FIG. 3 is connected to suppress the charging voltage.
, 12. , the valley, and the capacitor too.

4−と補助′礒源310間(二接続し、過充電分′f:
吸収するよ51;#成している。補助電源31の代シに
ツェ′ナーダイオードを用いてもよい、又、第1図と同
様(二、少なくともaJt化以上並列接続し、順次、駆
動して、オフゲート出力を得るように構成してもよい。
4- and the auxiliary power source 310 (two connections, overcharge):
I'm going to absorb it 51; A Zener diode may be used in place of the auxiliary power supply 31, or, as shown in FIG. Good too.

又、第4図の1次側回路を複数組設けるようパルストラ
ンスな構成してもよい。
Further, a pulse transformer configuration may be adopted in which a plurality of sets of the primary side circuits shown in FIG. 4 are provided.

〔発明の効果〕〔Effect of the invention〕

以上、本発明(=よれば、オフゲート回路を多重化して
構成すること(二よシ、動作周波数を高くできる効果の
あるオフゲート回路を提供することができる。
As described above, according to the present invention, by configuring off-gate circuits by multiplexing them, it is possible to provide an off-gate circuit that is effective in increasing the operating frequency.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本開明の一実施例を示す構成図、第2図は第
1図の動作を説明するための各部説形を示したタイムチ
ャート、第3図は本発明の他の芙施例を示す構成図、第
4図は従来のオフゲート回路の構成図、第5図は第4図
の動作を説明する比めの各部の波形図でめる。 1・・・GTOl  2,2a*2b・・・パルストラ
ンス、3・・・ゲート電源、  4* 4m + 4b
・・・コンデノサ、5 + 5m + sb・・・トラ
ンジスタ、  6 * 6m + 6b・・・ダイオー
ド、  7□7b * 8a + 8b・・・ダイオー
ド、  9a*9b・・・波形整形回路、 10・・・
フリップフロッグ、114゜11b・・・ダイオード、
 12. 、12b・・・ダイオード(7317)代理
人 弁理士 則 近 憲 佑(ほか1名)第1図 第2図
FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing a description of each part to explain the operation of FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 4 is a block diagram showing an example of the configuration, FIG. 4 is a block diagram of a conventional off-gate circuit, and FIG. 5 is a waveform diagram of various parts for comparison to explain the operation of FIG. 4. 1...GTOl 2,2a*2b...Pulse transformer, 3...Gate power supply, 4*4m + 4b
... Capacitor, 5 + 5m + sb ... Transistor, 6 * 6m + 6b ... Diode, 7□7b * 8a + 8b ... Diode, 9a * 9b ... Waveform shaping circuit, 10 ...・
Flip frog, 114°11b...diode,
12. , 12b...Diode (7317) Agent Patent attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)コンデンサに電荷を蓄積し、この放電により、オ
フゲート電流を出力するように構成したGTOのオフゲ
ート回路において、前記、オフゲート回路を少なくとも
2組以上設け、交互に駆動して所定の出力周波数を得る
ように構成したことを特徴とするGTOのオフゲート回
路。
(1) In a GTO off-gate circuit configured to accumulate charge in a capacitor and output an off-gate current by discharging the charge, at least two or more sets of the above-mentioned off-gate circuits are provided and driven alternately to achieve a predetermined output frequency. 1. A GTO off-gate circuit characterized in that it is configured to obtain a GTO off-gate circuit.
JP60112107A 1985-05-27 1985-05-27 Off gate circuit of gto Pending JPS61270915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60112107A JPS61270915A (en) 1985-05-27 1985-05-27 Off gate circuit of gto

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60112107A JPS61270915A (en) 1985-05-27 1985-05-27 Off gate circuit of gto

Publications (1)

Publication Number Publication Date
JPS61270915A true JPS61270915A (en) 1986-12-01

Family

ID=14578323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60112107A Pending JPS61270915A (en) 1985-05-27 1985-05-27 Off gate circuit of gto

Country Status (1)

Country Link
JP (1) JPS61270915A (en)

Similar Documents

Publication Publication Date Title
KR100729058B1 (en) External driving circuit for bridge type synchronous rectification
JPH04364359A (en) High-efficiency power converter with synchronous switching system
JPH05252730A (en) Control circuit for semiconductor switch
US6744647B2 (en) Parallel connected converters apparatus and methods using switching cycle with energy holding state
US5793628A (en) Multi-phase pulse-width-modulation power converter
US4805078A (en) Switched power supply for generating a plurality of isolated power voltage for a pulse converter
US6489730B2 (en) Discharge-lamp illumination circuit
US6661209B2 (en) Leading edge modulator for post regulation of multiple output voltage power supplies
JPS61270915A (en) Off gate circuit of gto
US3496444A (en) Voltage converter circuits
JPH1146479A (en) Switching power supply
JP2002247839A (en) Dc-dc converter and method of adjusting the same
JP3687424B2 (en) Pulse power supply
CN218514276U (en) Bootstrap capacitor voltage-stabilizing auxiliary circuit and power converter with same
JPH1198829A (en) Switching power source
JPH0624430B2 (en) DC-DC converter
JPH0746858A (en) Switching power supply
SU1690125A1 (en) Dc voltage converter
JP2996065B2 (en) Bridge type inverter device
KR200337815Y1 (en) Output compensation circuit of trans
JPH04308464A (en) Power supply
JPS5910166A (en) Triple voltage booster circuit
KR200250640Y1 (en) Output compensation circuit of trans
JPH0662581A (en) Switching power source circuit
SU1272432A1 (en) Self-excited voltage inverter