JPS6126994A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the load capacity of a bit line, to speed up reading and to decrease the transient current of the bit line by providing a transfer gate intermitting the bit line in synchronizing with a sensor amplifier control signal. CONSTITUTION:When precharging is completed and a word line X rises in the condition where a bit line B, antis B and B' and the anti B' come to a power source potential VDD, a potential difference in accordance with data contents of a memory cell appears on the bit line. When a sensor amplifier control signal phis goes to ''H'', the potential difference is amplified by a sensor amplifier consisting of P type transistors P4 and P5, N type transistor N1 and N2, etc. In the midist of the amplification, a signal phiSB synchronous with the signal phis goes to ''H'' to turn off transfer gates T1 of P type transistors P00 and P01, N type transistors N00 and N01, etc.; and the bit line B, and its anti B' are separated. Thus the load capacity of the sensor amplifier is reduced, and data is read out a high speed. Simultaneously, a transient current applied to the transistor of the sensor amplifier can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to complementary MO3 field effect transistor devices.

Conventional configuration and its problems C1 MOS static R used in semiconductor memory
For example, when an AM sense amplifier is an internally synchronized type, the high level of the bit line is the power supply potential (V, D) and the low level is the ground potential (GND), so a latch type sense amplifier as shown in Figure 1 is generally used. It will be done. In Figure 1,
First, when the bit line precharge signal φ becomes low level, the P-channel type MOS transistor P1. P2I
P3 is turned on and bit lines B and B are precharged to the vDD potential. When φ becomes high level again, precharging is completed. Then, when word line X is selected and its potential rises to the I level, n-channel MOS transistor N6. N7 turns on and this word line and column line Y
The data of the memory cell selected by
It appears on B as a potential difference.

When the potential difference between bit lines B and H becomes large to a certain extent, the sense amplifier turns on and starts reading. The memory side of the bit lines B and B to the sense amplifier will be referred to as the input signal line of the sense amplifier. here,
The sense amplifier control signal φ8 in FIG. 1 remains at a low level during the precharge period and the period when the data in the memory cell appears as a sufficient potential difference between the bit lines B and B to the n-channel M, OS. Transistor N3 is O
The sense amplifier does not operate due to the FF width. Therefore, φ
When the 8 signal is at a high level, the sense amplifier is turned on and starts operating, and the data is amplified.

In this way, the bit lines B and B, which have been precharged to the same potential by the signal φ, generate a potential difference by reading data, and the read data is amplified by the sense amplifier controlled by the sense amplifier control signal φ8. is transmitted on the output signal line of the sense amplifier and latched by the data latch circuit. Here, the output signal line refers to the latch circuit side with respect to the sense amplifiers of bit lines B and B.

In the series of data read operations described above, Pino) M
The load capacitance of B and B depends on the length of the bit line at the sense amplifier dimension, and the longer the length, the larger the resistance component, and the resistance
Since the capacitance product becomes large, this becomes an obstacle to high-speed reading. However, as the load capacitance of the bit line increases, it is necessary to set a sufficient timing margin for the timing of the sense amplifier control signal φ8, which also becomes an obstacle to speeding up. The timing setting at this time is bit line B
, B is to adjust the sense amplifier control so that the sense amplifier operates after a certain amount of potential difference occurs between the two terminals.

Therefore, as the degree of integration of semiconductor memories increases, the load capacitance of bit lines inevitably increases.
High-speed readout is becoming more difficult with the extension of bit lines, and it is necessary to increase the speed while maintaining sufficient timing margin on other circuits, including controlling the charging and discharging of word lines and other circuit wiring. This poses a major problem in circuit technology.

Object of the Invention The present invention provides a semiconductor memory that reduces the load capacitance of the focus line in a sense amplifier of a semiconductor memory, enables faster data reading of memory cells, and reduces transient current of the bit line. The purpose is to provide.

Structure of the Invention The present invention has a structure in which a transfer gate that operates in synchronization with a 1'-conductor sense amplifier (operated by a signal φ5 controlled by a sense amplifier control circuit) is connected to the input or output signal line of the sense amplifier. have.

The above-mentioned Drasfage H-1 is composed of at least one conductivity type MoS field effect transistor of P or N channel, with a φSR signal at the gate of the n channel type MOS transistor, and a φSR signal at the gate of the P channel type MO3) transistor. A signal φ13B which is an inversion of φ8B is input.

DESCRIPTION OF THE EMBODIMENTS A first embodiment of the present invention is shown in FIG. P channel M
OS transistor P4. P5 and n-channel MOS)
Transistor N,, N2. A latch type sense amplifier consisting of N3 and Pφφ, Pφ1 . This figure shows a circuit diagram of a transfer gate composed of Nφφ and Nφ1 double-conducting channel type MO3) transistors. In this embodiment, each of the sense amplifiers (memory cell (1111), B
FIG. 3 shows the potentials of ' and B' (on the sense amplifier side) and the timing of each signal. For ease of explanation, each signal is shown in a data read mode.

First, we will explain the relationship between each signal in terms of timing. In FIGS. 2 and 3, the precharge signal φ of the unswitched bit line becomes “LI+” and the transistor PI, p2
．． Before and after p3 turns on, the signal of φ8B is set to LI+
The transfer gate is turned on to electrically connect the bit lines BB and BB, and precharging is started in this state. (Region ■ in Figure 3) At this time, the sense amplifier sets the signal φ5 input to the transistor N3 in Figure 2 to "IL1' so that the operation is turned off almost simultaneously with the start of precharging. This timing state What is shown is the transition from area ■ to ■ in FIG.

Then, the bit lines B-B, B' and B' are precharged to completely the same potential and almost close to the power supply voltage7.
In the state of When the data content of the cell becomes a potential difference on the bit line, and the potential difference has increased to some extent, the signal φ8 controlled by the sense amplifier control circuit becomes "'H" again (region 3 in FIG. 3).

The sense amplifier turns on and starts amplifying the data on the bit line. When this data has been sufficiently amplified and the potential difference between the human lines B and B has increased to some extent (region 3 in Figure 3), φ8. becomes "w", and the transfer gate of the bit line (region T1 indicated by a dashed-dotted line in FIG. 2) is turned off.

As a result, the bit line B-B becomes the transfer gate,
l: It is disconnected from the sense amplifier, reducing the load on the sense amplifier. As a result, the potential difference of the human line B'·B/ on the sense amplifier side of the transfer gate rapidly increases, and data is amplified. This state is shown in the region (■) in FIG. Further, it can be seen that the potential difference between the electrically separated bit lines B and B does not become large after that.

In this way, reducing the load on the sense amplifier by disconnecting the human line at the transfer gate enables high-speed reading of memory cell data, and also reduces the logic amplitude of each of B-H, which reduces the precharge. It is also possible to reduce Ki by the same amount as in the previous example, thereby speeding up data access as a whole.

Further, the excess e-current flowing through the transistor due to the precharging of the hit line is reduced due to the disconnection of the hint line B1, and the shortening of the precharging time described above also has the effect of reducing the transient current.

The most noteworthy thing to note is that conventionally the power supply current had a strong frequency dependence in that the smaller the data write/read cycle time was, the sharper the increase in power supply current became. As the cycle time becomes smaller, the logic amplitude of bit line B-1 on the memory cell side becomes smaller, and precharging for the next cycle is performed before the discharge of bit line B-B by the memory cell is completed. As a result, the amount of precharge in each cycle can be reduced, resulting in a shorter cycle time, and even if the number of precharges increases by just 1 inch, the frequency dependence of the power supply current becomes extremely strong at high frequencies. Current does not increase much.

In this way, by improving the internal circuit configuration by providing transfer gates on the bit lines B and B of the memory cell of the sense amplifier, it is easy to speed up the access time of memory cell data and significantly reduce the power supply current. This is something that can be achieved.

-Also, in this embodiment, the transfer gate is used in an on state when reading data. It's Kade.
The timing at which the transfer gate turns off in read mode is determined by the fact that a certain potential difference occurs between the bit lines B' and 10'.
It is necessary to carry out this process with a sufficient potential difference so that there is no possibility that the potential relationship between the bit lines B' and B' will be reversed due to sense amplifier amplification. In this embodiment, the gate connected to the column address line Y that selects the bit line shown in FIG.
Transistor N4. The position of N5 may be on the input signal line side of the sense amplifier, that is, on the memory cell side.

A second embodiment of the present invention is shown in FIG. The difference in the first embodiment of the present invention is that in addition to the transfer gate circuit T1 in the sense amplifier shown in the first embodiment, there is also a data signal line 5'' on the data launch circuit side with respect to the bit line sense amplifier. This is because a transfer gate circuit T2 is further added to the output signal line of the sense amplifier.P
Changi Le MOS transistor Pφ2. Pφ4. N
Channel MO5 transistor Nφ3. In FIG. 4, for ease of explanation, the same symbols and numbers as in FIG. 2 are used for the transfer gate circuit T2 consisting of Nφ4.

In this embodiment, each control signal is φ8. silkworm. B and φ
FIG. 5 shows the timing and potential of 8□, and each signal is shown in read mode for ease of explanation.

A transfer gate circuit T2 is provided, and as shown in FIG. 5, the gate is turned on and off by a control signal φ8□ which is almost an inversion of the control signal JsB of the transfer gate circuit T. In FIGS. 4 and 5, the precharge φ of the bit line becomes II L II, and at the same time the precharge is started, the gate circuit T1 is turned on, the sense amplifier turns off the operation, and the signal line up to the sense amplifier is turned on. are all electrically connected. Here, the gate circuit T2 outputs a signal of φ8□ to “H” at the same time as the gate circuit T1 turns on.
”' and turns off. As a result, the column address line Y is selected and τ/.Even if the data latch circuit up to the buffer circuit and the output signal line of the cess amplifier are electrically connected, The oil in the gate circuit T2 is electrically disconnected.Therefore, in FIG. 4, precharging is performed only on the signal line up to the gate circuit T2.

Next, the precharge is completed and φ becomes “H”, and the sixth
In area 3 of the figure, the data of the memory cell is written to bits.

During this time, the gate circuit T is in the on state and the gate circuit T2 is in the off state. After the data in region 4f has been amplified as necessary and sufficiently, the gate circuit TI is turned off, and around the same time, the gate circuit T2 is turned on. By turning on the gate circuit T2, the data amplified by the sense amplifier propagates to the data latch circuit on the output signal line of the sense amplifier.

In reading data from such a series of memory cells, by adding the gate circuit T2, it is possible to further reduce the load capacitance of the signal line during precharging of the bit line, increasing the speed of precharging and further precharging. The power supply current can be reduced.

This makes it possible to shorten the precharge time (region 3 in FIG. 6), thereby realizing faster access time. Furthermore, when the sense amplifier amplifies the data appearing on the bit line after precharging, the gate circuit T
2 is off, in area 3 of FIG. 6,
Since the data latch circuit and the like are electrically disconnected on the output signal line of the sense amplifier, the load on the seventh amplifier can be reduced. This means that the data in the memory cell can be amplified at high speed, and a sufficient potential difference can be obtained during this time.

These effects are effective in addition to the effects when only the gate circuit T shown in the first embodiment of the present invention is present, and are effective in speeding up access time and reducing power consumption. Electrification will become a reality.

On the other hand, in write mode, φ is always L′′
It operates in the on state. In this embodiment, a transistor N4 has a gate connected to a column line Y for selecting a bit line shown in FIG. The position of N5 may be on the input signal line side of the sense amplifier.

Effects of the Invention As described above, the present invention reduces data access time by providing a sense amplifier in a semiconductor memory having a configuration in which a transfer gate is added that electrically connects and disconnects pit lines in synchronization with a sense amplifier control signal. Enables faster speeds and a significant reduction in power supply current. This can be easily achieved by a very simple circuit improvement of adding a transfer gate to the conventional sense amplifier configuration, or by a slight design modification of using a signal synchronized with the sense amplifier control signal. It is something.

[Brief explanation of the drawing]

FIG. 1 is a precharge circuit diagram including a conventional launch type sense amplifier circuit and memory cells, and FIG.
FIG. 3 is a precharge circuit diagram including the sense amplifier and memory cell of the first embodiment of the present invention, and FIG. 3 shows the timing of the control signal and the bit lines BB and B' in the first embodiment of the present invention.
4 is a diagram showing the potential of i', FIG. 4 is a precharge circuit diagram including a sense amplifier and memory cell of the second embodiment of the present invention, and FIG. 6 is a diagram of each control signal in the second embodiment of the present invention. It is a diagram showing timing and waveforms. p, ~3....- p channel type MOS,
N, ~N5. ．． -N channel type MOS, VDD・
...power supply potential, B・B, B'・i'・bit line, T
BiT2-,-) transfer gate circuit, Sφ~Pφ3
．． Nφφ~Nφ3--P, n-channel type MO3) transistor constituting the transferenide. Name of agent: Patent attorney Toshio Nakao et al. No. 16
CA Figure 2 Figure 13 Figure 4 Figure 5

Claims (2)

[Claims] (1) A p-type or n-type conductive channel type MOS that is activated by a signal synchronized with the sense amplifier control signal is placed on the input signal line of the sense amplifier that is activated by the sense amplifier control signal.
A semiconductor memory characterized in that a transfer gate formed of at least one field effect transistor is connected. (2) The semiconductor memory according to claim 1, wherein the transfer gate is connected to an input signal line of a sense amplifier and is further added to an output signal line of the sense amplifier.