JPS61269380A - Semiconductor device - Google Patents

Abstract

PURPOSE:To constitute a variable capacitance element, by arraying on one conductive type semiconductor substrate a plurality of opposite conductive type regions, a transistor, wiring layers and output terminals, and by varying the gate voltage of the transistor. CONSTITUTION:On a conductive type semiconductor substrate 5, capacitors 10, 30 as capacitance elements and a transistor 20 are formed, and an oxide film 6A of silicon dioxide is formed except sections connected to respective circuit elements. On the oxide film 6A, wiring layers 7A, 7B of aluminum (Al) are evaporated. Moreover, an insulating film 8 of silicon nitride is formed thereon by sputtering. The aluminum wiring layers 7A, 7B constitute a negative pole for the capacitor 10. The capacitance elements are constituted by P<+> type regions 51-53, and polysilicon wiring layers 9A, 9C constitute positive poles for the capacitors 10, 30. The transistor 20 is constituted by N<+> regions 21, 23.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a variable capacitance element.

[Prior Art] Conventionally, variable capacitance elements have been indispensable in radio antenna circuits and high frequency amplification circuits. However, a transistor provided in a semiconductor device has voltage characteristics such that when the gate potential changes, the capacitance of the PN junction surface changes. Efforts are being made to eliminate this voltage characteristic from transistors. However, since the electric circuit itself originally has circuit voltage characteristics, even if the voltage characteristics due to the gate potential can be eliminated, a voltage characteristic of J: will occur in the circuit, and this will affect the characteristics of the entire circuit. This becomes a problem.

[Problems to be Solved by the Invention] Therefore, an object of the present invention is to provide a semiconductor device whose capacitance can be varied depending on the gate potential.

c Means for Solving Problems] The present invention provides a conductive semiconductor substrate, a transistor provided on the substrate, a transistor formed on the substrate, and a
At least two regions of opposite conductivity type using an N junction surface as a capacitor, and a source terminal and a drain terminal provided in the transistor are individually and electrically connected to terminals provided in each of the regions of opposite conductivity type. a wiring layer connected to the
A semiconductor device comprising: an output terminal connected to each of the gate, source, and substrate of the transistor; and the capacitance between the source and the substrate is changed depending on the gate potential of the transistor. It is.

The conductive semiconductor substrate is a P-type or N-type single crystal substrate,
Preferably, the substrate is isolated. The opposite conductivity type region is an N type or P type conductivity type region formed corresponding to the conductivity type semiconductor substrate. Therefore, for example,
When the conductivity type semiconductor substrate is an N type substrate, the opposite conductivity type region is a P type region. The transistor is PNP type or NP
The transistor is an N-type transistor, and the transistor is formed depending on the conductivity type semiconductor. The wiring layer is a wiring layer in which regions of opposite conductivity type are electrically connected in parallel to the source and drain of the transistor. The wiring layer is formed of a conductor such as aluminum or copper by vacuum evaporation, sputtering, or the like.

[Function] The conductive semiconductor substrate has a buried layer on its surface.
It has a transistor and a plurality of regions of opposite conductivity type. The wiring layer individually and electrically connects the source terminal and drain terminal provided in the transistor to the terminal provided in each of the opposite conductivity type regions. An output terminal is connected to the gate, source, and substrate of the transistor.

A predetermined capacitor capacity is provided between each terminal of the substrate and the source due to a PN junction surface between the conductive type semiconductor substrate and the opposite conductive type region. For example, when the potential at the gate terminal is varied and raised, and the potential reaches the "threshold" of the transistor, the transistor is inverted. Therefore, the capacitance of the PN junction surface formed by the opposite conductivity type region connected to the drain side of the transistor is added to the capacitor capacitance. Therefore, the capacitance between the respective terminals increases as the transistors are inverted.

In other words, the semiconductor device of the present invention functions as a variable capacitance element that follows the potential of the gate terminal.

[Example] The present invention will be explained below based on a specific example. FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention.

An N-type silicon substrate was used as the conductive semiconductor substrate 5.

A capacitor 10130 and a transistor 20 as capacitive elements are formed on this substrate 5 using a known integrated circuit manufacturing technique.

An oxide film 6A made of silicon dioxide is formed on the substrate 5, except for the connection parts to the respective circuit elements, and on the oxide film 6A, necessary aluminum (hereinafter referred to as A
1) are formed by vapor deposition. Furthermore, an insulating film 8 made of silicon nitride is formed thereon by sputtering.

To explain each part in detail, the A1 wiring layer 7A17B constitutes the negative electrode of the capacitor 10. The capacitive element is composed of P-shaped regions 51 to 53, and has a polysilicon arrangement 11119.
A and 9G constitute the positive electrode of the capacitor 10.30, respectively, the polysilicon wiring layer 9B is the gate terminal of the transistor 20, and the transistor 20 is connected to the N+ type region 21.2.
3, and regions 21 and 23 are the source and drain, respectively. The capacitor 10 and the transistor 20 are arranged in a well 61, and the capacitor 30 is arranged in a well 63.

Further, the A1 wiring layer 7C has a transistor 20 and a capacitor 3.
Connect with the negative electrode of 0. Then, on the board 5, 5if
t etc. oxide films 71 to 74, PSG nato Nlt conversion 111
6B to 6D, S i s N 4th Class Nohassibation I! ! 8 is installed. A plan view of the above situation is shown in FIG. 2, and an equivalent circuit diagram of the same embodiment is shown in FIG. The numbers attached to the lead lines in FIGS. 2 and 3 correspond to the numbers attached to FIG. 1. The device of this embodiment is provided with terminals 2A and 2B.

The operation of the device of the first embodiment will be described below using the characteristic diagram shown in FIG. In FIG. 4, the horizontal axis shows the gate potential of the transistor 2o, and the vertical axis shows the terminal 2A.

It shows the capacity between 2B. Further, solid lines 108 and 118 indicate the voltage characteristics of the capacitor 10, broken lines 11308°31S indicate the voltage characteristics of the capacitor 30, and solid lines 10S and 15S indicate the entire capacitor of this embodiment, that is, the terminals 2A and 28.
The voltage characteristics between

It is well known that the voltage characteristics of capacitor 10+ are due to the generation and recombination of carriers in the inversion region.
As shown by the graph 10S→118 in FIG. 4, it changes stepwise around the "threshold" voltage VT. Further, for the same reason, the voltage characteristics of the capacitor 30 are also shown as graphs 308→318 shown in the figure. Capacitor 10.30
Since the connection between the transistor 20 and the transistor 20 is shown in the equivalent circuit diagram in FIG. 3, the capacitance Cab between the terminals 2A and 2B is
The transistor 20 is non-inverted when the potential of the terminal 2B is less than the VT with respect to the potential V of the terminal 2B.

Therefore, Cab is only the capacitance of the capacitor 10, but when the value (2) exceeds VT, the transistor 20 is inverted. In other words, the electrode 61 of the capacitor 1o and the capacitor 30
The electrodes 63 of are electrically connected. As a result, the Cab
is the parallel capacitance of capacitor 10 and capacitor 30.

The situation described above is shown by the graph 1oS→158.

By the way, for example, by arbitrarily setting the area of each electrode of the capacitor 10.3o, the capacitance of each capacitor can be set. In other words, the graph 10 mentioned above
Characteristics from 8 to 158 can be selected arbitrarily.

According to the first embodiment, by using a circuit configuration of a capacitor 10.30 whose PN junction surface is a capacitive element and a transistor which functions as a switching element by connecting each capacitor in parallel, the overall capacitor of the embodiment device The capacitance can be set in two positions and can be used as a variable capacitance element that follows the gate voltage.

In the first embodiment, two capacitors and two transistors and one element were formed, but the number of each is not limited to this.

Next, a second embodiment will be described. In the second embodiment, the capacitor 30 in the first embodiment is constructed on the capacitor 10. The situation is shown in FIG. 5, where elements corresponding to those in the first embodiment are given the same numbers. Note that capacitor 1
Each positive electrode of 0.30 mm is made of common polysilicon 9E. Moreover, the negative electrode 7b of the capacitor 3o is A1 wiring,
It is electrically connected to the A1 wiring 7C. Incidentally, although the capacitor 30 does not have voltage characteristics, the operation of the second embodiment device as a whole is similar to that of the first embodiment.

According to the second embodiment, in addition to the effects of the device of the first embodiment, there is an effect that no additional board area is required for the capacitor 30.

Next, we will discuss application examples. An example of application is a device using the device of the present invention as an oscillator.

Its block diagram is shown in FIG. That is, the application example devices are inverters 90 to 92, resistor 93, and capacitor 94 of the present invention. Here, the capacitor 94 may be considered as the entire device of the first embodiment, for example. This circuit outputs a square wave.This oscillator outputs a square wave.
Voltage characteristics occur depending on the capabilities of the transistors included in the inverters 90 to 92.

According to the applied example, by setting the voltage characteristics of the capacitor 94 to compensate for the voltage characteristics of each inverter, the voltage characteristics of the entire oscillator can be eliminated, and a stable oscillator can be realized.

[Effects of the Invention] According to the present invention, by disposing a plurality of opposite conductivity type regions, transistors, wiring layers, and output terminals on a conductivity type semiconductor substrate, the inventive device can change the gate voltage of the transistor. Therefore, it can be used as a variable capacitance element.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. FIGS. 2 1, 3, and 4 are a plan view, an equivalent circuit diagram, and a characteristic diagram showing the same embodiment device, respectively. FIG. 5 is a sectional view showing the structure of a semiconductor device according to the second embodiment. FIG. 6 is a block diagram of an oscillator using a specific embodiment of the present invention. 5...N-type silicon substrate 7A to 7C...AI wiring layer 9A to 9C...Polysilicon wiring layer 10.30...Capacitor 20...Transistor patent applicant Nippondenso Co., Ltd. agent Patent attorney Hiroki Okawa Patent Attorney Shudo Fujitani Patent Attorney Akio Maruyama Figure 1 Figure 2 r Figure 3 1 Gate @ Stand l Figure 5 Figure 6

Claims (3)

[Claims] (1) a conductive type semiconductor substrate; a transistor provided on the substrate; at least two opposite conductivity type regions formed on the substrate and using a PN junction surface with the substrate as a capacitor; and provided on the transistor. a wiring layer that individually and electrically connects the source terminal and drain terminal provided in each of the opposite conductivity type regions to terminals provided in each of the opposite conductivity type regions; and a wiring layer that is connected to each of the gate, source, and substrate of the transistor. What is claimed is: 1. A semiconductor device comprising: an output terminal; the semiconductor device is characterized in that the capacitance between the source and the substrate is changed according to a gate potential of the transistor; (2) A patent claim in which the conductivity type semiconductor substrate is a P type or N type semiconductor substrate, and the opposite conductivity type region is an N type or P type conductivity type semiconductor region corresponding to the P type or N type. The semiconductor device according to item 1. (3) The semiconductor device according to claim 1, wherein the substrate has the opposite conductivity type regions on each of opposing surfaces.