JPS61269294A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a latch-up state from occurring by operating a substrate bias voltage generating circuit and a plate voltage boosting circuit on the basis of oscillation pulses generated by the same oscillation circuit. CONSTITUTION:The boosting circuit VGG receives the oscillation output of the oscillation circuit OSC to generate a voltage VG boosted above a source voltage Vcc. The output voltage VG of the boosting circuit VGG is supplied to the plate electrode 5 of a capacitor Cs, thereby compensating the level loss of the storage capacity of the capacitor Cs due to the threshold voltage of MOS capacity as the capacitor Cs. The substrate back-bias voltage generating circuit VBG receives the oscillator output signal of the oscillation circuit OSC to generate a negative back-bias voltage -Vbb to be supplied to a semiconductor substrate. Therefore, the back-bias voltage -Vbb is applied to the semiconductor substrate 1 as the substrate gate of an N channel MOSFET, and the parasitic capacity value between its source and drain, and the substrate is decreased, thereby speeding up the operation of the circuit.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory, for example, M
The present invention relates to a technique that is effective for use in dynamic RAM (random access memory) that uses OS capacity as an information storage capacitor.

[Background technology]

A 1-bit memory cell in a dynamic RAM includes an information storage capacitor Cs and an address selection insulated gate field effect transistor (hereinafter referred to as MOSFET).
Qm, and in these, logic "1" and "0" information is stored in the form of whether there is a charge in the capacitor C8 or not. Information is read by turning on the MOSFET Qm, connecting the capacitor Cs to the data line, and sensing how the potential of the data line changes depending on the amount of charge stored in the capacitor Cs. be exposed. The capacitor Cs uses a MOS container that utilizes a space between a plate electrode (also referred to as a gate electrode) and a channel, which has substantially the same configuration as the gate electrode of a MOSFET. For this reason, it is necessary to constantly supply a power supply voltage to the plate electrode or gate electrode to induce a channel on the semiconductor surface under the gate electrode, or to form a semiconductor region under the gate electrode to create a depletion mode.

By the way, in order to realize a large storage capacity of about 1 Mbit, the capacitor Cs is three-dimensional (Mizohori capacitor).
・For example, Nikkei McGraw-Hill, February 27, 1984 r
127-141 of "Nikkei Electronics"). Since such a Mizohori capacitor utilizes the side surface of the groove, it is not easy to control it by ion implantation, making it extremely difficult to construct the depletion mode MOS container. Therefore, the power supply voltage is supplied to the gate electrode (plate) of such a Mizohori capacitor. However, as the voltage difference between the two electrodes is reduced by the threshold voltage for forming the channel, the amount of charge that can be stored is reduced. Therefore, when the memory array is highly integrated and has a large capacity as described above, in other words, the area of the memory cells, especially the area of the capacitor Cs that occupies most of the memory cells, is made small, and the data lines are When connecting memory cells, the ratio between the capacitance C1s of the capacitor and the stray capacitance Co of the data line is Cs/C.

will be a very small value. As a result, the change in the potential of the data line due to the small amount of charge accumulated in the capacitor Cs becomes a very small signal, which deteriorates the Th production capacity.

Therefore, a booster circuit that receives a periodic output signal such as that generated from an oscillation circuit and boosts the voltage to a level higher than the power supply voltage is built in, and the gate electrode of the MOS container constituting the capacitor C3 is supplied with power. It is conceivable to compensate for the level loss due to the threshold voltage by applying a high level voltage that is boosted to a level higher than the voltage.

In this case, the inventors have found that if a substrate bias generation circuit that supplies a negative back bias voltage to the semiconductor substrate is built in together with a booster circuit, the following problems will occur (substrate bias generation circuit For details, see, for example, Japanese Patent Application Laid-Open No. 13566/1983). That is,
Among the outputs of the booster circuit and the substrate bias circuit activated by power-on, the boosted voltage of the booster circuit is output first), and the following circuit operation occurs. For example, before the substrate back bias voltage is made into a good resistor,
When the voltage applied to the gate electrode of the MOS capacitor (plate voltage) is set to a large resistor, the gate of the MOS capacitor is shared and the substrate is coupled due to the parasitic capacitance existing between the plate and the substrate. The potential will be raised. In other words, N channel MO
A semiconductor substrate, such as a base gate of a MOSFET, such as an SFET, is brought to an undesired potential in response to the generation of a plate voltage. As a result, M
The OSFET is put into pseudo-depression mode,
- turned on all at once. As a result, a rush current having a relatively large value occurs when the power is turned on. Furthermore, if the memory includes a CM OS structure, such as when the peripheral circuit is configured with a CM'O5 (complementary MO3) circuit, if the potential of the substrate is made higher than the ground potential of the circuit as described above, The source and substrate of the ~fO3 FET formed in the above structure are biased in the forward direction.

This causes a serious problem in that the well-known parasitic silice element in the CMO3 circuit is turned on, causing latch-up.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that has a simple configuration and prevents generation of rush current when power is turned on.

Another object of the present invention is to provide a semiconductor memory that prevents touch amplifiers when the power is turned on.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical embodiments of the invention disclosed in this application is as follows. In other words, based on the oscillation power of the common oscillation circuit, a voltage higher than the power supply voltage is applied to the substrate bias generation circuit that supplies a back bias voltage to the substrate and the gate electrode of the MOS capacitor that constitutes the information storage capacitor of the memory cell. The plate voltage ordering circuit supplies a boosted voltage to the plate voltage ordering circuit.

[Example I]

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Each circuit element in the same figure is
It is formed by well-known CMOS (complementary MO3) integrated circuit manufacturing techniques on a single semiconductor substrate, such as single crystal silicon.

In the following description, MOS, such as in a memory cell,
The FET (insulated gate field effect transistor) is an N-channel MOSFET. In addition, in the same figure, P
A channel MOS FET has an N-channel MOS FET by adding a straight line between its source and drain.
Displayed separately from that of OS F B 'I'.
There is ζ.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET is formed on a polygonal plate formed on a source region, a drain region, and a thin gate insulating film on the semiconductor substrate surface between the source region and the drain region. It is formed in an N-type well region. Thereby, the semiconductor substrate constitutes a common substrate gate for the plurality of N-channel MOSFE'r formed thereon. The N-type well region has a P-channel MOS FI! formed thereon. ,'l” (7)
M body case) is constructed. The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

A more specific structure of the integrated circuit is shown in FIGS. 5 and 6. This can be roughly explained as follows. In Figure 6, the glabella insulating film is omitted to make the drawing easier to read.
2. Some conductor layers are omitted.

Among the surface portions of the single-crystal P-type silicon semiconductor substrate 1, other than the surface portions that are used as active regions, in other words, semiconductor wiring regions, capacitor formation regions, and sources, drains, and drains of N-channel and P-channel MOS FETs. A relatively thick field insulating film 2 formed by a known selective oxidation method is formed in areas other than the surface portion which is used as a channel forming region (gate forming region).

In the capacitor C3 forming region, although not particularly limited, a trench 3 for forming a trench-horizon capacitor is dug. On top of this groove is a thin insulating film (
#i, a first polysilicon layer 5 is formed with a chemical film 4 interposed therebetween. The first polysilicon layer 5 extends onto the field insulating film 2 . The single-layer polysilicon layer 5 is used as a common capacitor electrode for multiple memory cells in the same memory array, so it is used as a MO3FET for cell selection.
It is formed into a flat plate shape over the entire memory array except for the Qm forming region. An oxide film 6 is formed on the surface of the first layer polysilicon eyebrow 5 by thermal oxidation of itself. On the surface of the semiconductor substrate in the capacitor formation region, a plate voltage generation circuit (hereinafter simply referred to as a booster circuit VGG), which will be described later, is formed on the first polysilicon layer N (plate) 5. A capacitor Cs consisting of an insulating film 4 and a channel region is formed.Field oxidation 15
The first polysilicon layer 5 on the flZ is regarded as a -. seed wiring.

A second polysilicon layer 8 for use as a gate electrode is formed on the Chang Meisan formation region with a thin gate oxide film 7 interposed therebetween. This second polysilicon layer 8 extends over the field insulating film 2 and the first polysilicon layer 5. Although not particularly limited, word lines and dummy word lines in the memory array, which will be described later, are formed from the second polysilicon layer 8.

The surface of the active region that is not covered by the field insulation 111!2, IN-th and 2-th WI polysilicon N5 and 8 is covered with N0 type source, drain regions and semiconductors by a known impurity doping technique using them as an impurity doping mask. A wiring area is formed. As a result, gate electrode 8, gate insulation 1! l! A memory cell selection MOSFET Qm consisting of a source region 7 and a source and drain region 9 is formed.

A relatively thick glabellar insulation Il is formed on the surface of the semiconductor substrate including the tops of the first and second polysilicon layers 5 and 8! ! 10 is formed, and a conductor MII made of aluminum is formed on this glabellar insulation M*10. Conductor layer 11 is electrically coupled to polysilicon layer 8 and semiconductor region 9 via a contact hole provided in an insulating film below. A data line in a memory array, which will be described later, is composed of a conductor layer 11 extending on this glabella insulating film 10, although it is not particularly limited.

The surface of the semiconductor substrate including the top of the glabella insulating film 10 and the top of the conductor layer 11 is covered with a silicon nitride film and a phosphorus silicate glass 1.
Final pansivation film 12 consisting of odor
covered by.

The booster circuit VGG shown in FIG.
Generate G. Output voltage VG of booster circuit VGG is supplied to plate electrode 5 of capacitor C9. This compensates for the level loss of the storage capacitance of the capacitor Cs due to the threshold voltage of the MOS capacitor that is the capacitor C3.

The substrate back bias voltage generation circuit VBG shown in FIG. 1 receives the oscillation output signal of the oscillation circuit OSC and generates a negative back bias voltage -vbb to be supplied to the semiconductor substrate as described later. As a result, a back bias voltage -Vbb is applied to the semiconductor substrate 1, which is the substrate gate of the N-channel MO3FET, and the parasitic capacitance value between the source, drain, and substrate is reduced, so that the circuit can operate at high speed. It will be planned.

In this embodiment, the booster circuit VGG and the substrate back bias generation circuit VBG are operated by receiving the oscillation output signal fR from the same oscillation circuit OSC. In other words, both type pressure generation circuit VG
G and VBG are the oscillation circuit OS started when the power is turned on.
They are operated simultaneously by the oscillation output signal of C. This at least prevents the output of the voltage generating circuit VGG from being increased before the output of the voltage generating circuit BG.

That is, voltage VC is prevented from rising before voltage -vbb.

Although not particularly limited, the memory array M-ARY is of a two-point type (folded bit line type), and a pair of rows thereof are specifically shown in FIG. A pair of parallel complementary data lines.

At D, the input/output nodes of each of the plurality of memory cells constituted by the address selection MOS FET Qm and the information storage capacitor Cs are distributed and coupled with a predetermined regularity as shown in the figure. has been done.

The precharge circuit PCI is represented by the M O
SF E ']' Q 5 (7) Complementary data line.

0; (Constructed by inch MO3FET.

The sense amplifier SA consists of a P-channel MO3F uT (617, Q 9, shown as a representative) and an N-channel M
It is constituted by a CMOS launch circuit consisting of OS tr w -i' Q 6 and Q 8, and its pair of input/output nodes are coupled to the complementary data line D. In addition, the above launch circuit may include, but is not particularly limited to, a parallel form (DP channel MO3FE'l'Q12.Ql3
A power supply voltage Vcc is supplied through the parallel N-channel MOSJI'E'l'Q10. Through Ql 1°
The ground voltage Vss of the ζ circuit is supplied. These power switches MO3FETQ10. Ql 1 and MOSFE
TQI 2. Ql 3 is commonly used for latch circuits similarly provided for other rows within the same memory mantle. In other words, the sources of the P-channel MOS FET and N-channel MO3FET in the launch circuit in the same memory mat are commonly connected.

In the operation cycle, a complementary timing pulse φpal + φpal that activates the sense amplifier SA is applied to the gates of the MO3FETQI O, Ql 2, and
O3FETQI 1. A complementary timing pulse φpa2 + φpa2 delayed from the timing pulse φpal*$pal is applied to the gate of Ql3. By doing this, the sense amplifier SA
The operation can be divided into two stages. timing pulse φρa
When l, φpal is generated, that is, in the first stage, MO3FE with relatively small conductance
Due to the current limiting effect of TQI O and QI2, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing undesired level fluctuations. After the difference in complementary data line potential is increased by the amplification operation in the sense amplifier SA, the timing pulse φpa2. When φpa2 is generated, that is, when it enters the second stage, the MOSF with relatively large conductance
E'T''QI 1.Ql 3 is turned on.

The amplification operation of the sense amplifier SA is performed by MOSFETQll,
This is made faster by turning on QI3. By performing the amplification operation of the sense amplifier SA in two stages in this way, it is possible to read data at high speed while preventing undesired changes in the complementary data line.

Although not particularly limited, the row decoder R-OCR is configured by a combination of two divided row decoders R-DCR1 and R-DCR2.

In the figure, one circuit (four word lines) of the second row decoder R-OCR2 is shown as a representative. According to the illustrated configuration, N-channel MO3FETs Q32-Q36 receiving address signals T2-T6 and P-channel MO3FETs Q32-Q36 receive address signals T2-T6;
CMOS composed of OSFETQ37 to Q41
A word line selection signal for selecting the four lines is formed by a NAND circuit. The output of this NAND circuit is inverted by a CMOS inverter IVI, and passed through N-channel type cut MO3FETs Q28 to Q31 to an N-channel type transmission gate M as a switch circuit.
It is transmitted to the gates of OSFETs Q24 to Q27.

The first row decoder R-DCR1 receives 2-bit complementary address signals aO, aO, although its specific circuit is not shown.
Four types of word line selection timing signals φx00 to φxll are formed from the word line selection timing signal φX by the decode signals formed by the word line selection timing signals φX, al, and T″l.

These word line selection timing signals φx00 to φxl
l is the transmission gate MOSF'E'l'Q24~Q2
7 to each word line.

Although not particularly limited, when the address signals aO and al are at low level, the timing signal φχoo
It is set to high level in synchronization with the evening/C timing signal φX.

Similarly, the timing signal φ is 01, φxlO and φxL.
I are address signals 0 and al, and aO, respectively.
and al, and aQ and 11 are set to low level, and are set to high level in synchronization with timing signal φX.

As a result, the address signals a1 and T1 are transmitted to the word line group (WO, Wl, hereinafter referred to as the first word line group) corresponding to the memory cell coupled to the data line among the plurality of word lines. It is regarded as a kind of word line group selection signal for identifying the word line group (W2, W3, hereinafter referred to as a second word line group) corresponding to the memory cell coupled to data JJ (D).

o t") 7' = r-da R-DCRI and R-DCR
By dividing the row decoder into two as shown in FIG. 2(7), the pitch (interval) of the row decoder R-DCR2 can be matched with the pitch of the word lines. As a result, no wasted space is created on the semiconductor substrate. An N-channel MOSFET Q20- is connected between each word line and the ground potential.
Q23 is provided, and by applying the output of the NAND circuit to its gate, the word line is fixed at the ground potential when not selected.

Although not particularly limited, the word line may have a far end side (
N-channel type MO3FETs QI-Q4 for reset are provided at the end opposite to the decoder side), and these MO3FETs QI-Q receive the reset pulse φpw.
4 is turned on, the word line selected by C1 is reset to the ground level from both ends thereof at the next timing.

Note that the remaining 2 bits of the row address signal 7 (a7
and a7), a8 (a8 and d8) are used as switching signals (selection signals) for "?'7)" (a memory array similar to the above divided into a plurality of pieces).

Row address buffer X-ADB is connected to external terminal AO-A.
In response to the address signal supplied from 8, the internal address signal aO is in phase with the address signal supplied from the external terminal.
Forming address signals 70 to 8 (hereinafter collectively referred to as ao-a8) having a phase opposite to that of ~a8,
The signal is supplied to the row decoder R-DCR via a multiplexer MPX, which will be described later.

Column switch C-5W is shown as a representative N
Channel type MOSFETQ42. Like Q43,
The complementary data line D is selectively coupled to the common complementary data line CD, CD. These MO3FETQ42. Q4
A selection signal from the column decoder C-DCR is supplied to the gate of No. 3.

Column decoder C-DCR has a column selection timing controlled by data line selection timing signal φy, and receives address signal T which is in opposite phase to internal address signals a9 to a14 supplied from column address buffer Y-AD-B.
By decoding 9 to 14, a selection signal to be supplied to column switch C-5W is formed.

Column address buffer Y-A D B is connected to external terminal A
In response to address signals supplied from terminals 9 to A14, internal address signals a9 to a14 which are in phase with the address signals supplied from external terminals and address signals T9 to T14 (which are in reverse phase) are output.
Combine these below! It is expressed as 9-14. )
is formed and supplied to the column decoder C-0CR.

Between the common complementary data lines CD and 53, an N-channel precharge MOSFET Q44 constituting a precharge circuit similar to the above is provided. A pair of human output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA are coupled to the common complementary data lines CD, CD.

During a read operation, the data output buffer DOB is activated by the timing signal φrw, amplifies the output signal of the main amplifier MA, and outputs it to the external terminal 11.
Send from 0. Note that during a write operation, the data output buffer DOB is activated by the timing signal $rw.
The output of is placed in a high impedance state. During a write operation, the data input cover sofa DIB is put into the operating state by the timing f electric signal φr-, and the external terminal ■
By transmitting a complementary write signal according to the write signal supplied from 10 to the common complementary data lines CD, CD, writing to the selected memory cell is performed. In addition,
During a read operation, the output of the data buffer sofa DAB is brought into a high impedance state by the timing signal φr-. “As mentioned above, in the write operation to the dynamic memory cell consisting of the address selection MO3FETQm and the information storage capacitor C3, in order to perform a full write to the information storage capacitor Cs,
In other words, in order to prevent level loss of the high level input to the information storage capacitor Cs due to the threshold voltage of the address selection MO3FETQm, etc., the word line boot activated by the word line selection timing signal φX is activated. A strap circuit (not shown) is provided. This word line bootstrap circuit uses the word line selection timing signal φX and its delayed signal to set the high level of the word line selection timing signal φX to 11 source voltage V.
The level is as high as cc or higher.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, what is indicated by the circuit symbol A'I''D is an address signal aO to a8 (or aQ to τ8).
) and address signals a9 to a14 (or 79 to 14)
This is an address signal change detection circuit that detects a change in the rising or falling edge of the address signal. The address signal change detection circuit ATD includes a portion corresponding to address signals aO-a8 and a portion corresponding to address signals a9 to a14.

Portions corresponding to the address signals aO to a8 include, but are not particularly limited to, exclusive OR circuits that receive the address signals aO to a8 and their delayed signals, respectively, and an OR circuit that receives the output signals of these exclusive OR circuits. Consists of circuits. The portions receiving address signals a9-a14 are constituted by circuits similar to those corresponding to the address signals aO-a8. That is, an exclusive OR circuit that receives an address signal and a delayed signal of the address signal is provided for each address signal. When any one of address signals aO to a8 changes, this address signal change detection circuit ATD forms a row-related address signal change detection pulse φr synchronized with the change timing. Similarly, the address signal change detection circuit ATD detects the address signal a9.
When any one of the signals .about.a14 changes, a column-system address signal change detection pulse .phi.C is generated.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. That is, this timing generation circuit TO
is the write enable signal Wτ supplied from the external terminal
, receives the chip selection signal S and forms the series of various timing pulses described above.

What is shown in the circuit diagram E+REFC is an automatic refresh circuit, which includes a refresh address counter, a timer, etc. (not shown). This automatic refresh path REFC is activated by setting the signal REF to a low level from an external terminal. That is, when the chip selection signal C3 is at a high level, and the refresh taJ+REF goes low or goes to a bell, the automatic refresh circuit REFC is put into an operating state accordingly.

That is, from the circuit REFC, the multiplexer MPX
In contrast, a control signal φref is output that causes the internal address signal from the built-in refresh address counter to be transmitted to the row decoder R-DCH. As a result, a refresh operation (auto-refresh) is performed by selecting one word line corresponding to the internal address signal.

Further, when the refresh signal REF is kept at a low level, a timer is activated, and the refresh address counter is incremented at fixed time intervals, during which a continuous refresher operation (self-refresh) is performed.

FIG. 2 shows a circuit diagram of an embodiment of the substrate bias voltage generating circuit BG and the booster circuit (plate voltage generating circuit) VGG. In the same figure, inverter circuit I
V2 to IVIO is not particularly limited, but CMO3
It is constructed of a circuit and is operated by a positive power supply voltage such as +5V applied between a power supply terminal Vcc and a reference potential terminal or ground terminal VSS, which constitute an external terminal of the integrated circuit.

The substrate bias voltage generation circuit VBG generates a negative back bias voltage -vbb to be supplied to the semiconductor substrate. This causes a back bias voltage to be applied to the substrate gate of the N-channel MO3FET. The board of this embodiment? The voltage generation circuit VBG is an oscillation circuit O8C constituted by three (an odd number is sufficient) inverter circuits IV2 to IV4 connected in series in a ring shape.
A CM that receives the oscillation output signal, shapes its waveform, and amplifies it.
OS inverter circuit IV5. It consists of lV6 and the following rectifier circuit or level conversion circuit.

In other words, the rectifier circuit is the above CMOS impark circuit I.
A capacitor C1 receives a periodic pulse signal obtained from the output of V6 at one electrode e1, and '4ti62 on the 411 side of this capacitor C1 and the ground potential point Vs of the circuit.
MOS F in the form of a diode provided between
E T C=150 and M in the form of a diode provided between the other electrode e2 of this capacitor C1 and the substrate 1.
A MOSFET is connected between this substrate 1 and the ground potential point Vss of the circuit.
There is a parasitic capacitor C2 consisting of junction capacitance, wiring capacitance, etc. between the source and the substrate. The diode type MOS transistor 'E'l'Q50 is connected to the inverter circuit IV6.
The pulse output from the high level (power supply voltage V cc
), it is turned on by the positive voltage supplied via the capacitor Cs. This makes the capacitor CI
is precharged by high level.

Next, when the pulse is set to a low level (circuit ground potential), that is, when one electrode el of the capacitor CI is set to a low level, the other electrode e2 of the capacitor C1 becomes -(Vcc -V th ) becomes a negative potential. here,
vth is the threshold voltage of MOSFETQ50. This negative potential turns on the diode-type MOSFET Q51.

Accordingly, the negative potential applied to the electrode e2 is MOS)
It is transmitted to the parasitic capacitance C2 via 'ET' Q51. That is, a substrate back bias voltage of -vbb is applied to the substrate l.

On the other hand, a booster circuit VGG that forms a voltage VG applied to a plate (first layer polysilicon) 5 configured by sharing the gate electrode of the information storage capacitor Cs in the memory cell is configured to output the oscillation output of the oscillation circuit OSC. A two-stage C (not particularly limited) that constitutes a delay circuit that receives a signal.
MOS inverter circuit IV7. IV8 and a CMOS inverter circuit IV9 for waveform shaping and amplification. It consists of IVIO and a booster circuit. The booster circuit is an inverter circuit I output from the CMOS inverter circuit IVIO.
A capacitor C3 whose one electrode e3 receives an oscillation pulse delayed with respect to the output pulse of V6, a diode-shaped MO3FET Q52 provided between the other electrode e4 of this capacitor C3 and the power supply voltage Vcc, and this It is composed of a diode-type MO3FET Q53 provided between the other electrode e4 of the capacitor C3 and the plate 5. A parasitic capacitance IC4 exists between the plate 5 and the ground potential point of the circuit, and a parasitic capacitance C5 exists between the plate 5 and the substrate 1.

The operation of the booster circuit VGG is as follows. That is,
The above diode type MOS FET Q52
When the output pulse output from the C converter circuit IVIO is brought to the low level of 0, it is accordingly turned on. As a result, the capacitor C3 becomes 7VCC-Vth (however, vth is MOS l'i'
E'r is precharged to a level of 52 threshold voltage. Next, when the oscillation pulse rises to the high level of the source voltage level 1i, the other electrode e4 of the capacitor C3 becomes (2Vcc -V
th) is set to a high potential.

By making this boost IE1 positive, it is in the form of a diode, and the threshold voltage vth is set to H.
is turned on, and the boosted voltage appearing at electrode e4 is MO
It is transmitted to the parasitic capacitance C4 via S1-'E"l'Q53. A boosted voltage VC is applied to the plate 5. This voltage VG is finally 2Vcc-2Vlh.
(2Vth is the threshold voltage of MO3FE'l'Q52 and Q53).

In this embodiment, the oscillation output signal of the same oscillation circuit OSC is used to operate the dual-type voltage generation circuits VGG and VBG, and the negative oscillation output signal is used as the input oscillation signal of the booster circuit VGG that forms the positive boosted voltage VG. Since it supplies an oscillation signal delayed with respect to the input oscillation signal of the substrate bias voltage generation circuit VBG that forms the bias voltage -vbb, the output voltage -v of the substrate bias voltage generation circuit VBG is first generated.
Vbb can be lowered. This prevents the substrate potential from being raised to a level higher than the ground potential of the circuit due to the start of operation of the booster circuit VGG.

In this embodiment, a two-stage CMOS inverter circuit IV7. is used as the delay circuit in the booster circuit VGG. IV8
is used, but the present invention is not limited to this, and various other embodiments may be adopted. The number of inverter circuits does not need to be two, as long as the signal can be delayed. The inverter circuit does not need to be a CMOS circuit, and the delay circuit does not need to be an inverter circuit.

Note that during the operation of the automatic refresh circuit REFC (during refresh), a large amount of substrate current flows through the substrate l, so the substrate back bias voltage -Vbb temporarily increases (
(decreasing in absolute value), but the above-mentioned rush current and launch-up do not occur.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the booster circuit VGG.

In this embodiment, in order to more reliably prevent the substrate potential from becoming higher than the ground potential of the circuit due to the start of operation of the booster circuit VGG, the booster circuit VGG has an output voltage -vbb of the substrate bias voltage generation circuit VBG. It is configured to start operating when the voltage is lowered to a predetermined level. Although not particularly limited, according to this embodiment, the booster circuit VG
In order to control G, a substrate bias voltage -vbb is detected.

The level detection circuit LDC for detecting that the substrate bias voltage -Vbb is set to a predetermined negative potential has the following configuration. That is, the level detection circuit LDC includes a level detection section LD, an inverter circuit consisting of MO3FETs Q61 and Q62, and an inverter circuit IVI1. IV12 and a P-channel MO3FETQ63 for forming a feedback circuit.

The level detection section LD consists of the following. P channel MO3
FETQ56 is constantly turned on by constantly supplying the circuit ground potential to its gate, and acts as a load resistor.

A P-channel MOSFET Q57 for output level clamping is connected in series to this MOSFET Q56.

This MOSFET Q57 is constantly turned on as its gate is constantly supplied with the circuit ground potential.

Drain and substrate of MO3FETQ57 above (-Vbb)
are connected to N-channel MO3FETQ5 in diode form and each having a threshold voltage vth.
8 to Q60 are provided in series. MOSFETQ5
8 to Q60 substantially constitute a level shift circuit.

The operation of the detection circuit having this configuration is as follows. In other words, if the absolute value of the substrate bias voltage -vbb is now at a level smaller than the combined threshold voltage 3VLh of the diode-type MO3FETs Q58 to Q60, these MOSFETs Q58 to Q60 are turned off. . By this, the above MO3FETQ56 and Q57
The potential at the connection point (output voltage of the level detection section LD) is set to a high level such as the power supply voltage Vcc.

On the other hand, if the absolute value of the substrate bias voltage -vbb is set to a level greater than the combined threshold voltage 3vth of the diode-type MO3FETs Q58 to Q60, these MO3FETs Q58 to Q60 are turned on. Accordingly, the above MOSFETQ56 and Q
The potential at the connection point 57 (output voltage of the level detection section LD) is set to a low level that is higher than the ground potential of the circuit by the threshold voltage vth of MO3FETQ57. In addition, from the above power supply voltage Vcc, MO3FETQ56 to Q
The current flowing to the substrate via 60 is equal to the substrate bias voltage -
Decrease vbb in absolute value. In order to prevent such voltage drop, and the above MOSFE'rQ58 to Q6
The conductance of the load MOSFET Q56 is set to an extremely small value in order to form the above-mentioned low level by the composite conductance of MOSFET Q57 and MO3FETQ57. That is, MO3FETQ56 is set to have an extremely small conductance so that only a small amount of current flows.

The high level and low level of the detection output of the level detection section LD as described above are determined by the following level determination circuit. Although the level determination circuit is not particularly limited, it is constituted by a hysteresis circuit in order to prevent the oscillatory determination CMO3 having an extremely narrow pulse width from being output therefrom. That is, the level determination circuit has P channel MO3FE'l'Q61 and N channel MO3 as shown in the figure.
CMOS inverter circuit configured with FETQ62, CMOS inverter circuit IVI1. The operation of the device determination circuit composed of IV12 and feedback MOSFET Q63 is as follows. Now, if the output of the level detection unit LD is changed from high level to low level, MO
Inverter circuit I by positive feedback by 3FETQ63
The output of VII is quickly changed to low level. In response, the detection output of inverter circuit IV12 is set to high level. The detection output formed by this inverter circuit IV12 is used as the output of the level detection circuit LDC.
It is supplied to one input of the MOS Nant gate circuit Gl.

The other input of the Nant gate circuit Gl is supplied with the oscillation output signal of the oscillation circuit O8C shown in FIG. 2 above. The Nant gate circuit Gl functions as a control gate (switch) for determining whether or not to transmit the oscillation output signal of the oscillation circuit OSC to the booster circuit VGG, depending on the detection output of the level detection circuit LDC. The output signal of this Nant gate circuit Gl is applied to the same CMOS inverter circuit IV10. Capacitors C3, C4 and MOSFET Q52 in diode form
, C53 is supplied to the booster circuit VGG.

In addition, in this embodiment, the boosted voltage VG is connected to the capacitor Cs.
In order to prevent the breakdown voltage from exceeding the dielectric breakdown voltage of the dielectric film 4, a level clamping MO in the form of a diode is connected between the output voltage VG and the power supply voltage Vcc.
3FETQ54. C55 (each threshold voltage is V
th) are provided in series form. As a result, the output voltage VG is clamped at Vcc+VLb.

In this embodiment, the detection output of the level detection unit LD is kept at a high level until the substrate bias generation circuit VGG starts operating when the power is turned on and the voltage -vbb is lowered to a predetermined potential or less. Therefore, a low level (logic "O") is supplied to one input of the Nant gate circuit Gl. As a result, the gate of the Nant gate circuit G1 is closed and the output signal is at a high level (logic @l"
) is fixed. As a result, the booster circuit VGG is prevented from performing its boosting operation.

When the potential of the substrate bias voltage -vbb is made sufficiently low by the start of operation of the substrate bias circuit VBG, the detection output of the level detection section LD changes from high level to low level, so the output of the inverter circuit 1v11 is quickly brought to the low level. Ru. In response, the voltage detection circuit LDC outputs its output f word (CMOS inverter circuit 1v
12 output signal) from low level to high level at high speed. This high level signal opens the gate of the Nant gate circuit ci, and transmits the oscillation output signal of the oscillation circuit O3C to the CMOS inverter circuit IVIO. As a result, an oscillation pulse is supplied to the booster circuit, so that the boosting operation described above is started and the plate voltage VG is raised to a high level higher than the power supply voltage.

In this embodiment, an oscillation pulse is supplied to the booster circuit VGG after the output of the substrate bias generation circuit VBG is set to a predetermined low level. As a result, it is possible to reliably prevent the substrate potential from being raised to a level higher than the ground potential of the circuit due to the above-mentioned computation caused by the start of operation of the booster circuit VGG.

The level detection circuit LDC needs only to have at least a level detection section.The level detection section LD is not limited to the above circuit and can take various embodiments.

[Embodiment 3] FIG. 4 shows a circuit diagram of still another embodiment of the above-mentioned booster circuit VGG.

In this embodiment, the voltage detection circuit LD shown in FIG.
In addition to the output signal of C (the output signal of CMOS inverter circuit 1v12), the following control signal is supplied.

That is, in this embodiment, when the boosted voltage (plate voltage) VG formed by the booster circuit reaches a desired potential or higher, the operation of the booster circuit is stopped, thereby forming a higher voltage than necessary. This prevents the generation of meaningless current consumption. That is, the boosted voltage VG is used as the operating voltage of the CMOS inverter circuit consisting of the P-channel MO3FETQ64 and the N-channel MO3F'ETQ65.
4 sources. A power supply voltage Vcc is constantly supplied to the input terminal of this CMOS inverter circuit. In addition, in this CMOS inverter circuit, the conductance of N-channel MOSFET Q65 is
It is set sufficiently small compared to the conductance of OSFETQ64.

In other words, the N-channel MOSFET Q65 is configured to allow only a small amount of current to flow, like the MO3FET Q56 shown in FIG. 3 above. Now, when the boosted voltage VC is equal to or higher than the power supply voltage Vcc and is a relatively low voltage close to it, only the above-mentioned small voltage is supplied between the gate and source of the P-channel MO3FET Q64. This turns MOSFETQ64 off.

As a result, the above CMOS inverter circuit (Q64.Q6
The output signal of 5) is set to low level. This output signal is inverted to a high level signal by the CMOS inverter circuit 1v13 and supplied to the Nant gate circuit Gl. As a result, if the output of the inverter circuit IV12, which is the output of the detection circuit LDC for the substrate bias voltage -vbb, is at a high level, the Nant gate circuit G1 opens its gate and supplies the oscillation pulse to the booster circuit VGG.

In response to this, the booster circuit VGG continues to perform its boosting operation.

By this boosting operation, the boosted voltage VG is increased, and the gate voltage (Vcc
), the MOS FETQ64 is turned on accordingly. As a result, the output signal of the CMOS inverter circuit consisting of MO3FETs Q64 and Q65 is changed from low level to high level. In response to this, the inverter circuit IV13 changes its output signal from high level to low level and closes the Nant gate circuit G1.5. As a result, the supply of oscillation pulses to the booster circuit VGG is stopped, and accordingly the boosting operation is also stopped. Therefore, the boosted voltage VG is not increased any higher (and meaningless current consumption in the boosting operation is also stopped).

When the boosted voltage VG is gradually lowered by leakage current, the MO3FETQ64 is turned off again. As a result, the gate of the Nant gate circuit G1 is opened again in the same manner as described above, so that the supply of the oscillation pulse is resumed, and the dropped voltage is recovered.

Thereafter, by similar operations, the booster circuit VGG repeats intermittent boosting operations.

The operation of the RAM shown in FIG. 1 above is summarized as follows.

In the chip selection state where the chip selection signal CS supplied from the external terminal is set to low level, if any address signal A L f) supplied via the external terminal changes, the address signal change detection circuit ATD detects an address signal change. Detection detection pulse φr.

φC is formed.

The timing ordering circuit TG outputs the memory array M-ARY in synchronization with the address signal change detection pulses φr and φC.
Temporarily reset the selection circuit.

That is, the timing pulse φpa1. φpa2 (
sense amplifier SA by fls Pal, φpa2)
is inactive and the complementary data line D is set to floating high and low levels according to the previous read or write information. Further, the word line selection timing signal φX and the data line selection signal φy are set to low level to put them in a non-selected state. After this, the precharge pulse φpcw is once set to high level and the complementary data lines are short-circuited to perform the half precharge operation as described above. After this precharge operation is completed, the word line selection timing signal φX is The word line is selected according to the address signal taken in by setting it to high level.

Next, the timing pulse φpaLφρa2 (φp8
1°φpa2), the sense amplifier SA is activated to amplify the stored information of the memory cell read out as complementary data #MD, D, and is transmitted to the complementary data lines p, D.

The charge as stored information in the memory cell, which is once destroyed by the word line selection operation, is recovered by receiving the level of the amplified complementary data line D as it is.

Next, column decoder C-DCR forms a selection signal according to data line selection timing signal φy and supplies it to column switch C-5W. As a result, the pair of data lines D and the common complementary data lines CD and CD are coupled, so that the common complementary data lines CD and CD receive data according to the level of the coupled data line D. appear. In the case of a read operation, the read signal read onto the common complementary data lines CD, CD is amplified by the main amplifier MA. Then, the data output buffer DOB is activated by the high level of the timing pulse φrw, and the read output 1) out is sent from the external terminal I10. In the case of a write operation, the data cover sofa D is activated by the high level of the timing pulse φrw.
High level and low level write signals supplied via IB are applied to common complementary data lines CD, CD and column switch MOSFET Q42. Q43 and complementary data line,
The data is written to the memory cell via D.

〔effect〕

(11) By operating the substrate bias voltage generating circuit and the plate voltage boosting circuit based on the oscillation pulses formed by the same oscillation circuit, at least the plate voltage boosting circuit starts operating first. This prevents the substrate potential from becoming higher than the circuit ground potential due to coupling between the It is possible to prevent the generation of a rush current that is changed to a current value, and in the 0M03 circuit, it is possible to obtain the effect that latch-up can be prevented from occurring.

(2) By inserting a delay circuit in the booster circuit for oscillation pulses generated by the same oscillation circuit, the operation of the booster circuit can be delayed. This allows the substrate bias generation circuit to start operating first and bring the substrate potential to the negative side first, which has the effect of more reliably suppressing the rise in substrate potential due to the coupling. can get.

(3) By detecting that the output voltage of the substrate bias generation circuit has reached the desired potential and supplying an oscillation pulse to the booster circuit side, the substrate potential due to the above-mentioned coupling becomes a positive potential. This has the effect of being able to more reliably prevent this.

(4) By providing one common oscillation circuit for two types of voltage generation circuits, it is possible to achieve the effect of simplifying the circuit.

(5) By supplying a boosted voltage higher than the power supply voltage to the plate (gate) of the information storage capacitor, the MOS'
Since it forms the channels that make up the J mouse,
As a result of increasing the level of stored storage information, it is possible to improve the operating margin.

(6) Since a boosted voltage higher than the power supply voltage is supplied to the plate of the information storage capacitor to form a channel constituting the MOS capacitor, the actual amount of information charge can be reduced even in the Mizohori capacitor. You can get the effect of making it bigger.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, the reference voltage required for the read operation of the memory cell may be formed using a dummy cell.Also, the specific circuit of other peripheral circuits constituting the dynamic RAM described above may be formed using a dummy cell. The configuration can take various embodiments.

For example, the address signal may be multiplexed and supplied from a common address terminal in synchronization with the address strobe signals RAS and CAS.An automatic refresh circuit is not particularly required.

The delay circuit consisting of the inverter circuits IV7 to v9 in FIG. It can be constructed from a gate circuit such as a Nant gate circuit whose operation is controlled by the output of the circuit. In this case, the output of the time constant circuit is supplied to the gate circuit via a waveform shaping circuit such as an inverter circuit. Therefore, it is possible to adopt a circuit configuration consisting of a counter circuit that receives the output of the oscillation circuit, and a state storage circuit such as a flip-flop circuit that detects the count-up of the counter circuit. If the delay circuit is modified in this way, the delay time for the circuit VGG of FIG. 2 can be made sufficiently large.

In FIG. 3, the pulse signal supplied to the substrate bias generation circuit VBG may be controlled by a level detection circuit similar to the level detection circuit LDC in FIG. 3 and a new gate circuit similar to the gate circuit G1. In other words, feedback may be applied to the substrate bias generation circuit VBG to stabilize the level of the bias voltage -vbb. In this case, the booster circuit VGG is operated regardless of the intermittent operation of the substrate bias generation circuit VBG. In order to do this, the detection level of the detection circuit LDC of FIG. 3 for the booster circuit VGG is made somewhat smaller in absolute value than that of the detection circuit for the substrate bias generation circuit.

Control of the substrate bias generation circuit and the booster circuit is also possible by using one common level detection section. For example, the level detection circuit LDC and gate circuit G1 in FIG.
A state memory circuit consisting of a flip-flop circuit is provided between the oscillation circuit OSC and the substrate bias generation circuit VBG, which is automatically reset when the power is turned on and set to the set state by the output of the detection circuit LDC.
A gate circuit gate-controlled by the output of the detection circuit LDC is provided between the detection circuit LDC and the detection circuit LDC. A memory circuit whose state is changed to one state when the power is turned on can be composed of, for example, a CR time constant circuit that receives a power supply voltage and a flip-flop circuit that receives its output. According to this configuration, the state storage circuit has a bias voltage of −v after power is turned on.
When bb is brought to a predetermined level, it is set to a set state. The state storage circuit is maintained in the set state regardless of subsequent changes in the output level of the level detection circuit LDC. The booster circuit VGG is maintained in the operating state by setting the state storage circuit to the cent state after power is turned on. Bias voltage -vbb is stabilized by a feedbank via level detection circuit LDC. According to another example, the level determination circuit of FIG.
to Q63 and inverter circuit IVI1. An additional level determination circuit having substantially the same circuit configuration as the circuit consisting of IV12 is provided, and a gate circuit gate-controlled by the output of the additional level determination circuit is provided between the oscillation circuit osc and the substrate bias generation circuit VBG. It will be done.

The additional level determination circuit is adapted to receive the output of the level detection section LD together with the level determination circuit of FIG. In this case, the determination level of the additional level determination circuit is set so that the level determination circuit of FIG. On the other hand, the absolute value is increased somewhat. If the level determination circuit is combined, the current flow through it to the semiconductor substrate is reduced somewhat.

Substrate in Substrate Bias is Not Restrictive For example, if a back bias voltage is applied to a well region formed in a semiconductor substrate, that well region is considered to be the substrate in substrate bias.

It is not essential whether the semiconductor memory itself is formed on one independent semiconductor substrate or not.

A semiconductor memory formed together with a circuit such as a microprocessing unit on one semiconductor substrate also constitutes a semiconductor memory within the meaning of the present invention.

The oscillation circuit is not limited, and may be, for example, a signal generation circuit such as a clock pulse generation circuit that receives an output from a source oscillation circuit.

[Application field]

This invention is a dynamic RAM that uses an enhancement mode MO3 capacitor as an information storage capacitor.
It can be widely used in semiconductor memories such as.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the substrate bias generation circuit and the booster circuit, and FIG. 3 is a circuit diagram showing another embodiment of the booster circuit. FIG. 4 is a circuit diagram showing yet another embodiment of the booster circuit, FIG. 5 is a plan view showing the structure of the embodiment shown in FIG. 1, and FIG. FIG. 7 is a sectional view taken along the line XX in FIG. 6; M-ARY...Memory array, Pct...Precharge circuit, SA...Sense amplifier, C-5W...Column switch, R-DCR...Row address decoder, C-DC
R: Column address decoder, MA: Main amplifier, ATD: Address signal change detection circuit, TG: Timing generation circuit, REF: Automatic refresh circuit, D
OB...data output buffer sofa, DIB...data input buffer, MPX...multiplexer, VBG...substrate bias generation circuit, VGG...boost circuit w52 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A substrate bias generation circuit that receives an oscillation output signal and supplies a back bias voltage to the substrate, and a gate of a MOS capacitor that receives the oscillation output signal and constitutes an information storage capacitor of a memory cell. A semiconductor memory characterized in that an electrode includes a plate voltage generation circuit that supplies a voltage boosted to a voltage higher than a power supply voltage. 2. Claims characterized in that the oscillation output signal supplied to the input of the plate voltage generation circuit is delayed compared to the oscillation output signal supplied to the input of the substrate bias generation circuit. The semiconductor memory according to item 1. 3. The plate voltage generation circuit is formed by a voltage detection circuit that receives the output voltage of the substrate bias voltage generation circuit, and is a gate circuit whose gate is opened by a signal output when the output voltage reaches a predetermined voltage level. 2. The semiconductor memory according to claim 1, wherein the oscillation output signal is input and supplied through the semiconductor memory. 4. The semiconductor memory according to claim 1, 2 or 3, wherein the MOS capacitor is a Mizohori capacitor.