JPS61264932A - Digital data multiplexer - Google Patents

Abstract

PURPOSE:To realize the multiplex level of a digital data by using a time slot conversion circuit to replace multiplexed data, using a separation circuit to separate the data thus processed and giving the result to the 2nd and 3rd buses. CONSTITUTION:A multiplexed data 41a from a data bus 41 and a multiplexed data 42a from a data bus 42 are multiplexed further by a multiplexing circuit 16 and inputted to a time slot conversion circuit 17 as a multiplex highway input 16a. After the time slot is replaced under the control of a time slot conversion control circuit 18 in the circuit 17, the result is inputted to a multiplexing and separation circuit 19 as a multiplexed highway output. The data is separated into two systems of data strings in the circuit 19, one data string 43a is outputted to the 3rd data bus 43 connected to terminal interface circuit 13-15 and the other data string 44a is outputted to the 4th data bus 44 connected to line interface circuits 21-23. Thus, plural terminal equipments are connected optionally to plural high speed digital lines.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is directed to multiplexing digital data from multiple telephones, data terminals, etc., and connecting the multiplexed digital data to multiple high-speed digital lines provided by Nippon Telegraph and Telephone Company, etc. The present invention relates to a digital data multiplexing device that enables.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional digital data multiplexing device. In the figure, 1 is a data terminal, 2 is a telephone set, and these are terminal interface circuits 1 and 2, respectively.
1.12 to the multiplexing circuit 3. 4 is a multiplexing control circuit, 5 is a line interface circuit, 6 is the entire block of the digital data multiplexer, and 7 is a termination device on the subscriber side of the high-speed digital line, which is usually called a DSU (data line termination unit).

Next, the operation will be explained. Signals from the data terminal 1, primarily the telephone, undergo processing such as format conversion or analog/digital conversion in the terminal interface circuits 11 and 12, and then are input to the multiplexing circuit 3, where they are sent to the multiplexing control circuit 4. The control signal 4 is multiplexed into a signal with a predetermined transmission rate, frame synchronization bits and service pits are added in the line interface circuit 5, and the C
After MI code conversion, DSU of high-speed digital line
7 is output. Conversely, for the signal sent from the DSU 7, the CMI code is converted into a unipolar code in the line interface circuit 5, and after timing extraction and frame synchronization are performed, the signal of the channel that can be used by the user is sent to the multiplexing circuit 3. The multiplexed signal is separated under the control of the multiplexing control circuit 4 and input to each terminal interface circuit 11, 12, etc. In the terminal interface circuit 11 to which the data terminal 1 is connected, data is received by the data terminal 1 in a predetermined data format after processing such as speed conversion and format f conversion.

In addition, the terminal ink 7 circuit 1 to which the telephone 2 is connected
2, the signal is received by the telephone as an analog voice signal after processing such as speed conversion and digital/analog conversion. In addition to data terminals and telephones, terminal devices include data modems, PBXs (Private Area Network Digital Exchanges), video conferencing equipment, and LANs (Looal Area Networks).
) can also be connected by simply replacing the terminal interface circuit. Note that here, for convenience, a processing circuit that has a multiplexing function and a demultiplexing function is simply referred to as a multiplexing circuit as mentioned above, and a control circuit that similarly has multiplexing control and demultiplexing control functions is simply referred to as a multiplexing circuit. This is referred to as the conversion control circuit 4, and the same expression will be used below.

FIG. 5 shows digital data multiplexing devices 6m and 5b similar to those shown in FIG. 4 connected to a plurality of high-speed digital lines.

[Problem that the invention seeks to solve]

Since the conventional digital multiplexing device is configured as described above, when connecting it to a high-speed digital line as shown in Fig. 4, the 0807m,
The same number of digital data multiplexing devices as the digital data multiplexing device 7b are required, and the data terminals 1& and the telephone 2a accommodated in the digital data multiplexing device 6a in FIG. 5 are connected to the digital data multiplexing device 6b.
There was a problem in that the data terminal 1b and the telephone 2b could not be connected to the DSU 7a connected to the digital data multiplexing device 6a. Ma4, D8 [77m
The signal from D is passed through a digital data multiplexer.
In the case of relaying to the SU 7b, terminal interface circuits of the same type must be connected back to each other as shown in connection 8, which poses problems such as not being able to be constructed economically.

This TLA was developed to solve the problems mentioned above, and it is possible to connect multiple high-speed digital lines with one digital data multiplexer, and also connect terminals to different high-speed digital lines. The purpose of the present invention is to provide a digital data multiplexing device that can change line settings as shown in FIG. .

[Means for solving problems]

The digital data multiplexing device according to the present invention performs frame phase synchronization and bit phase synchronization on data from terminals, etc. in the plurality of interface circuits, further speed converts the data, and transmits this speed converted data to the first bus multiplexing control. The data is sent to the first data bus based on the circuit's data sending command, and the data on the second data bus is received in response to the data receiving command, and the data from the high-speed digital line is code-converted in the plurality of line interface circuits. , performs frame phase synchronization and bit phase synchronization to further convert the speed, and sends the speed-converted data to the third data bus based on the data sending command of the second bus multiplexing control circuit, and also sends the speed-converted data to the third data bus based on the data sending command of the second bus multiplexing control circuit. The data on the fourth data bus is received, the data on the first and third data buses are multiplexed onto one signal line by a multiplexing circuit, and this multiplexed data is sent to a time slot conversion circuit to time the data on the first and third data buses. The structure is such that the slots are exchanged, and the data resulting from this operation is separated by a separation circuit and supplied to the second and third data buses.

[For production]

In the digital data multiplexing device according to the present invention, data from the terminal interface circuit and data on the line interface circuit side are multiplexed once and time slot conversion is performed by the time slot conversion circuit, so that data from the terminal device can be converted into any high-speed digital data. In addition to being able to connect to the line, some of the data from the high-speed digital line
It also becomes possible to loop back the data using a digital data multiplexer and relay it to another high-speed digital line. Further, since the data bus of the digital data multiplexing device of the present invention multiplexes only significant data passing through the terminal interface circuit and the line interface circuit, the operating speed of the time slot conversion circuit O can be kept to the necessary minimum. , it becomes possible to increase the sum of the effective data rates of the terminal devices and high-speed digital lines that can be accommodated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 13, 14, and 15 are terminal interface circuits, 31 is a bus multiplexing control circuit on the terminal side, and 41.4 is a terminal interface circuit.
3 is a data bus to which a terminal interface circuit is connected;
21, 22, 23H line interface circuits, 32 a bus multiplexing control circuit on the line side, and 42, 44 a data bus connected to the line interface circuits. 16 is a multiplexing circuit that multiplexes the signals of the two data buses 41 and 42; 17 is a time slot conversion circuit; 18 is a time slot conversion control circuit that controls the time slot conversion circuit 17; 19 is a time slot conversion circuit 17 This is a demultiplexing circuit that separates the output of -11 and sends it to two data buses 43 and 44.

Next, the operation will be explained. Signals from the terminal devices are input to terminal interface circuits 13 to 15, and in each terminal interface circuit, speed conversion and frame phase synchronization are performed to facilitate bus multiplexing, and then the signals are sent to the bus multiplexing control circuit 31. Only significant data is multiplexed onto the first data bus 41 under the control of the first data bus 41. On the other hand, the signal from the high-speed digital line D8U is sent to the line interface circuit 2.
1 to 23, and each line interface circuit 21 to
23 is CMI/Unipo 2 code conversion.

Processing such as timing extraction and frame synchronization is performed, frame phase synchronization is established, and after speed conversion, significant data is transferred to the second data bus 42 under the control of the bus multiplexing control circuit 32 on the line side. only multiplexed. data bus 4
The multiplexed data 41 from 1 and the multiplexed data 42m from the data bus 42 are further multiplexed by the multiplexing circuit 16 and input to the time slot conversion circuit 17 as a multiplexed highway input 16 &. Here, after the time slots are replaced as appropriate under the control of the time slot conversion control circuit 18, the signal is inputted to the demultiplexing circuit 19 as a multiplexed high-way output. The demultiplexing circuit 19 separates data into two data streams, one of which is
43a is output to the third data bus 43 connected to the terminal interface circuits 13 to 15, and the other data string 4
4. is output to the fourth data bus 44 connected to the line interface circuits 21-23. The data on the third data bus 43 is bus-demultiplexed under the control of the bus multiplexing control circuit 31 on the terminal side, inputted to each predetermined terminal interface circuit 13 to 15, and then transferred to each terminal interface circuit 13. ~15, after processing such as speed conversion, the data is output to the terminal device. On the other hand, the fourth data bus 44
The above data is bus demultiplexed under the control of the bus multiplexing control circuit 32 on the line side and input to each predetermined line interface circuit 21 to 23, and each line interface circuit 21 to 23 performs speed conversion. , CMI code conversion, addition of synchronization bits, etc., the high-speed digital line DS
Output to U. In the above description, the data input to and output from the terminal interface circuits 13 to 15 may be data from a single terminal or multiplexed data from a plurality of terminals. In addition, the path multiplexing control circuit 31
32 is an address control memory (ACM) in which predetermined addresses are given to the terminal interface circuits 13 to 15 and line interface circuits 21 to 23 in advance.
This can be realized by sequentially selecting these addresses based on the output of , and opening and closing input/output gates.

In the above operation, the time slot) ffi conversion circuit 17
1 by performing time slot switching control in
It is now possible to connect data from fixed terminal devices to any high-speed digital line.

Further, if a part of the data on the high-speed digital line is controlled to be looped back by the time slot conversion circuit 17, it becomes possible to relay the data to another high-speed digital line. This type of function will be explained in more detail using the timing diagrams of FIGS. 2 and 3. now.

The first terminal interface circuit 13 and the first line interface circuit 21 as well as the second terminal interface circuit 14 and the second line interface circuit 22 are both
．． Assuming that signals are being sent and received at a data rate of 56 Mb/s, the data bus speed is 6.144 Mb/s.
A case where multiplexing is performed with b/, will be explained.

Now, let the data group from the first terminal interface circuit 13 be a person, and let the data group from the second terminal interface circuit 14 be B. If the data groups from the second line interface circuits 21 and 22 are represented as C and D, the state of the multiplexed data on each data bus 41 to 44 can be shown as shown in FIG. Here, since the data bus speed is 6.144 Mb/s, the l frame is 768 bits, and each data group of 1.536 Mb/s is formed from 192 bits of data per frame, and the second half of each frame is 768 bits long. 384 bits are empty bits. Multiplexed signal on data bus 41m, 4
2m are arranged as shown in FIG. 3, and this signal is converted by the multiplexing circuit 16 into 12.288 M b7. with a data rate of 5.144 M/.02 times. The multiplexed signal 1 is multiplexed by interleaving 1 bit at a time.
B, the time slot conversion circuit 170 random access memory (hereinafter referred to as RAM) is arranged in sequence.
written to. This RAM has a double buffer configuration, and data is written in one frame and read out in the order of 7)'L/s supplied from the time slot conversion control circuit 18. This ibis.

If the output data string from the RAM is read out in the array shown at 19m in FIG. ．． 44. As shown in FIG. 2, the data groups of the terminal interface circuit 13 appear on the data bus in an arrangement such that they are output to the line interface circuit 21, and the data groups B, C, and D are similarly output from the corresponding terminals. Connections are made between the Iyl face circuit 14*15 and the line interface 7A circuit 22,23. Furthermore, when changing the time slots, by changing only the bit arrangement of a specific channel to a different setting, some of the data from the terminal interface circuits 13' to 15 can be changed to different line interface circuits 21 to 15. 23 or to relay part of the data from one line interface circuit to another line interface circuit.

In addition, in one or more embodiments, the data bus speed is 6.144 Mb.
Although an example in which the time slot conversion circuit operates at /s is shown, other operating speeds may be used, and the operating speed of the time slot conversion circuit can be changed accordingly.

〔Effect of the invention〕

As described above, according to the present invention, the outputs of the terminal interface circuit and the line interface circuit are speed-converted and multiplexed onto the corresponding first and third data buses, and these two data After further multiplexing the bus to form a highway and performing time slot conversion in a time slot conversion circuit composed of a group of random access memories, demultiplexing the highway output and supplying it to the second and fourth data buses; Since the configuration is such that data is transferred from these two data buses to the terminal interface circuit and the line interface circuit, respectively,
Multiple terminals can be arbitrarily connected to multiple high-speed digital lines, line settings can be changed to connect terminals to different high-speed digital lines, and signal relay between multiple high-speed digital lines can be realized at the multiplexing level. Furthermore, since only data that is significant for the operating speed of the data bus is multiplexed, it is possible to maximize the number of terminal devices and high-speed digital lines that can be accommodated.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram of a digital data multiplexing device according to an embodiment of the present invention, and FIG. 2 is a timing diagram showing data strings of signals to be multiplexed and signals to be separated.
FIG. 3 is a timing diagram of a data stream for explaining time slot conversion, FIG. 4 is a block connection diagram of a conventional digital data multiplexing device, and FIG. 5 is an example of its application. 13.14.15 is a terminal interface circuit. 16 is a multiplexing circuit, 17 is a time slot conversion circuit, 1
9 is a separation circuit, 21, 22.23 is a line interface circuit, 31.32 is a bus multiplexing control circuit, 41 is a first data bus, 42 is a third data bus, 43 is a second data bus, 44f1g4 data bus. Special plan applicant Mitsubishi Electric Corporation - 1 Agent Patent attorney 1) Hiroshi Sawa I. (2 others) Figure 3 Figure 4 Building 5 Figure 6 &

Claims (1)

[Claims] Data from a terminal, etc. is speed-converted by performing frame phase synchronization and bit phase synchronization, and the speed-converted data is sent to the first data bus based on the data sending command of the first bus multiplexing control circuit. A plurality of terminal interface circuits receive data on the second data bus in response to a receive command, and the data from the high-speed digital line is converted to speed by performing code conversion, frame phase synchronization, and bit position matching, and the speed converted data is processed. a plurality of line interface circuits that transmit data to a third data bus based on a data transmission command of the second bus multiplexing control circuit and receive data on a fourth data bus according to a data reception command; a multiplexing circuit that multiplexes data on a data bus and a third data bus onto a single signal line; a time slot conversion circuit that swaps time slots of the data multiplexed by the multiplex circuit; The conversion circuit separates the data subjected to the time slot swapping operation and transfers the data to the second data bus and the fourth data bus.
A digital data multiplexing device comprising a separation circuit for supplying a data bus to a digital data bus.