JPS61264834A - Multi-processor system control system - Google Patents

Multi-processor system control system

Info

Publication number
JPS61264834A
JPS61264834A JP10600885A JP10600885A JPS61264834A JP S61264834 A JPS61264834 A JP S61264834A JP 10600885 A JP10600885 A JP 10600885A JP 10600885 A JP10600885 A JP 10600885A JP S61264834 A JPS61264834 A JP S61264834A
Authority
JP
Japan
Prior art keywords
station
slave
processing program
slave station
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10600885A
Other languages
Japanese (ja)
Inventor
Shoji Kobayashi
昭二 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP10600885A priority Critical patent/JPS61264834A/en
Publication of JPS61264834A publication Critical patent/JPS61264834A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)
  • Multi Processors (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)

Abstract

PURPOSE:To decentralize the peak load of a master station to slave stations by providing a process control computer to the master station and a controller using a microprocessor to each slave station so as to give the same effect as that brought about by the execution of a processing program by a master station CPU. CONSTITUTION:The master station CPU 1 executes the program and applies the state input request of a circuit breaker CB13 of a slave station 2. A processing program required for the processing is transferred by the microprocessor (MPU) 2-3 of the slave station 2 via a data way 9-1 from the CPU 1. The MPU 2-3 receives the processing program, executes it and inputs the state of a circuit breaker 3 via a process input/output controller 2-4. After the end of processing of the circuit breaker 3, the state input processing of a circuit breaker 4 is executed. Then it is discriminated that the data of the circuit breaker 4 is obtained from the MPU 2-3 of the slave station 2 and the processing program is transferred from the MPU 2-3 to the MPU 2n-3 of the slave station 2 by a similar method.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は、マルチ・プロセッサシステム制御方式、特に
主局から複数の従局を制御するマルチ・プロセッサシス
テム制御方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multi-processor system control method, and particularly to a multi-processor system control method for controlling a plurality of slave stations from a master station.

[発明の技術的青票] 以下、電力系統制御の場合を例に説明する。[Technical blueprint for invention] The case of power system control will be explained below as an example.

電力系統設備のうち、例えば送電線、変圧器等は、その
保守作業のために時間を限定して停止され、保守作業完
了時に復旧される。
Among power system facilities, for example, power transmission lines, transformers, etc. are stopped for a limited time for maintenance work, and are restored when the maintenance work is completed.

これらの設備を停止/復旧させるためには、しゃ断器、
ラインスイッチ、接地、各種保護リレー等の機器を入/
切、又は使用/ロック等の操作をする必要がある。
In order to stop/restore these facilities, circuit breakers,
Connect equipment such as line switches, grounding, and various protective relays.
It is necessary to perform operations such as turning off, using/locking, etc.

例えば、送電線を停止/復旧させるためには、その線路
に接続される、一般的には遠く隔れた電気所(変電所)
全てについて、関係する機器操作を順序正しく、誤りな
く、速やかに実行する必要がある。
For example, in order to stop/restore a power transmission line, an electric station (substation) connected to the line, typically far away, must be used.
All related equipment operations must be performed in an orderly, error-free, and prompt manner.

このため、従来は第5図に示す如く、主局1にプロセス
制御用計算機1−1、データ伝送装@1−2を備え、従
局2及び2nは夫々データ伝送装置2−1.20−1、
制御装置2−2,2n−2を備えて、これらの間をデー
タ伝送装置で結合した構成としていた。そして主局1に
おいて、予め操作手順を実行する処理プログラムを生成
、記憶しておき、操作開始時刻到来時に、順次主局1か
ら各従局に対して操作信号を伝送し、従局に接続される
機器の操作を主局にある個別指示によって実施していた
For this reason, conventionally, as shown in FIG. 5, the main station 1 is equipped with a process control computer 1-1 and a data transmission device @1-2, and the slave stations 2 and 2n are equipped with a data transmission device 2-1, 20-1, respectively. ,
The control device 2-2 and 2n-2 were provided, and these were connected by a data transmission device. Then, in the master station 1, a processing program for executing the operation procedure is generated and stored in advance, and when the operation start time arrives, the master station 1 sequentially transmits operation signals to each slave station, and the equipment connected to the slave stations is Operations were carried out according to individual instructions from the main station.

[背景技術の問題点] 電力系統運用におけるこの種の操作は、一般的には頻繁
に、しかも複数の独立した設備が、朝、夕の同一時間帯
に行なわれることが多く、各々の設備に付帯する操作対
象機器の数は膨大な岳になる。
[Problems in the background art] This type of operation in power system operation is generally performed frequently, and moreover, is often performed on multiple independent pieces of equipment at the same time in the morning and evening. The number of attached devices to be operated is enormous.

このため、主局1のプロセス制御用計算機1−1の負荷
がピークに達し、充分な応答性が得られず1、その結果
、速やかな操作が阻害される場合もあった(参考資料二
東芝レビュー、1982年4月号、vOし 37、 N
n5)  。
As a result, the load on the process control computer 1-1 of the main station 1 reached its peak, making it impossible to obtain sufficient responsiveness1, and as a result, prompt operations were sometimes impeded (Reference Material 2 Toshiba Review, April 1982 issue, vOshi 37, N
n5).

[発明の目的] 本発明は上記問題点を解決するためになされたものであ
り、主局のピーク負荷を従局に分散させる様にしたマル
チ・プロセッサシステム制御方式を提供することを目的
としている。
[Object of the Invention] The present invention was made in order to solve the above problems, and an object of the present invention is to provide a multi-processor system control method that distributes the peak load of the main station to the slave stations.

[発明の概要] 本発明では、主局にプロセス制御用計算機、従局にマイ
クロプロセッサを用いた制御装置を置き、各々をリング
状にデータウェイで結合した構成とし、主局計算機にて
機器操作のための処理プログラムを生成し、これを操作
対象機器の接続される従局にデータウェイを介して廻送
し、必要な機器操作を、その機器の接続された従局にて
処理プログラムステップを実行することにより実施し、
必要な全ての従局に対して処理プログラムを廻送後、主
局に戻し、主局CPUにては、処理プログラムを実行し
たことと同等の効果を生じさせるものである。
[Summary of the Invention] In the present invention, a process control computer is placed in the main station, a control device using a microprocessor is placed in the slave station, and each is connected in a ring shape by a data way, and the main station computer controls equipment operations. Generate a processing program for the operation, send it to the slave station connected to the device to be operated via the data way, and execute the processing program steps in the slave station connected to the device to perform the necessary device operation. carried out by
After the processing program is transmitted to all necessary slave stations, it is returned to the master station, and the master station CPU produces the same effect as executing the processing program.

[発明の実施例] 以下図面を参照して実施例を説明する。第1図は、本発
明によるマルチ・プロセッサシステム制御方式を説明す
るための一実施例の構成図である。
[Embodiments of the Invention] Examples will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment for explaining a multi-processor system control method according to the present invention.

第1図において、各従局にはデータ伝送装置2−1.2
n−1、マイクロプロセッサ2−3.2n−3及びプロ
セス入出力制御装置2−4.2n−4を備え、主局と各
従局との間、及び従局間はデータウェイ9−1を介して
相互に接続し、データの高速交換が出来る構成を有して
いる。
In Figure 1, each slave station has a data transmission device 2-1.2.
n-1, a microprocessor 2-3.2n-3 and a process input/output control device 2-4.2n-4, and communication between the main station and each slave station and between the slave stations is via a data way 9-1. They have a structure that allows them to be interconnected and exchange data at high speed.

第2図(a)は主局CPU 1の機能ブロック図であり
、設備の停止/復旧のための任意の処理プログラムを作
成するプログラム生成機能10−1、任意の従局に対し
て処理プログラムを発送する発送機能10−2、任意の
従局から処理プログラムを受信する受領機能10−3、
及び実行開始制御機能10−4を有している。なお、1
0−5は処理プログラムである。
FIG. 2(a) is a functional block diagram of the main station CPU 1, which includes a program generation function 10-1 that creates an arbitrary processing program for stopping/restoring equipment, and sends the processing program to an arbitrary slave station. a sending function 10-2 for receiving processing programs; a receiving function 10-3 for receiving processing programs from any slave station;
and an execution start control function 10-4. In addition, 1
0-5 are processing programs.

第2図(b)は、従局の機能ブロック図であり、前記主
局同様の各機能を有している。なお、10−6は入出力
制t[1機能である。
FIG. 2(b) is a functional block diagram of the slave station, which has the same functions as the master station. Note that 10-6 is an input/output system t[1 function.

次に、動作を説明するため、ある送電線の停止に関して
、従局2に接続されるしゃ断器CB1.3、接地用ライ
ンスイッチLS1.5、及び従局2nに接続されるCB
2.4、接地用ラインスイッチLS2.6を、予め決め
られた順序で誤りなく、入/切操作を行なう方法を例に
とる。
Next, in order to explain the operation, regarding the stoppage of a certain power transmission line, the breaker CB1.3 connected to slave station 2, the grounding line switch LS1.5, and the CB connected to slave station 2n will be explained.
2.4. Let us take as an example a method for turning on/off the grounding line switch LS2.6 in a predetermined order without error.

今、主局CPt11にて、プログラム生成機能10−1
により、処理プログラム10−5が生成される。当処理
プログラム10−5には、プロセス・データの入/出力
の出来る局番号が格納されている。
Now, on the main station CPt11, program generation function 10-1
As a result, a processing program 10-5 is generated. The processing program 10-5 stores station numbers from which process data can be input/output.

本処理プログラムを実行するため、先ず、主局CPU 
1にて本処理プログラム10−5を実行する。
In order to execute this processing program, first, the main station CPU
1, the main processing program 10-5 is executed.

第3図(a)、(b)は、動作説明のフローチv−1・
、第4図(a)、 (b)は機器状態入力要求処理及び
復器操作要求処理である。
FIGS. 3(a) and 3(b) show the flowchart v-1 for explaining the operation.
, FIGS. 4(a) and 4(b) show the device status input request process and the restorer operation request process.

先ず、最初は、ステップP1にて従局2のCB1.3の
状態入力要求を行なう。この時、CB1.3のデータは
従局2の)IPIJ 2−3から得られ、従局2のHP
U 2−3に対する処理プログラムの転送要求P3が行
なわれる。
First, in step P1, a status input request for CB1.3 of slave station 2 is made. At this time, the data of CB1.3 is obtained from IPIJ 2-3 of the slave station 2, and the data of CB1.3 is obtained from the slave station 2's HP
A processing program transfer request P3 is made to U2-3.

この結果、主局CPυ1の発送機能10−2が起動され
、データウェイ9−1を介して、従局2のHPU 2−
3に対して、従局2のHPU 2−3にて処理プログラ
ムを続行するために必要なデータ、つまりプログラムロ
ジック、中間データ及びプログラムカウンタ(以下、こ
れらを総称して“処理プログラム”と記す)が転送され
る。
As a result, the sending function 10-2 of the master station CPυ1 is activated, and the HPU 2- of the slave station 2 is activated via the data way 9-1.
3, the data necessary to continue the processing program in the HPU 2-3 of slave station 2, that is, program logic, intermediate data, and program counter (hereinafter collectively referred to as "processing program") is be transferred.

プログラムカウンタは、処理プログラムの実行中、位置
を示すためのカウンタである。
The program counter is a counter that indicates the position during execution of a processing program.

従局2では、従局2 (7) HPU 2−3(7)受
領機能10−3が起動され、処理プログラム10−5を
受取り、プログラムカウンタに示される位置から受領し
た処理プログラム10−5を実行し、入出力制御機能1
0−6及びプロセス入出力制御装置2−4を介してCB
1.3の状態を入力する。
In the slave station 2, the slave station 2 (7) HPU 2-3 (7) receiving function 10-3 is activated, receives the processing program 10-5, and executes the received processing program 10-5 from the position indicated by the program counter. , input/output control function 1
0-6 and the CB via the process input/output control device 2-4.
1. Enter the status of 3.

CB1に関する処理を完了後、CB2状態入力処理P4
を実行する。この時、CB2.4データが従局2のHP
U 2−3より得られることが判定され、同様の方法に
より、処理プログラム10−5が従局2のHPU 2−
3から、従局2nのHPU 2n−3へ転送される。
After completing the process related to CB1, CB2 status input process P4
Execute. At this time, CB2.4 data is the HP of slave station 2.
It is determined that the processing program 10-5 can be obtained from the HPU 2-3 of the slave station 2, and in a similar manner, the processing program 10-5 is obtained from the HPU 2-3 of the slave station 2.
3, it is transferred to HPU 2n-3 of slave station 2n.

この様に、処理プログラム10−5は、その処理ステッ
プを実行するために必要なプロセス・データの入出力の
出来る従局のHPUに順次転送される。
In this way, the processing program 10-5 is sequentially transferred to the slave HPU that can input and output process data necessary to execute the processing steps.

処理プログラム10−5終了時には、終了処理P13を
実行することにより、主局CPU 1に転送され(第3
図(b))、主局CPU 1で終了状態を検出し、1設
備の操作を完了させる。
When the processing program 10-5 ends, it is transferred to the main station CPU 1 by executing the end processing P13 (the third
(b)), the main station CPU 1 detects the end state and completes the operation of one equipment.

本発明に用いたデータウェイは、ネットワーク型データ
交換器を用いたデータ・ネットワークに直き換えても、
発明の本質は変らない。
Even if the dataway used in the present invention is directly replaced with a data network using a network type data exchanger,
The essence of invention remains the same.

[発明の効果] 以上説明した如く、本発明によれば下記効果が得られる
[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

■負荷が分散され、応答性の改善が図れる。■Load is distributed and responsiveness can be improved.

主局の負荷が従局の処理分散により軽減される。The load on the master station is reduced by distributing processing among the slave stations.

特にピーク時の負荷が平滑化される。In particular, peak loads are smoothed out.

■従局マイコンが小型化出来る。■Slave station microcontroller can be downsized.

従局マイコンにて実行する処理プログラムは、必要に応
じて、主局又は他の従局に転送されるため、複数の処理
プログラムによる同一資源の多重使用が可能となる。こ
のため、装置の小型化、低廉化が可能となる。
Since the processing program executed by the slave station microcomputer is transferred to the master station or other slave stations as necessary, multiple use of the same resource by a plurality of processing programs is possible. Therefore, the device can be made smaller and less expensive.

■機能の拡張が容易に出来る。■Functionality can be easily expanded.

従局にて実行するプログラムは、主局にて生成されるた
め、主局で任意の機能を持つプログラムを作り、従局の
手直しを行なわず、実行させることが出来る。
Since the program executed by the slave station is generated by the master station, a program having any function can be created in the master station and executed without modifying the slave station.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるマルチ・プロセッサシステム制御
方式を説明する一実施例の構成図、第2図は主局及び従
局の機能ブロック図、第3図は動作説明のフローチャー
ト、第4図は機器状態入力要求及び機器操作要求処理を
示す図、第5図は従来方式を説明する図である。 1・・・主局(CPU)      2.2n・・・従
局1−1・・・プロセス制御用計算機 1−2.2−1.2n−1・・・データ伝送装置2−2
.2n−2・・・制御装置 2−3.2n−3−?イクロプロセッサ(HPU)2−
4.2n−4・・・プロセス入出力制御装置3.4・・
・CB 5.6・・・LS(接地用ラインスイッチ)7.8・・
・母線      9−1・・・データウェイ10−1
・・・プログラム生成機能 1σ−2・・・発送機能     10−3・・・受領
機能10−4・・・実行開始制mum能 10−5・・・処理プログラム 10−6・・・入出力制御機能 (7317)代理人 弁理士 則近憲佑(他1名) 第2図 (α9 (b) 、第4図
Fig. 1 is a block diagram of an embodiment of the multi-processor system control method according to the present invention, Fig. 2 is a functional block diagram of a master station and a slave station, Fig. 3 is a flowchart explaining the operation, and Fig. 4 is a diagram of equipment. FIG. 5 is a diagram showing the state input request and device operation request processing, and is a diagram explaining the conventional method. 1...Main station (CPU) 2.2n...Slave station 1-1...Process control computer 1-2.2-1.2n-1...Data transmission device 2-2
.. 2n-2...control device 2-3.2n-3-? Microprocessor (HPU) 2-
4.2n-4...Process input/output control device 3.4...
・CB 5.6...LS (grounding line switch) 7.8...
・Bus line 9-1...Data way 10-1
...Program generation function 1σ-2...Sending function 10-3...Receiving function 10-4...Execution start control function 10-5...Processing program 10-6...Input/output control Function (7317) Agent Patent attorney Kensuke Norichika (and 1 other person) Figure 2 (α9 (b), Figure 4)

Claims (1)

【特許請求の範囲】[Claims] 主局のプロセス制御用計算機からの制御指令をデータウ
ェイを介して複数従局へ伝送して、各従局を制御する電
力系統制御システムにおいて、各従局には個々にマイク
ロプロセッサを備えてこれらを相互にデータウェイによ
りリング状に結合し、主局計算機にて機器操作のための
処理プログラムを予め生成、記憶しておき、機器操作を
必要とする従局に対して、前記処理プログラムを廻送す
ることにより、従局マイクロプロセッサにて対応する処
理プログラムのステップを実行し、全ての従局マイクロ
プロセッサに対して、前記処理プログラムを廻送後に、
主局に戻すことを特徴とするマルチ・プロセッサシステ
ム制御方式。
In a power system control system that transmits control commands from a process control computer in a master station to multiple slave stations via a dataway to control each slave station, each slave station is equipped with an individual microprocessor and these stations are mutually controlled. By connecting in a ring shape through a data way, a master station computer generates and stores a processing program for operating equipment in advance, and transmits the processing program to slave stations that require equipment operation. , execute the steps of the corresponding processing program in the slave microprocessor, and after transmitting the processing program to all slave microprocessors,
A multi-processor system control method characterized by returning data to the main station.
JP10600885A 1985-05-20 1985-05-20 Multi-processor system control system Pending JPS61264834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10600885A JPS61264834A (en) 1985-05-20 1985-05-20 Multi-processor system control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10600885A JPS61264834A (en) 1985-05-20 1985-05-20 Multi-processor system control system

Publications (1)

Publication Number Publication Date
JPS61264834A true JPS61264834A (en) 1986-11-22

Family

ID=14422646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10600885A Pending JPS61264834A (en) 1985-05-20 1985-05-20 Multi-processor system control system

Country Status (1)

Country Link
JP (1) JPS61264834A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0311945A (en) * 1989-06-08 1991-01-21 Hitachi Ltd Supervisory control method and device for power system
US5408176A (en) * 1988-03-21 1995-04-18 Blatt; David W. E. Monitoring and fault protection of high voltage switch yards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408176A (en) * 1988-03-21 1995-04-18 Blatt; David W. E. Monitoring and fault protection of high voltage switch yards
JPH0311945A (en) * 1989-06-08 1991-01-21 Hitachi Ltd Supervisory control method and device for power system

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