JPS61264821A - Ternary output circuit - Google Patents

Ternary output circuit

Info

Publication number
JPS61264821A
JPS61264821A JP60106517A JP10651785A JPS61264821A JP S61264821 A JPS61264821 A JP S61264821A JP 60106517 A JP60106517 A JP 60106517A JP 10651785 A JP10651785 A JP 10651785A JP S61264821 A JPS61264821 A JP S61264821A
Authority
JP
Japan
Prior art keywords
potential
transistor
point
diode
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60106517A
Other languages
Japanese (ja)
Inventor
Kenshiro Okamura
岡村　健史郎
Takao Tosaka
登坂　高夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60106517A priority Critical patent/JPS61264821A/en
Publication of JPS61264821A publication Critical patent/JPS61264821A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To decide easily a potential being always stable without being affected by a load connected to an output terminal by providing the 3rd transistor (TR) and plural diodes and connecting them as specified. CONSTITUTION:When a TR 13 is turned on, an output potential point 7 goes nearly to a common potential. When the point 7 is nearly at the common potential, a current going to flow from a base of a TR 10 through the collector is blocked by a diode 8, then no problem is caused. When both the TRs 13, 11 are turned off, the point 7 goes to nearly a power supply potential. When the TR 13 is turned off and the TR 11 is turned on, since the base of the TR 10 is at a constant potential, the collector potential of the TR 10 is constant regardless of a load connected to the point 7. Then the potential at the point 7 is decided easily by the number of diodes connected between the base of the TR 10 and a high potential point 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、１つの出力端子よシ３種の電位を得るために
用いる３値出力回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a three-value output circuit used to obtain three types of potential from one output terminal.

〔従来の技術〕[Conventional technology]

従来よシ、この種の３値出力回路として、第２図に示す
ような回路がある。図において、１は電源電位である高
電位点、２は接地電位である低電位点、３はそのコレク
タが高電位点１に接続されると共に、エミッタがＮＰＮ
）ランジスタ４のコレクタに接続され九ＮＰＮ）ランジ
スタ、５はその一端が高電位点１に接続され、その他端
が抵抗６の一端に接続された抵抗である。トランジスタ
４のエミッタは低電位点２および抵抗６の他端に接続さ
れておシ、抵抗５と抵抗６との接続点およびトランジス
タ３のエミッタとトランジスタ４のコレクタとの接続点
に出力端子７が接続されている。Conventionally, there is a circuit as shown in FIG. 2 as this type of three-value output circuit. In the figure, 1 is a high potential point that is a power supply potential, 2 is a low potential point that is a ground potential, and 3 is a collector connected to the high potential point 1, and an NPN emitter.
9 NPN) transistor 5 is connected to the collector of transistor 4, and 5 is a resistor whose one end is connected to the high potential point 1 and the other end is connected to one end of the resistor 6. The emitter of the transistor 4 is connected to the low potential point 2 and the other end of the resistor 6, and the output terminal 7 is connected to the connection point between the resistance 5 and the resistance 6 and the connection point between the emitter of the transistor 3 and the collector of the transistor 4. It is connected.

次に、このように構成された出力回路の動作を説明する
。すなわち、トランジスタ３がオンし、トランジスタ４
がオフしたときの出力端子７の電位は、トランジスタ３
のコレクタとエミッタとの電位差によって決マシ、略電
源電位となる。また、トランジスタ３がオフし、トラン
ジスタ４がオンしたときの出力端子７の電位は、トラン
ジスタ４のコレクタとエミッタとの電位差によシ決まシ
、略接地電位となる。更に、トランジスタ３および４が
ともにオフしたときの出力端子７の電位は、抵抗５およ
び抵抗６の抵抗値によって決まる。この様に、トランジ
スタ３および４の動作によって出力端子７は、電源電位
、接地電位および抵抗５゜６によって決まる中間電位の
３種の電位に変わシ得る。Next, the operation of the output circuit configured as described above will be explained. That is, transistor 3 is turned on and transistor 4 is turned on.
The potential of the output terminal 7 when the transistor 3 is turned off is
This is determined by the potential difference between the collector and emitter of , which is approximately the power supply potential. Further, when the transistor 3 is turned off and the transistor 4 is turned on, the potential of the output terminal 7 is determined by the potential difference between the collector and emitter of the transistor 4, and becomes approximately the ground potential. Furthermore, the potential of output terminal 7 when both transistors 3 and 4 are turned off is determined by the resistance values of resistor 5 and resistor 6. In this manner, the output terminal 7 can be changed to three potentials by the operation of the transistors 3 and 4: the power supply potential, the ground potential, and an intermediate potential determined by the resistor 5.6.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来のこのような出力回路によると、ト
ランジスタ３および４をともにオフにした場合を考えて
みるに、抵抗６を流れる電流！。However, according to such a conventional output circuit, if we consider the case where both transistors 3 and 4 are turned off, the current flowing through resistor 6! .

は、抵抗５を流れる電流■１　と出力端子７よシ外部の
負荷へ流出する電流Ｉ、との差、即ちＩ、−■、となる
。しかるに、出力端子７の電位は抵抗６の抵抗値をＲ６
とすると、Ｒｓ　　（Ｌ　　Ｉｔ）となシ、外部の負荷
に流出する電流Ｉ、に比例して変動することになる。更
に、高電位点１から低電位点２には、トランジスタ３お
よび４の状態によらず抵抗５および６を通して電流が流
れ、消費電力が問題となシ、この消費電力を小さくする
ために、抵抗６の抵抗値Ｒ６を大きくする必要があシ、
Ｒ６を大きくすると出力端子７の電位変動が増加してし
まう。is the difference between the current (1) flowing through the resistor 5 and the current I flowing out from the output terminal 7 to an external load, that is, I, - (2). However, the potential of the output terminal 7 increases the resistance value of the resistor 6 by R6.
Then, Rs (L It) will vary in proportion to the current I flowing out to the external load. Furthermore, current flows from high potential point 1 to low potential point 2 through resistors 5 and 6 regardless of the states of transistors 3 and 4, and power consumption is a problem. It is necessary to increase the resistance value R6 of 6.
If R6 is increased, potential fluctuations at the output terminal 7 will increase.

つｔｂ、出力端子フの電位は、抵抗６の抵抗値とこの抵
抗６を流れる電流とによって決まり、この抵抗６を流れ
る電流値は出力端子７に接続される負荷によって変化す
るので、容易に出力端子７の電位を決定することが出来
ないという問題があった。tb, the potential of the output terminal F is determined by the resistance value of the resistor 6 and the current flowing through this resistor 6, and since the current value flowing through this resistor 6 changes depending on the load connected to the output terminal 7, it is easy to output There was a problem that the potential of the terminal 7 could not be determined.

本発明はこのような問題点を解消するためになされたも
ので、その目的とするところは、出力端子に接続される
負荷に影響されず、常に安定した電位を出力すると共に
、この出力電位を容易に決定することのできる３値出力
回路を提供することにある。The present invention was made to solve these problems, and its purpose is to always output a stable potential without being affected by the load connected to the output terminal, and to maintain this output potential. The object of the present invention is to provide a three-value output circuit that can be easily determined.

〔問題点を解決するための手段〕[Means for solving problems]

このような目的を達成するために、本発明は、高電位点
に抵抗を介して第１のダイオードのアノードを接続し、
このダイオードのカソードに第１のトランジスタのコレ
クタを接続し、このトランジスタのエミッタに抵抗を介
して第２のトランジスタのコレクタを接続し、この第２
のトランジスタのエミッタおよび低電位点に第３のトラ
ンジスタのエミッタを接続し、この第３のトランジスタ
のコレクタを前記第１のダイオードのアノードに接続し
、前記第１のトランジスタのベースに第２のダイオード
のカソードを接続し、このダイオードのアノードを高電
位点に接続すると共に、第３のトランジスタのコレクタ
と第１のダイオードとの接続点を出力電位点としたもの
である。To achieve such an objective, the present invention connects the anode of the first diode to a high potential point via a resistor,
The collector of a first transistor is connected to the cathode of this diode, the collector of a second transistor is connected to the emitter of this transistor via a resistor, and the collector of a second transistor is connected to the emitter of this transistor via a resistor.
an emitter of a third transistor is connected to the emitter of the transistor and a low potential point, a collector of the third transistor is connected to the anode of the first diode, and a second diode is connected to the base of the first transistor. The anode of this diode is connected to a high potential point, and the connection point between the collector of the third transistor and the first diode is set as an output potential point.

〔作用〕[Effect]

したがって、この発明による出力回路によれば、出力電
位点よシ出力される中間レベルの電位を、第１のトラン
ジスタのエミッタ、コレクタ間電圧および第２のダイオ
ードのアノード、カソード間電圧によシ容易に決定する
ことができる。Therefore, according to the output circuit according to the present invention, the intermediate level potential outputted from the output potential point can be easily converted into the emitter-collector voltage of the first transistor and the anode-cathode voltage of the second diode. can be determined.

〔実施例〕〔Example〕

以下、本発明に係る３値出力回路を詳細に説明する。第
１図はこの出力回路の一実施例を示す回路図である。同
図において、８は電流制限用の抵抗９を介してそのアノ
ードが高電位点１に接続された第１のダイオード、１０
はこのダイオード８のカソードにそのコレクタが接続さ
れた第１ＯＮＰＮ　）ランジスタ、１１はこのトランジ
スタ１０のエミッタに電流制限用の抵抗１２を介してそ
のコレクタが接続された第２ＯＮＰＮ）ランジスタ、１
３はこのトランジスタ１１のエミッタおよび低電位点２
にそのエミッタが接続された第３ＯＮＰＮトランジスタ
である。この第３のトランジスタ１３のコレクタはダイ
オード８のアノードおよび出力電位点７に接続されてお
シ、第１のトランジスタ１００ベースは第２のダイオー
ド１４０カソードに接続されている。そして、ダイオー
ド１４のアノードが第３のダイオード１５のカソードに
接続され、このダイオード１５のアノードが高電位点１
に接続されている。尚、１６および１７はトランジスタ
１１および１３のベースに接続された信号入力端子であ
る。Hereinafter, the three-value output circuit according to the present invention will be explained in detail. FIG. 1 is a circuit diagram showing one embodiment of this output circuit. In the figure, 8 is a first diode whose anode is connected to the high potential point 1 via a current limiting resistor 9;
is a first ONPN) transistor whose collector is connected to the cathode of this diode 8; 11 is a second ONPN) transistor whose collector is connected to the emitter of this transistor 10 via a current limiting resistor 12;
3 is the emitter of this transistor 11 and the low potential point 2
and a third ONPN transistor having its emitter connected to. The collector of this third transistor 13 is connected to the anode of the diode 8 and the output potential point 7, and the base of the first transistor 100 is connected to the cathode of the second diode 140. The anode of the diode 14 is connected to the cathode of a third diode 15, and the anode of this diode 15 is connected to the high potential point 1.
It is connected to the. Note that 16 and 17 are signal input terminals connected to the bases of transistors 11 and 13.

次に、このように構成された出力回路の動作を説明する
。すなわち、トランジスタ１３がオンの場合、出力電位
点７が略接地電位となる。出力電位点７が略接地電位の
時、トランジスタ１０のベースからコレクタを通って流
れようとする電流はダイオード８によって阻止されるの
で問題はない。Next, the operation of the output circuit configured as described above will be explained. That is, when the transistor 13 is on, the output potential point 7 becomes approximately the ground potential. When the output potential point 7 is approximately at ground potential, there is no problem because the current that attempts to flow from the base of the transistor 10 through the collector is blocked by the diode 8.

トランジスタ１３および１１がともにオフ状態の場合は
、出力電位点７は略電源電位となる。更に、トランジス
タ１３がオフ状態で、トランジスタ１１がオン状態の場
合は、トランジスタｌＯのベースは定電位であるため、
トランジスタｌＯのコレクタ電位は出力電位点７に接続
される負荷によらず一定電位となる。ダイオード８，１
４．１５のアノード、カソード間の電圧を各々Ｖ！畠ｔ
　Ｖ？１４　ＨＶ？１１とし、トランジスタ１００ベー
ス、エミッタ間電圧をＶｍｍｔｏとし、コレクタ、エミ
ッタ間電圧をｖｅｌｌＩＯとし、電源電位なＶｅｃとす
ると、出力電位点７の電位Ｖｏは、 ＶＯ＝Ｖｅｅ　　Ｖｔ＋ｓ　　Ｖｅｃ４−Ｖｍｍｔｏ＋
Ｖｅｍｔｏ士Ｖｔ畠＝　Ｖｅｃ　−２ｖ？、　Ｂ　＋　
Ｖｅ　ｍｔ　。When transistors 13 and 11 are both off, output potential point 7 is approximately at the power supply potential. Furthermore, when the transistor 13 is off and the transistor 11 is on, the base of the transistor lO is at a constant potential, so
The collector potential of the transistor IO remains constant regardless of the load connected to the output potential point 7. diode 8,1
The voltage between the anode and cathode of 4.15 is V! Hataket
V? 14 HV? 11, the voltage between the base and emitter of the transistor 100 is Vmmto, the voltage between the collector and emitter is VELLIO, and the power supply potential is Vec, then the potential Vo at the output potential point 7 is: VO=Vee Vt+s Vec4-Vmmto+
Vemtoshi Vt Hatake = Vec -2v? , B+
Ve mt.

となシ、出力電位点７の電位はトランジスタ１００ベー
スと高電位点１との間に接続するダイノードの数によシ
容易に決定できる。In addition, the potential of the output potential point 7 can be easily determined by the number of dynodes connected between the base of the transistor 100 and the high potential point 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明による３値出力回路によると
、高電位点に抵抗を介して第１のダイオードのアノード
を接続し、このダイオードのカソードに第１のトランジ
スタのコレクタを接続し、このトランジスタのエミッタ
に抵抗を介して第２のトランジスタのコレクタを接続し
、この第２のトランジスタのエミッタおよび低電位点に
第３のトランジスタのエミッタを接続し、この第３のト
ランジスタのコレクタを前記第１のダイオードのアノー
ドに接続し、前記第１のトランジスタのベースに第２の
ダイオードのカソードを接続し、このダイオードのアノ
ードを高電位点に接続すると共に、第３のトランジスタ
のコレクタと第１のダイオードのアノードとの接続点を
出方電位点としたので、出力電位点よシ％Ｈルベル、％
Ｌルベルおよび中間レベルの電位を出力することができ
、中間レベルの電位を第１のトランジスタのエミッタ、
コレクタ間電圧および第２のダイオードのアノード、カ
ソード間電圧によシ決定することができる。すなわち、
出力電位点に接続される負荷に対して安定した電位を出
力することができ、かつ中間電位の値を第２のダイオー
ドの数を変えることにより容易に決定することが可能と
なる。As explained above, according to the three-value output circuit according to the present invention, the anode of the first diode is connected to a high potential point via a resistor, the collector of the first transistor is connected to the cathode of this diode, and the transistor The collector of the second transistor is connected to the emitter of the first transistor through a resistor, the emitter of the third transistor is connected to the emitter of the second transistor and the low potential point, and the collector of the third transistor is connected to the emitter of the first transistor. the anode of the second diode is connected to the base of the first transistor, the anode of this diode is connected to a high potential point, and the collector of the third transistor and the first diode are connected to each other. Since the connection point with the anode is set as the output potential point, the output potential point is
L level and an intermediate level potential can be output, and the intermediate level potential is outputted to the emitter of the first transistor,
It can be determined by the voltage between the collector and the voltage between the anode and cathode of the second diode. That is,
A stable potential can be output to the load connected to the output potential point, and the value of the intermediate potential can be easily determined by changing the number of second diodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る３値出力回路の一実施例を示す回
路図、第２図は従来の３値出力回路を示す回路図である
。 １・、・・・高電位点、２・・・・低電位点、７・・・
・出力電位点、８・・・・第１のダイオード、９，１２
・・・・抵抗、１０・・・・第１のトランジスタ、１１
１Ｉ・・・第２のトランジスタ、１３・・・・第３のト
ランジスタ、１４−・・・第２のダイオード、１５・・
・・第３のダイオード。FIG. 1 is a circuit diagram showing an embodiment of a three-value output circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional three-value output circuit. 1...High potential point, 2...Low potential point, 7...
・Output potential point, 8...First diode, 9, 12
...Resistor, 10...First transistor, 11
1I...second transistor, 13...third transistor, 14-...second diode, 15...
...Third diode.

Claims (1)

【特許請求の範囲】[Claims] 高電位点に抵抗を介してそのアノードが接続された第１
のダイオードと、このダイオードのカソードにそのコレ
クタが接続された第１のトランジスタと、このトランジ
スタのエミッタに抵抗を介してそのコレクタが接続され
た第２のトランジスタと、このトランジスタのエミッタ
および低電位点にそのエミッタが接続されると共にその
コレクタが前記第１のダイオードのアノードに接続され
た第３のトランジスタと、前記第１のトランジスタのベ
ースにそのカソードが前記高電位点にそのアノードが接
続された第２のダイオードとを備え、前記第３のトラン
ジスタのコレクタと前記第１のダイオードのアノードと
の接続点を出力電位点とした事を特徴とする３値出力回
路。a first whose anode is connected to a high potential point via a resistor;
a first transistor whose collector is connected to the cathode of this diode, a second transistor whose collector is connected to the emitter of this transistor via a resistor, and the emitter of this transistor and a low potential point. a third transistor having its emitter connected to and its collector connected to the anode of said first diode, its cathode connected to the base of said first transistor, and its anode connected to said high potential point. a ternary output circuit, comprising a second diode, and a connection point between the collector of the third transistor and the anode of the first diode is an output potential point.
JP60106517A 1985-05-17 1985-05-17 Ternary output circuit Pending JPS61264821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60106517A JPS61264821A (en) 1985-05-17 1985-05-17 Ternary output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60106517A JPS61264821A (en) 1985-05-17 1985-05-17 Ternary output circuit

Publications (1)

Publication Number Publication Date
JPS61264821A true JPS61264821A (en) 1986-11-22

Family

ID=14435599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60106517A Pending JPS61264821A (en) 1985-05-17 1985-05-17 Ternary output circuit

Country Status (1)

Country Link
JP (1) JPS61264821A (en)

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