JPS61262934A - Data processor and data transmission line - Google Patents

Abstract

PURPOSE:To attain smoothly data processing by supplying data automatically from a data processor when a register at the preceding stage is idle and constituting an asynchronous data processor. CONSTITUTION:The data are outputted from a parallel data buffer B1 and the buffer B1 is going to be idle. This fact is detected by the corresponding C element C1 and delivers a signal AKO in the form of a high place. Thus the signal AKO is supplied to the C element C2 at the next stag in the form of a high-order signal AKI. Here a signal TRO obtained from a signal C2 obtained from the corresponding element C2 is set at a high-order. Then the signal TRO is supplied to the element C1 at the preceding stage via a data processor 54 in the form of a signal TRI of a high-order in case data exist at a parallel data buffer B2 at the next stage. Here the signal TRO of a high place is also applied to the buffer B2 as a transfer command signal. Thus a data packet loaded in the buffer B2 is outputted to the buffer B1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device, and particularly to a data-driven data processing device.

(Prior Art) Neumann type data processing devices have drawbacks such as slow speed and difficulty in parallel processing due to sequential processing. Therefore, recently, data driven type (data flow type) data processing apparatuses have been proposed and implemented. An example of such a data-driven data processing device is disclosed, for example, in Nikkei Electronics, published on April 9, 1980, pages 181 to 218.

In conventional data-driven data processing devices, FIF
Data is transferred from the FTF memory to the processing unit through a synchronous path.

(Problems to be Solved by the Invention) In a data-driven processing device, the processing flow is not uniform because the processing starts from the one that is fired. Therefore, conventionally, as described above, a plurality of buffer memories (FTFO memory) and processing elements were connected using a synchronous lotus.

In such conventional data processing devices, the capacity of the FTF○ memory is greatly affected by the speed and timing of firing, so all (this FIFO to ensure smooth processing)
Designing or selecting memory capacity is extremely difficult. Therefore, in reality, it is necessary to design the FIFO appropriately.
Processing is stopped when the amount of data becomes too large.

On the other hand, in order to avoid such a situation, a special overflow processing mechanism may be employed to control continuation and stop of input for each part. However, such a processing mechanism becomes complicated in terms of hardware.

Therefore, the main object of the present invention is to provide a data-driven data processing device that can perform data processing smoothly.

(Means for Solving the Problems) To put it simply, the first invention is arranged between the registers in the former stage and the latter stage, and the registers in the former stage and the latter stage, and receives data from the latter stage and processes it. Data processing means for giving the result to the register in the previous stage, empty detection means for detecting the empty space in the register in the previous stage, and output from the register in the latter stage in response to the empty space in the register in the previous stage being detected by the empty detection means. a data processing device, comprising: means for transferring the data that has been processed and passed through the data processing means to a register at the previous stage; and an instruction means for instructing the data processing means on the type of processing according to the contents of the register at the previous stage. It is.

In the second invention, push-in and pump-out of data can be performed independently and simultaneously, and the pushed-in data is automatically shifted to a register in the previous stage on the condition that the register in the previous stage is free. This is a data transmission path in which data processing means is arranged between the registers of the data transmission path constructed using self-propelled shift registers.

(Operation) Data is transferred from the previous register to the further previous register. At this time, for example, a processing code included in this data is input to the instruction means.

The instruction means generates a type of processing or a series of types of processing in the data processing means according to the content, and provides it to the data processing means. At this time, the data in the register at the subsequent stage is given to the data processing means, and processing according to the instruction from the instruction means is executed. On the other hand, when the vacancy detection means detects vacancy in the register at the previous stage, the transfer means provides the data that has passed through the data processing means to the register at the previous stage.

(Effects of the Invention) According to the present invention, if the register at the previous stage is empty, data is automatically given from the data processing means.
It can be configured as an asynchronous data processing device. Therefore, depending on the frequency of processing in the processing means,
Processing can be executed smoothly without the need for special buffer control. Further, according to the present invention, it is only necessary to arrange the data processing means between the registers, and repeated data processing can be performed efficiently, and its design is also extremely simple.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

(Embodiment) FIG. 1 is a conceptual system diagram showing an example of a parallel processing type emulator as an example of a data processing device in which the present invention can be implemented. The system 10 includes an asynchronous delay line ring 12 as a data transmission path, a data packet to be processed is given to the asynchronous delay line ring 12 through a merging section 14, and the processed data is outputted through a branching section 16. be done. The data packet given from the merging section 14 passes through the asynchronous delay line ring 12,
It is branched by the branching section 18 and provided to the function storage section 20 . The data read from the function storage section 20 is given to the asynchronous delay line ring 12 again through the merging section 22.

The data packet given from the function storage unit 20 includes a header HD and a plurality of data words DW, -DWn following it, as shown in FIG. 2, for example. header hd
includes a processing code PC and a control code CC, and this processing code PC includes a code indicating a packet structure and a code indicating processing contents. As a code indicating the packet structure, an order code indicating that it is a header or the last data word is given, for example, by the 17th and 16th two bits. A code indicating the processing content is particularly called an F code, and is used to specify the type of processing, such as r+J, r-J, . . . or data replacement or insertion. The control code CC includes node information resulting from the program structure, that is, logical information such as physical destination information and color information.

The data packets as described above transmitted by the asynchronous delay line ring 12 are provided to a first loop-shaped data transmission path 28 forming a firing section 27 through a branching section 24 and a merging section 26 . Different data packets are taken into a second loop-shaped data transmission path 34 forming the firing section 27 through different branching sections 30 and merging sections 32 .

First and second loop-shaped data transmission lines 28 and 3
The data packets given to No. 4 are transmitted through the respective loops in opposite directions, and are given to the firing detecting section 36 which constitutes the firing section 27 together with these transmission paths. The firing detection unit 36 compares the control codes included in each data packet between the two data packets, thereby distinguishing between the data packet existing two days above the first loop-shaped data transmission path and the second data packet. A new data packet is generated based on the specific data packet detected as a data packet pair. The new data packet generated in this manner is placed, for example, on the first loop-shaped data transmission path 28 and is brought onto the asynchronous delay line ring 12 again through the branching section 38 and the merging section 40.

A new data packet transferred on the asynchronous delay line ring 12 is transferred to the arithmetic processing unit 44 through the branching unit 42, for example.
and then processes the single or multiple pieces of processing target data included in the data packet and following the header according to the processing code included in the header of the data packet. The data processed by the arithmetic processing unit 44 is merged into the asynchronous delay line ring 12 again through the merge unit 46. This processing result is given again to the function storage section 2° or outputted through the branching section 16.

Note that the system 10 further includes a control code processing section 4.
8 and a color management section 5o are provided.

The present invention can be applied to the arithmetic processing section 44 in the system 1o shown in FIG. However, such an arithmetic processing unit 44 is not inserted in parallel with the main data transmission path 12, but is inserted in series with the data transmission path 12, as shown by the dotted line in FIG. good.

FIG. 3 is a schematic block diagram showing one embodiment of the present invention. The arithmetic processing unit 44 includes parallel data buffers 7BO, Bll B2 . B3. ...and C elements (Coin) provided in relation to each of them.
incident Element) Co, C,,C
2, C3,... These parallel data hash sofa B
. -B3 and C elements C3-C3 together constitute an asynchronous free-running shift register.

This asynchronous free-running shift register is capable of independently and simultaneously pushing in and popping out data, and furthermore, the push-in data must be available on the condition that the previous stage register or parallel data buffer is empty. A shift register that automatically transfers data without using a shift clock. Such an asynchronous self-propelled shift register can also be used as the main data transmission line 12 and the looped first and second data transmission lines 28 and 34.

Here, with reference to FIGS. 4 and 5, the C element constituting the asynchronous self-propelled shift register will be described. C
Element C includes six terminals T, ~T6, and terminal T receives a signal TRI (Transfer
In ) is given, and from terminal T2, a signal A KO (Acknowledge Ou
t) is output. A signal TPO (Transfer 0ut) is output from the terminal T3 to the C element in the previous stage, and a signal AK from the C element in the previous stage is output from the terminal T4.
I (Acknowledgement In) is given. Signal TRO is further given to its corresponding parallel data buffer as a transfer command signal. And signal A
KI is given as an empty signal of the preceding stage parallel data processor.

Note that a reset signal RESET is applied to the terminal T5, and a stop signal 5TOP is applied to the terminal T6.

In the circuit shown in FIG. 4, the reset signal RE is sent from the terminal T5.
When SET is given, it is inverted by an inverter and this signal is given to four Nant gates c,
, C4,c,l and G,4 both become high level. Nant Gate G, , G4 and Gl 1 ,
The output of Gl4 is at high level, and therefore the outputs of G3 and G13 that receive it are both at low level. The high level output of the Nandt gate G4 becomes the signal AKO, which is given as the signal AKI from the terminal T2 to the C element at the subsequent stage. This is a signal representing the empty status of the preceding stage parallel datum 7 fur.

At this time, if data has not yet arrived, the signal TR■ to the terminal T1 is at a low level. When the input signals R, BS, and ET to the terminal T5 are released, the output of the inverter becomes high level, while the NAND gate GI4
The signal AK' from is also at high level, and this state is the initial state.

In the initial state, therefore, the Nant gate G +
and Gll are at high level, and one input of OR gate G2 and G12 is at high level. Therefore, the two inputs of Nandts gates G3 and G13 are both at high level, and therefore the outputs of these Nandts gates G3 and CI3 are both at low level. That is, signal TR' and signal TPO from terminal T3 are at low level. Nando game-1-G
The inputs of 4, G, and 4 are low level, high level, and high level, respectively, and these Nant gate G
The outputs of CI4 and CI4 are each at high level.

When the data is transferred and the signal TRI applied to the terminal T1 from the C element in the subsequent stage changes to high level as shown in FIG.

All three inputs of will be high level, and its output will be low level. Then, the output of the Nant gate G3, that is, the signal TR' becomes high level as shown in FIG. 5, and the output of the Nant gate G4 becomes low level. When the signal TR' becomes high level, the Nant gate G3. The output of Nant gate C'+3 becomes low level, the output TPO of Nant gate C'+3 becomes high level, and the output AK' of Nant gate G,4 becomes
becomes low level. Nando game-1-04 and G, 4
The outputs of the gates G3 and GI3 are respectively returned to the inputs of the gates G3 and GI3, and the outputs of the gates G3 and G13 are locked at a high level.

In this way, as shown in FIG. 5, the signal AKO from the terminal T2 becomes low level, indicating that data has been transferred to the corresponding parallel data processor of this C element C. In other words, in that state, data transfer is no longer possible. This is communicated to the subsequent C element that the message is not accepted. Also, Nando Game-1-G
, 3 are at high level, and a high level signal TRO is applied from terminal T3 to the C element at the previous stage. This high level signal TRO is given as a transfer command to the corresponding parallel data buffer, and the data in the parallel data buffer is sent to the previous stage.

When the signal AK◯ goes low, the signal TRI goes low as shown in FIG. 5, and therefore the outputs TR' of the NAND games -1 to G+ return to the high level. moreover,
As described above, when the output AK' of the Nandt gate G14 changes to low level, the output AKO of the Nandt gate G4 returns to the high level, and the output TR' of the Nandt gate G1-03 returns to the low level.

When the signal AKO from the C element in the previous stage, that is, the signal AKI applied from the terminal T4, changes from high level to low level, as shown in FIG. 5, the empty space in the parallel data buffer in the previous stage is extracted. and Orgate G
Since the input of G12 is at low level and the signal TR' is also at low level, the output of this OR gate G1□ is also at low level. At this time, the output of Nante gate GI3 is at a high level, so Nante gate GI4
output changes to high level. Therefore, the input of the Nant gate G13 becomes high level, and the Nant gate G13
output returns to low level. In this way, the state returns to the same state as the initial state.

If the signal AKO from the previous stage C element, that is, the signal AKI from the terminal T4, remains at a low level, that is, if the parallel data buffer corresponding to the previous stage C element is not yet empty, then the Nantes gate G1. Since one of the inputs remains at a low level, even if the signal TRT from the terminal T is given as a high level and the signal TR' changes to a high level, the NAND game 1/C++ does not act and the signal TPO does not go to a high level, thereby refusing to accept data from the subsequent stage, and therefore data cannot be transferred to the parallel data buffer corresponding to this C element in that state.

In this way, a parallel data buffer B, as shown in FIG. -B3 and C elements C8 to C3 constitute an asynchronous self-propelled shift register.

In addition, a stop signal 5TOP is applied to this C element C from the terminal T6.
is given, the high level signal is the OR gate G
5 is given to Nandoge l-G+3. Therefore, this Nantes Gate G.

The output of terminal T3 becomes low level, and in this state, the signal TPO from terminal T3 becomes low level, and data transfer is stopped.

As shown in FIG. 3, a parallel data buffer B forming an asynchronous self-running shift register included in the arithmetic processing unit
1 and B2, for example, Al1 L U (Arithmatic Logic Uni
A data processing element 54 is arranged, including a t) + multiplier and the like. Then, the data from the previous stage parallel data processor B, especially the processing code PC included in the data bucket (
2) is applied to the processing instruction circuit 56. Simply put, this processing instruction circuit 56 is a parallel data buffer B.
, the data processing element 54
An instruction signal is given to instruct the type or mode of data processing. Therefore, when data from the parallel data buffer B2 at the subsequent stage is given to the data processing element 54 and processed there, the content of the processing is controlled by the processing code from the parallel data buffer B at the previous stage. become. In other words, the type of processing or series of types of processing for subsequent data is determined by the preceding data.

FIG. 6 is a block diagram showing one embodiment of the present invention.

The arithmetic processing unit 44 includes the parallel data buffers B and B2, as described above with reference to FIG. 3, and the data processing element 54 is inserted between them. Data processing element 54
includes ALU58 in this example, and this ALU5
The two inputs of 8 have parallel data buffers B1 and B
Data to be processed from 2 (FIG. 2) is given. Then, corresponding to the respective parallel data buffers Bl and B2, C elements C1 and C2 as explained in FIG.
will be provided. The 17th bit (and 16th bit) data of the parallel data buffer B2 is stored in the data processing element 54.
given to. When the 17th bit data is 11'', the data processing element 54 indicates that the data is a header, and the data processing element 54 directly transfers the data from the parallel data buffer B2 to the parallel data buffer B.
, output to. That is, when the data is a header, the data processing element (ALU) becomes NOP.

Processing instruction circuit 56 includes a decoder 60 and a flip-flop group 62. The decoder 60 is given the F code included in the processing code PC (FIG. 2) from the parallel data buffer B at the previous stage, and also receives the I of the 17th bit of data included in the processing code, that is, the sequential code. bit is given. Flip-flop group 6
2 has a C element C1 corresponding to parallel data buffer B.
The empty signal TRO is provided as a trigger input.

The set input of the flip-flop group 62 is connected to the decoder 6.
A signal from 0 is applied, and the 16th bit data included in the processing code PC from the parallel data buffer B1, ie, 1 bit of the order code, is applied to the reset input. The output of this flip-flop group 62 is given again to the decoder 60, and therefore the output of the decoder 6o is held by the flip-flop group 62.

The output of the decoder 60 is given to the ALU 58 included in the data processing element 54 as a processing instruction signal.

In the circuit of FIG. 6, the parallel data buffer B2 at the subsequent stage to the parallel data buffer B at the previous stage.

Data transfer to is controlled by corresponding C elements C2 and C1, respectively, as described above. That is, when data is output from parallel data buffer B, and this parallel data buffer B attempts to remain in an empty state, the corresponding C
Element C8 detects this and outputs signal AKO at a high level.

This signal AKO is input to the subsequent C element C2 as a high level signal AKT. At this time, after.

If data exists in the parallel data buffer B2 of the stage, the signal TPO from the corresponding C element C2 becomes high level,
It serves as a high level signal TRI to the previous stage C element C7.
given to. At this time, since the high-level signal TPO is also given to the parallel data buffer B2 as a transfer command signal, the data packets loaded in the parallel data buffer B2 are output to the preceding parallel data buffer B. .

As mentioned above, when the header of a data packet is input to the preceding stage parallel data buffer B1 via the ALU 58 of the data processing element 54, the F code is input along with the 17th bit data included in the data packet. is applied to decoder 60.

If it is a header of a data packet, the 17th bit signal is at a high level as shown in FIG. 60 decodes the F code input from the parallel data buffer B.

For example, if the F code at that time is rNOPJ, the rNOPJ command is given from the decoder 60 to the ALU 58 included in the data processing element 54. Decoder 60 further generates, for example, "F+1" and provides it as a signal to flip-flop group 62.

It goes without saying that the F code for the first data word DW may be any other suitable unary operation, such as increment or inversion, in addition to rNOPJ as described above.

To explain in more detail, when the processing code of the header of the data packet of the preceding stage parallel data buffer B is inputted to the decoder 60, the decoder 60 provides the ALU 58 with an operation command of, for example, "increment". When data is loaded into the subsequent parallel data bath sofa B2, the ALU 58 executes an "increment" operation. When the C element C1 detects an empty space in the preceding parallel data buffer Bl, the result of the above-mentioned "increment" operation is given to the preceding parallel data buffer Bl at that timing. At this time, at the same time,
r F + from the decoder 60 to the flip-flop group 62
1. J is written. At this point, the data word of the data bucket exists in the preceding parallel data buffer B, and therefore the rF+IJ code from this flip-flop group 62 is valid as an input to the decoder 60. That is, after the header of the preceding parallel data buffer B1 is released by the decoder 60, the decoder 60 receives the code from the flip-flop group 62.

Then, the decoder 60 decodes r F −1−I J from the flip-flop group 62 .

Assuming that the decoder 60 is configured to generate, for example, an arithmetic command of "+" when this rF+IJ is input, after the decoder 60 first outputs an arithmetic command of "increment", this The decoder 60 provides the ALU 58 with a calculation command for "10". Therefore, in the ALU 58, the previous stage parallel data buffer B
, and the subsequent parallel data buffer B2.
Performs a "+" operation with the data from. In this way, the decoder 60 outputs the necessary operation commands until the data in the preceding parallel data bucket B+ becomes the last data word of the data packet, and the ALU
At 58, the corresponding calculation is repeated.

In the last data word, as shown in FIG. 2, one bit of the order code, that is, the 16th pinpoint, goes high. This high level signal is transmitted to the flip-flop group 62.
given as the recent input. Therefore, from then on, the outputs of this flip-flop group 62 become, for example, all zero.

In this way, an operation is performed on one data packet. Then, the type of processing to be performed on the data to be processed from the parallel data buffer B2 in the subsequent stage is specified by the data in the parallel data buffer B in the previous stage. Since data is popped out from the subsequent parallel data buffer B2 on the condition that the previous parallel data buffer B is empty, this arithmetic processing unit 44 must be configured as a completely asynchronous system. I can do it.

FIG. 7 is a block diagram showing another embodiment of the invention. In the embodiment of FIG. 6, the data processing element 54, that is, the AL
In U58, the data of the preceding stage parallel data buffer B, that is, the preceding data and the succeeding stage parallel data buffer B2
That is, the subsequent data is received as input, and the processing result is again given to the parallel data buffer B at the previous stage.

On the other hand, in the embodiment shown in FIG. 7, a data packet having a structure as shown in FIG. 8 is used.

In the data bucket shown in FIG. 8, a data word DW contains a plurality of (in this example, two) pieces of processing target data in parallel, and when this data word is popped out, two
Two pieces of processing target data will be output at the same time. Therefore, in the embodiment of FIG. 7, the ALU 58 included in the data processing element 54 receives only data from the parallel data buffer B2 at the subsequent stage, and provides the result to the parallel data buffer B at the previous stage. However, in this embodiment as well, the processing instruction circuit 56 sends data to the ALU 58 of the data processing element 54 based on the data of the preceding stage parallel data buffer B, that is, the preceding data word.
Processing on subsequent data words at is performed. Also in this FIG. 7 embodiment, the arithmetic processing section 44
It is configured as a completely asynchronous system.

FIG. 9 is a block diagram showing another embodiment of the invention. In the embodiments shown in FIGS. 6 and 7 above, both systems were described as systems that simultaneously process 8-bit data. On the other hand, FIG. 9 shows an embodiment in which 8-bit data is sequentially processed 2 bits at a time.

However, its basic configuration is similar to the previous two embodiments.

The arithmetic processing unit 44 in FIG. 9 includes seven stages of parallel data buffers 11311 to B1
It is configured to include an asynchronous self-propelled shift register consisting of a combination of registers l to cr7.

Note that the parallel data buffers Bll"Bl□ are both
18 bits, with data processing elements 54 . ~546 is inserted. In this example, data processing elements 543-546 both include:
It includes 2-bit ALU, and the data processing elements 54□ are 8
Data processing element 54, including a bit shifter. includes a positive/negative/zero determination circuit. Therefore, in this embodiment, the results calculated by the data processing elements 543 to 546, that is, the four ALUs, are transferred to the data processing element 54 as necessary.
2 or 8 bit shifter and then data processing element 54. That is, the positive/negative/zero determination circuit determines whether the result is positive/negative/zero and is pushed into the parallel data filter Bl+ at the front stage.

Data processing element 54. - 546, the processing instruction circuits 561 - 566 described above with reference to FIGS. 6 and 7 are provided. Each processing instruction circuit 56. ~566 includes a decoder 60 and a group of flip-flops 62.

Decoder 60 for each processing instruction circuit 56° to 566
, from the corresponding parallel data buffer Bll”B10,
The 17th bit is given and flip-flop group 6
As mentioned above, the 16th bit is given to the bit 2.

These processing instruction circuits 56. The decoder 60 included in ~566 achieves the decoding function as shown in Table 1 below.

(Margin below) Table 1 f3f2f1foS4S3S2SIS.

oooooooooo.

011.100111 1000 01.000 110.010000 First four F codes “0000”, 0001”, “0
010" and "0011", outputs 32.S3 and S4 are both aO", and all data processing elements 54. ~546 is N OP (No-O
peration). Then, the following four F codes "o t o o", "'0101", "0110"
” and “0111”, in both cases the output S2
becomes 1". Therefore, as will be described later, only the 2 ALUs included in the data processing elements 543 to 546 are activated.
1001”.

For "1010" and "1011", the output S3 becomes "1" in both cases, and the 8-bit shifter included in the data processing element 54.degree. is activated, as will be described later. The last four F codes "1100", "1101",'
1110" and "1111", in both cases,
The output S4 becomes "1", and as will be described later, the data processing element 54. The positive/negative/zero determination circuit included in is activated.

In this embodiment of FIG. 9, data packets as shown in FIG. 10 are processed. FIG. 10(A) shows the case where the data packet contains only one word of data, and FIG. 10(B) shows the case where the data word 1- contains a plurality of data words DWI to DWn. It shows the case. And two 8-bit data L. ~L7 and R8-R
7, and the result is data L of one of the parallel datums 7 and 7 in the previous stage. It is stored in the position corresponding to ~■7. In addition, in this FIG. 10, f included in the processing code PC. -f3 indicates F code.

2 included in each of the data processing elements 543 to 546
Bit ALU is input and receives input R, as shown in FIG. 11, and receives control signals So, S.

and S2, execute the operation specified by it, and transfer the result to the corresponding 2
Give it to Bittu. Further, the carry signal from this A L tJ is given to the previous stage ΔLU. These 2 Pinot)
ALU performs the functions shown in Table 2 below.

Table 2 S, So Output 0 0 L+R O] L-R 0LORR 11LA'NDR * However, 52-1 NOP when S2-0 The 8-bit shifter included in the data processing element 542 has the configuration shown in FIG. 12, for example. . In other words, if it is an 8-bit shifter, the input is 8 pins 1-. ～■Receives 7 and outputs 8-bit data.

. ~07 is output. Its functions are given in Table 2 below.

(Margins below) Table 3 S, S. Function 0 0 Shift left (arithmetic) 0 1 Shift left (logical) 1 0 Shift right (arithmetic) 1 1 Shift right (logical) * However, 53-1 NOP when S3-0 Data processing element 54. The positive/negative/zero determination circuit included in the circuit has the configuration shown in FIG. 13 and executes the functions shown in Table 4 below.

(Left below) Table 4 S, So Function 0 0 A>O? 01 A≦B? 1 0 A=O? 11 A≠0? *However, when 54-1 S4-0, it is NOP. In this positive/negative/zero judgment circuit, for the functions shown in Table 4, when "True", "FF (hex)"
, when it is “False”, it is “00 (hex)”
'' is outputted and applied to the preceding stage parallel data buffer Bl+.

In the embodiment of FIG. 9 as well, when the empty state of the parallel data buffer in the previous stage is detected by the corresponding C element, data from the parallel data buffer in the latter stage is outputted toward the previous stage. During the data transfer, a data processing element 54 is inserted between each parallel data buffer.
1 to 546, and the processed results are given to the preceding stage parallel data eight sofas.

To explain in more detail, first, data is transferred from the last stage parallel data buffer B1□ to the previous stage parallel data buffer BI.
6, the data processing element 546 (i.e. 2 bits) A, as described in detail in FIG. 6 above.
In L U, the processing shown in Table 2 is executed, and a carry signal, if any, is given to the preceding stage data processing element 545, ie, A LU, through the preceding stage parallel data buffer BI6. Then, the calculation result is sent to the parallel data buffer B in the previous stage.

6 is given to the corresponding 2 bits. Further, when data is transferred from the parallel data buffer B16 to the preceding parallel data buffer BI5, an operation is executed by the data processing element 545, that is, the 2-bin ALU. and,
A carry signal, if any, is applied to the parallel data buffer B, 5, and a carry signal, if any, is applied to the preceding stage data processing element 544, ie, the 2-bit ALU. Similarly, when transferring data from parallel data buffer BI5 to parallel data buffer B14, and from parallel data buffer BI4 to parallel data buffer BI3, data processing elements 544 and 543 are connected, respectively. Chi two two pits) A
Operations are performed in the LU.

Therefore, the calculation results of the two 8-bit data are pushed into the parallel data processor B13 at that stage.

When transferring data from the parallel data buffer B13 to the parallel data buffer BI2, if necessary, the 8-pitton lid included in the data processing element 542 is activated and the functions shown in Table 3 are executed. The result is provided to parallel data buffer BI2. Then, when transferring data from the parallel data buffers B and 2 to the parallel data buffer Bl+, the data processing element 54
The positive/negative/zero determination circuit included in , is activated, the functions shown in Table 4 are executed, and the results are stored in the first-stage parallel data buffer Bl+. In this way, from the series of parallel data buffers B17 to parallel data buffers Bl+
Predetermined data processing is performed along with the data transfer to.

Since the arithmetic processing section 44 as described above is itself an asynchronous system, such an arithmetic processing section or data processing device is connected in series to the asynchronous delay line ring or data transmission path 12 shown in FIG. It is possible to insert In this case, if a series of data processing is distributed as shown in FIG. 9, the time required for each data processing element can be shortened to such an extent that data transmission is not hindered at all. That is, if data processing is configured as an asynchronous system as in the present invention, the data processing function can be directly incorporated into an asynchronous self-propelled shift register used as a data transmission path.

[Brief explanation of the drawing]

FIG. 1 is a conceptual system diagram showing an example of a parallel processing type emulator in which the present invention can be implemented. FIG. 2 is an illustrative diagram showing an example of a data packet to be processed. FIG. 3 is a schematic block diagram showing the principle of this invention. FIG. 4 is a circuit diagram showing the C element. FIG. 5 is a timing diagram for explaining the operation of the C element not shown in FIG. 4. FIG. 6 is a block diagram showing one embodiment of the present invention. FIG. 7 is a block diagram showing another embodiment of the invention. FIG. 8 is an illustrative diagram showing the structure of a data packet to be processed in the embodiment of FIG. FIG. 9 is a block diagram showing another embodiment of the invention. FIG. 10 is an illustrative diagram showing an example of the structure of a data packet to be processed in the embodiment of FIG. FIG. 11 is a block diagram showing a 2-bit A L tJ. FIG. 12 is a block diagram showing an 8-bit shifter. FIG. 13 is a block diagram showing a positive/negative/zero determination circuit. In the figure, 12 is an asynchronous delay line ring (data transmission path), 27 is a firing section, 36 is a firing detection section, 44 is an arithmetic processing section, 54 and 54-, ~546 are data processing elements, 5
6 and 561 to 566 are processing instruction circuits, Bo to B3 and Bll"Bl□ are parallel data buffers, co-03
and CI1 to C1□ indicate C elements. Patent applicant Sanyo Electric Co., Ltd. (3 idiots) Agent Patent attorney Yama 1) Yoshito (1 other person)

Claims (1)

[Scope of Claims] 1 Registers in the preceding stage and the succeeding stage; data processing means disposed between the registers in the preceding stage and the succeeding stage, receiving data from the latter stage, processing it, and providing the data to the register in the preceding stage; an empty space detection means for detecting an empty space in a register; in response to the empty space in the preceding stage register being detected by the empty space detecting means, the data output from the latter stage register and passed through the data processing means is transferred to the preceding stage; A data processing device, comprising: means for transferring data to a register in the previous stage; and an instruction means for instructing a type of processing to the data processing means according to the contents of the register at the previous stage. 2. The data processing device according to claim 1, wherein the data includes a processing code and target data, and the instruction means includes means for decoding the processing code from the preceding register. 3. Means for inputting the target data from the preceding register into the processing means, the processing means inputting the target data from the preceding register and the target data from the succeeding register from the instruction means. 3. The data processing apparatus according to claim 2, further comprising means for processing in accordance with an instruction. 4. The data according to claim 2, wherein the data includes a plurality of the target data, and the processing means processes the plurality of target data from the subsequent register based on an instruction from the instruction means. Processing equipment. 5 A self-propelled type that can push in and pop out data independently and simultaneously, and that pushed-in data is automatically shifted to the register in the previous stage, subject to the availability of the register in the previous stage. A data transmission line configured using a shift register, the data transmission line comprising data processing means arranged between the registers of the self-propelled shift register.