JPS6126113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device capable of digitally processing image information.

Traditionally, image processing has been done in analog
There was no diversity in the processing of image information.

An object of the present invention is to provide a processing device that can perform various processes by processing image information in blocks. The gist of the present invention is to provide an image information processing apparatus that processes image information using a processing apparatus, including a storage means for storing image information consisting of a plurality of pixel signals, and a signal for instructing editing processing related to the image information. an instruction signal generation means for extracting the pixel signals stored in the storage means in units of blocks based on the signal from the instruction signal generation means, and repeating movement of the blocks in the storage means via the processing device; Image information processing characterized by comprising: a pixel signal processing means having a repeating step; and an output means for outputting edited image information by outputting the pixel signal processed by the pixel signal processing means. It is a device.

FIG. 1A illustrates an example of a reading device (conversion means) that reads images such as handwritten characters as electrical signals.

1-1 is a manuscript recording text, 1-2 is a laser beam from a laser oscillator (not shown), 1-3
A rotating polygon mirror 1-4 is rotated at a constant speed by a motor (not shown), and a laser beam 1-4 is scanned by the rotating polygon mirror 1-3 and focused on a document by a known f/theta lens 1-5. scanning position. 1-
6, 1-7, and 1-8 are optical sensors such as photomultipliers for receiving the laser beam reflected by the original 1-1, and in this embodiment, three are arranged to reduce so-called shading. ing.

The original 1-1 is driven at a constant speed in the direction of an arrow 1-9 by means not shown, and the laser beam 1-2 is directed to the laser scanning position 1 by a rotating polygon mirror 1-3.
-4 Scan in the direction of arrow 1-10.

At this time, by detecting the reflected light from the original 1-1 with the optical sensors 1-6, 1-7, and 1-8, it is possible to obtain an electrical signal responsive to the black and white density of the original from the optical sensors.

Further, 1-11 indicates a synchronization optical sensor installed at the laser beam scanning start position, and the signal obtained from the optical sensor 1-11 can be used as a synchronization signal.

FIG. 1B shows another embodiment of the reader, in which instead of deflecting the light beam as in FIG.
A photosensor array 1-12 in which 1000 light emitting diodes are arranged in a straight line is used to sequentially light up the light emitting diodes.

That is, if the light from the photosensor array 1-12 is imaged onto the document 1-1 by the lens 1-13, the light spot will move sequentially over the scanning position 1-4 in the direction of the arrow 1-14 as in FIG. 1A. It moves in the direction.

Therefore, if the optical sensors 1-6 to 1-7 are arranged and the document 1-1 is moved at a constant speed in the direction of the arrow 1-15, then from the optical sensors 1-6 to 1-8, the first
In the same way as explained with reference to FIG. A, it is possible to obtain an electrical signal that responds to the density of the document.

FIG. 2 shows an example of a manuscript recording sentences etc. used in this embodiment. Manuscript 1-1
In this embodiment, a frame 2-1 is provided in which eight lines can be written at a line interval of 10 mm, and text is written as shown in the frame 2-1.

Note that when scanning the original 1-1 in FIG. 2 with the image reading device shown in FIG. 1, each row is divided into an integer number of scanning lines (64 in this embodiment).
The document feeding speed and the light scanning speed are determined so that the document is scanned.

FIG. 3 is a block diagram showing an embodiment of the editing device according to the present invention, and 3-1 is an image reading device as shown in FIG. After the electrical signal is converted to a binary signal of 0 or 1 level,
It is applied to the control device 3-2.

This control device 3-2 includes RAM3-3 and ROM3.
-4 and a central processing unit 3-5;
ROM3-4 by the instruction switch installed in -6.
A program stored in the switch is selected and the process instructed by the switch is executed. 3-
Reference numeral 7 indicates an image memory connected to the control section 3-2, and the switch 3 of the operation section 3-6
-8, the reading device 3-
1, and has a capacity sufficient to store at least one page worth of information as shown in FIG. 1.
Similarly, 3-9 is an image memory, which can sequentially store the binary signals obtained from the reading device 3-1 by driving the switch 3-10 of the operation section 3-6. be. The memory 3-9 stores certain sentences and symbols in advance (for example, trademarks, idiomatic sentences in letters, etc.).
The pattern may be stored as a dot signal.

Reference numeral 3-11 indicates a display device such as a CRT, which displays the contents of the image memory 3-7 by driving the switch 3-12 of the operation section 3-6. -13, the contents of the image memory 3-9 are displayed.

3-14 is a light pen, and as is well known, the position on the display 3-11 indicated by the light pen, in other words, the address on the image memory 3-7 or 3-9, can be recognized and read into the RAM.

Reference numeral 3-15 indicates a printer, which can print image information on the image memory 3-7 by driving a switch 3-16 of an operation section 3-6.

The operation section 3-6 further includes an erase switch 3-17 and an insert switch 3-18, and as will be described in detail later, the contents of the image memory 3-7 can be changed by commands from these switches. It is possible to erase images or insert other image information.

FIG. 4 shows the image memories 3-7 and 3-9 in more detail.
This shows the configuration of addresses 7, 3-9.

That is, the image memories 3-7 and 3-9 have addresses 0 to 999 in the X-axis direction and addresses 0 to 512 in the Y-axis direction.
It even has an address, and by specifying X and Y, it is possible to specify a specific location in the memory.

In this embodiment, each row of the document in FIG.
) is scanned and read sequentially, and stored in the image memory 3-
The shading is binarized into 7 or 3-9 and stored.

In this case, the frame 2-1 of the original 1-1 in FIG. 2 is divided into 1000 horizontal positions and 512 vertical positions (64×8). That is, it is decomposed into 1000 x 512 pixels (dots) and stored in the image memory 3-7 or 3-9 with the horizontal position corresponding to X and the vertical position corresponding to Y.

The synchronizing optical sensor 1-11 shown in FIG. 1A is used for timing when a binarized signal is stored in the image memory 3-7 or 3-9.

FIG. 5 is a diagram showing an editing pattern displayed on the display screen (for example, CRT) of the display device 3-11 shown in FIG.

5-1 in FIG. 5 is a number indicating the position in the X-axis direction and corresponds to the address in the X-direction in FIG.
2 is a number indicating the number of lines, and by displaying these numbers, the position of the image can be indicated.

The relationship between N indicating the number of rows and the address in the Y-axis direction in FIG. 4 is that in the present invention, 64 laser scanning lines constitute one row, so the N1th row is 64
The Y-axis position is expressed as ×(N1-1)≦Y<64×N1.

Since it would be complicated to represent the image position by X, Y, the Y direction will be numbered by row, and the image position will be represented by the address (X, N).

For example, 5-3 in the 1st column in the vertical direction of the 3rd row is X=
440(2), N=3, and the shaded area 5-4 is indicated by 560≦X<950, N=4.

If FIG. 5 and FIG. 2 are correlated, the image on the document in FIG.
7 is stored as a dot pattern.

Here, the operation of the control unit 3-2 in the case of deleting a text will be explained.

From position 5-5 to position 5-6 in the 6th row of Figure 5
The diagonally shaded area up to one column before , that is, in the sixth diagram, gives a feeling of uneasiness.
An example of deleting the part will be described below. As will be described later, by this deletion operation, images after position 5-6 are moved starting from position 5-5, and images after position 5-6 are sequentially packed from position 5-5 onwards. In order to generalize and explain the operation,
-5 is represented by the address X=X ₁ , N=N ₁ , and similarly, the position 5-6 is represented by the address X=X ₂ , N=N ₂ . That is, the image address of the starting point of the portion to be deleted is (X ₁ , N ₁ ), and the image address of the next position of the ending point is (X ₂ , N ₂ ).

To perform deletion as described above, first drive the switch 3-17 to select the deletion program stored in the ROM 3-4.

The deletion program has an outline as shown in the flowchart of FIG. 7, and will be explained below according to this flowchart.

Incidentally, the processing device 3-5 in FIG. 3 includes an increment circuit 3-1 as is well known.
9. It goes without saying that a comparison circuit 3-20, an arithmetic circuit 21, and a decrement circuit 22 are included, and a part of the RAM 3-3 includes areas Xa,
Na，Xb，Nb，Xc，Nc，Xe，Ne，Xd，Nd，
are formed, and each area contains information.
Xa, Na, Xb, Nb, Xc, Nc, Xd, Nd, Xe,
Ne, is stored.

Also, in the following explanation, Xa and Na indicate areas in RAM, Xa and Na indicate addresses stored in Xa and Na, and [(Xa) (Na)] indicates (Xa) (Na)
This indicates the information stored at the address indicated by .

Now, as mentioned above, after pressing the switch 17, point the position 5-5 on the display 3-11 with the light pen 3-14, and the addresses X1 and N1 will be displayed in the RAM.
are stored in areas Xa and Na. Next, when the light pen points to the position 5-6 on the display 3-11, the addresses X2 and N2 are stored in the RAM areas Xb and Nb.

Therefore, in such a state, (Xa)=X1,
(Xb)=X2, (Na)=N1, (Nb)=N2. Since it is a common practice to store input information in a specific location in a storage device as described above, a detailed description thereof will be omitted here.

In this way, X1,
When N1, X2, and N2 are stored, 7 is shown in Figure 7.
- Perform the steps indicated in 1.

That is, address (Xb) (Nb) on memory 3-7
Move the information to address (Xa) (Na). To explain with reference to FIG. 5, information at position 5-6 is brought to position 5-5.

After such processing is completed, step 7-2 is entered and the X address is incremented by 1 in order to form the X address from which information is to be read next.

That is, the information (Xb) in the area Xb is read out, incremented by "1" by the increment circuit 3-19, and then stored in the area Xb again.

After such processing is completed, the program enters step 7-3, and checks whether address X, the read address formed as described above, exists in the memory 3-7. In other words, a constant stored in advance in ROM
1000 (this number is 1 larger than the maximum value of address X of memory 3-7), information (Xb) is read from area )but
Determine whether it is less than 1000.

If (Xb) is not <1000, the X address exceeds the maximum value, so step 7-4 is performed to perform a line feed.

That is, 0 is stored in Xb to set (Xb) = 0, and information (Nb) of area Nb is read out and applied to the increment circuit 3-19 to set (Nb) to 1.
After increasing, store it in Nb again.

After the address has been changed to the new line address in this way, the process goes to step 7-5, and it is checked whether or not address N of the read address formed as described above exists in the memory 3-7. In other words, constant 9 is stored in ROM in advance (this value is stored in memory 3-7).
(This is a number that is 1 larger than the maximum value of
At the same time, information (Nb) is read from area Nb, and both are compared by a comparison circuit 3-20 to determine whether (Nb) is smaller than 9 or not.

If (Nb) is not smaller than 9, memory 3
Since it has exceeded the area of -7 (memory 3-7 has 1<N<8), it stops ("END") at this point.

When (Xb)<1000 in step 7-3, or (Nb)<9 in step 7-5
When this happens, the read address exists on the memory 3-7, and the process proceeds to step 7-6 for forming a new address for writing the information read from the read address.

That is, information (Xa) in area Xa is read out and applied to the increment circuit 3-19, (Xa) is incremented by 1, and this increased value is stored in Xa again.

After such processing is completed, the program enters step 7-7 and checks whether address X, the write address formed as described above, exists on the memory 3-7. In other words, the constant stored in the ROM
1000 is read out, and (Xa) is read out from the area Xa, and both are compared by the comparison circuit 3-20 to determine whether (Xa) is smaller than 1000 or not.

If (Xa) is not <1000, it means that the X address exceeds the maximum value, so step 7-8 is performed to perform a line feed.

This step 7-8 is similar to the step 7-4.
Replace (Xb) with (Xa), , (Nb) with (Na)
, so detailed explanation will be omitted.

After the step 7-7 is completed, (Xa)<1000
Otherwise, after step 7-8 is completed, the process returns to step 7-1 and repeats the cycle.

In this way, this cycle can be completed in step 7-
If the process continues until (Nb) < 9 in Figure 5, the shaded area in Figure 5 will be removed, and the information after position 5-6 will be transferred to position 5-5
It will be stored subsequently.

Next, we will discuss the case where information stored in the memory 3-9 is inserted into a part of the memory 3-7.
-6, the switch 3-18 is pressed to select the insertion program as shown in FIG. 8 stored in the ROM and execute the insertion.

That is, first, the memory 3-7 is connected to the display 3-7.
11 and indicate the desired insertion point using the light pen 3-14.

For example, in FIG. 5, if information on the memory 3-9 is to be inserted into position 5-5, addresses X1, N1 of the insertion location are stored in RAM areas Xa, Na.

Next, drive the switch 3-13 to
9 on the display 3-11 and indicate the start point (X3N3) and end point X4, N4 of the information to be inserted with the light pen 3-14, the address of the start point is stored in the area XcNc of RA. , the end point address is stored in RAM areas Xd and Nb. . However, the address of the end point is also stored in the area XeNe for later processing.

After storing the necessary address in the RAM in this way, first check whether there is enough space in the memory 3-7 for insertion.

As a preprocessing for such a check, it is calculated how many rows and columns of information there are to be inserted.

That is, in step 8-1, the X coordinate information (Xd) of the end point of the insertion information is read out from the RAM area Xd, and the coordinate information (Xc) of the starting point is read out from the RAM area.
The calculation circuit 3-21 performs (Xd)-(Xc), and the comparison circuit 3-20 compares whether the calculation result is 0 or greater than 0.

If NO, go to step 8-2, area Xd
The information (Xd) read from the sum and the constant 1000 read from the ROM are added by the arithmetic circuit 3-21, and the result is stored in the RAM area Xe.

In addition, the information (Nd) read from the area Nd is applied to the decrement circuit 3-22 and subtracted by 1.
This reduced information is stored in the RAM area Ne.

If YES in step 8-1,
Alternatively, after the signal that completed step 8-2 is applied again to step 8-1, step 8-2 is applied again.
3 will be performed.

In this step 8-3, the information (Xc) of the area Xc is calculated from the information (Xe) of the area Xe by the arithmetic circuit 3.
−21, and apply this subtraction result to the area Xe
It is stored in . (The result of this subtraction is also stored in the RAM area Xb for later processing.) Next, processing 8-4 is entered, where (Nc) is subtracted from the information (Ne) in the area Ne, and the calculation result is region
Store in Ne. (The result of this subtraction is also stored in the RAM area Nb for later processing.) If the processing up to step 8-4 is completed, the amount of information to be inserted is (Ne).
Represented by rows + (Xe) columns.

Therefore, the insertion information ((Ne) line +
(Xe) column) is checked to see if there is enough space to insert it.

That is, in step 8-5, the memory 3
The address (Xa) of the insertion point of -7 is read from the area Xa, and the information (Xe) is read from the area Xe, both are added by the arithmetic circuit 3-21, and the result is stored in the area Xe. Similarly, information (Na) and (Ne) are added and the addition result is stored in area e.

Next, in step 8-6, it is checked whether (Xe) occupies one or more rows. That is, the comparison circuit 3-20 compares whether (Xe) is less than 1000 (columns constituting one row), and if it is less, the process goes to step 8-8, and if it is not, the process goes to step 8-7.

In other words, if it is not small, it means that (Xe) has a length of one line or more, so step 8
-7 subtracts 1000 from (Xe) and stores the result in Xe, increments (Ne) and stores the result in Ne.

(Xe) (Ne) after processing in step 8-6 or 8-7 indicates the number of rows with complete information and the remaining columns after inserting the information into memory 3-7. , by comparing whether (Ne)<9 in step 8-8, it can be determined whether the information to be inserted can fit into the memory 3-7.

In order to create space in the memory 3-7 by the length corresponding to the length of the insertion information when it can be inserted into the memory 3-7, the space creation program shown in FIG. 8B is executed, and the space creation program shown in FIG. 7, there is no need to create a space and it is sufficient to simply transfer from memory 3-9 to memory 3-7, so the transfer program shown in FIG. 8C is executed.

Figure 8B shows a program that creates a space for the text to be inserted as described above.
In Figure A, all the sentences to be inserted are in memory 3.
Since it has been determined that the image can be stored within -7, in FIG. 8B, it is sufficient to shift the image at the address after the insertion position to the rear by an amount equivalent to the length of the text, etc. to be inserted.

That is, in step 8-9, the constant 8 stored in the ROM is read out, and (Nb) is read out from the RAM area Nb, and the arithmetic circuit 3
-21, calculate 8-(Nb) and use this result as Nb
Store in. Also, constant 999 stored in ROM
At the same time, (Xb) is read from the RAM area Xb, and the arithmetic circuit 3-21 calculates 999-(Xb), and stores this result in Xb.

Then address (Xb) (Nb) and memory 3-
The space between address 999, the end point of 7, and 8 is the space corresponding to the information to be inserted, so the address (Xb)
Move the information of (Nb) to address 999, 8, and move the information of address (Xb)-1, (Nb)-1 to address 998, 8.
By moving the information at addresses (Xb)-2 and (Nb)-2 to addresses 997 and 8, and so on until the insertion position, the inserted statement will be inserted after the insertion position. It is possible to create a space corresponding to the length.

Therefore, the smell in step 8-10 is stored in memory 3-
The last addresses 999 and 8 of 7 are stored in areas Xe and Ne.

In step 8-11, (Xb) (Nb)
Transfer the information of the address indicated by to the address (Xe) (Ne). Since the transfer of one piece of information has been completed through these steps, next step 8-12 is to transfer the area to return one address to be read for transfer.
Circuit 3-22 that decrements Xb information (Xb)
is applied to subtract “1”, and the subtracted information is applied to area Xb
Store in.

Steps 8-13 and 8-14 are for determining whether or not the address to be read for transfer has reached the insertion position Xa, Na.
-13, it is determined whether (Nb) is not equal to (Na). If they are equal, further step 8-1
Information read from area Xb in 4 (Xb)
and the information (Xa) read from Xa are compared by the comparison circuit 3-20, and when (Xb)<(Xa) (after reaching the insertion position), the process moves to step Cc in FIG.

When step 8-14 is YES, or 8-
If 13 is YES, step 8-15, 8
-16, it is checked whether there is a need to add a line break to the read address.

That is, it is determined whether the information (Xb) of area Xb has the relationship Xb≧0, and if (Xb)≧0, then (Nb) − 1 is stored in Nb in order to break the address. , 999 is stored in Xb.

After completing steps 8-15 and 8-16, the information read from area Xe is decremented and rewritten in step 8-17 in order to move the address to which the read information is written by one.
Store in Xe.

Next, in steps 8-18 and 8-19 (Xe)
It is determined whether or not it is necessary to add a line break to the address (Ne), but this step is performed in steps 8-15 and 8
Since it is the same as -16, the explanation will be omitted.

In this way, step 8-18 or 8-
When step 19 is completed, the process returns to step 8-11, and this loop is repeated until step 8-14 becomes NO.

FIG. 8C is a flowchart showing an outline of a program for transferring insertion information from memory 3-9 to memory 3-7. This is included in the flowchart.

That is, as mentioned above, the starting point address of the insertion information in the memory 3-9 is inserted into the RAM areas Xc, Nc as information (Xc) (Nc), and the ending point address is inserted into the RAM areas Xd, Nd as information (Xd). ) (Nd), and the insertion location of memory 3-7 is (Xa)
(Na), the information in the address shown by (Xc) (Nc) is transferred to the address shown by (Xa) (Na), and the information in the address shown by (Xc) + 1, (Nc) + 1, Information can be transferred from memory 3-9 to memory 3-7 by sequentially continuing transfer operations such as transferring information to addresses indicated by (Xa)+1 and (Na)+1. .

That is, in step 8-20, the information indicated by the address (Xc) (Nc) of the memory 3-9 is transferred to the memory 3-7.
Transfer to address (Xa) (Na).

Next, in steps 8-21 to 8+23, the information write address of the memory 3-7 is incremented by one. That is, in step 8-21, (Xa) is incremented and stored in Xa, and in step 8-22, it is checked whether or not (Xa) exceeds the maximum value of the X coordinate. The address is changed to the new line address in step 8-23. If the N coordinate exceeds 8 as a result of line break in this way,
Since there is no storage area in the memory 3-7 to be transferred, the transfer is ended ("END") at this point.

If an area for transfer remains in the memory, the read address of the memory 3-9 is incremented by 1 in steps 8-25 to 8-27. These steps are substantially similar to steps 8-21 to 8-23. In this way, a new read address is
Once stored in Xc and Nc, it is checked in steps 8-28 and 8-29 whether this new address matches the end address (Xd) (Nd), and if they match, the transfer ends ( “END”).

If they do not match, the process returns to step 8-20 and repeats the cycle.

After completing the editing work in this way, if you press the switch 3-16 on the operation section 3-6,
A paper sheet having the contents of the memory 3-7 printed thereon can be obtained from the printer 3-15.

In FIG. 8, the programs indicated by A to C have been described as insertion programs, but it is also possible to use a portion of them to perform independent operations.

For example, by using only the program shown in Figure 8C, address (Xc) of memory 3-9 can be
(Nc) to (Xd) (Nd) information to memory 3-7
It can be transferred to addresses (Xa) (Na) and later.

Further, in the above embodiment, an example in which information in the memory 3-7 is deleted is illustrated, but information in the memory 3-9 can be similarly deleted.

Also, in the above implementation, only the case where the information in the memory 3-9 is inserted into the memory 3-7 is described, but similarly, the information in the memory 3-7 is inserted into the memory 3-7.
Of course, it can be inserted into -9.

Therefore, the two areas M and N in memory 3-7
If you want to exchange the location of information in areas M and N
After transferring the information to the memory 3-9, the information on M and N in the area memory 3-9 can be deleted, and then the information on areas N and M can be transferred from the memory 3-9 to 3-7. It is something.

In the above embodiment, manuscript paper is used that is divided only horizontally by ruled lines, but because of this, when inserting or deleting, etc., characters may be cut off and separated into the end of a line and the beginning of the next line. In order to correct this, it is necessary to make adjustments by inserting blanks again. As shown in the manuscript diagram in Figure 9, the manuscript is divided into image unit blocks by adding vertical lines as well (in Figure 9, there are 8 unit blocks vertically and 10 horizontally, for a total of 80 unit blocks). Deletion and insertion correction can be performed based on each unit block, and in this case, characters are not divided, and processing operations such as editing become extremely easy.

With this configuration, the Q coordinate corresponding to the frame as shown in FIG. 9 can be used instead of the X coordinate, and all addresses can be specified using N and Q.

As described above, the present invention can realize a processing device that can perform various types of processing by blocking image information.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a reading device, FIG. 2 is a front view showing a document, FIG. 3 is a block diagram showing an embodiment of a processing device according to the present invention, and FIGS. A schematic diagram showing the memory shown in the figure, FIG. 5 is a front view showing the mask on the display,
FIG. 7 is a flowchart showing the operation of the embodiment according to the present invention when deleting a part of information;
The figure is a flowchart showing the operation of one embodiment of the present invention when inserting information, and FIG. 9 is a front view showing a mask on the display. Here, 1-1 is the original, 3-1 is the reading device, 3
-2 is the control device, 3-3 is RAM, 3-4 is
ROM, 3-5 is a processing device, 3-6 is an operation unit,
3-7, 3-9 are memories, 3-11 is a display,
3-14 is a light pen.

Claims (1)

[Scope of Claims] 1. In an image information processing device that processes image information using a processing device, a storage means for storing image information consisting of a plurality of pixel signals, and generating a signal instructing editing processing related to the image information. an instruction signal generation means for extracting the pixel signals stored in the storage means in units of blocks based on the signal from the instruction signal generation means, and repeatedly moving the blocks in the storage means via the processing device; An image information processing device comprising: a pixel signal processing means having a step; and an output means for outputting edited image information by outputting a pixel signal processed by the pixel signal processing means. . 2. The image information processing device according to item 1, wherein the pixel signal processing means takes out the pixel signal from the storage means and returns it to another area within the storage means.