JPS6126086A - Display magnification conversion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a pattern memory (image memory) that stores dot patterns displayed on a cathode ray tube display device (hereinafter abbreviated as CRT) at address positions corresponding to the arrangement on the display surface. ), and more specifically, it relates to image memory processing when enlarging or reducing a dot pattern in a display direction.

[Prior art]

FIG. 1 is a block diagram showing a conventional method for displaying reduced images on a CRT. In the figure, (1) is an image memory (referred to as a first image memory).

In order to simplify the explanation below, the CRT displays black and white, and a 1-bit memory is provided corresponding to one pixel (one dot) on the display surface, and the logic rlJ, r
Assume that pixels corresponding to OJ are displayed in "black" and "white". In addition, the image memory (1) is located in the horizontal direction (hereinafter referred to as
Suppose that M x n bits are arranged in the vertical force direction (hereinafter referred to as the Y direction) and N x n bits are arranged in the vertical force direction (hereinafter referred to as the Y direction).

N and n are each integers. Also, the shaded part within the frame of image memory (1) in Figure 1 is logic "4."
, and the other bits are cooking "0" bits,
This image memory 11) is read out as is and transferred to the CRT.
When K is displayed, similar characters are displayed in the diagonally shaded area within the frame of image memory (1). The circuit shown in Figure 1 is CR
This is a circuit for creating an image memory reduced to 1/n in order to display the image reduced to 17n on T.

(la), (lc) are X direction address registers, (lb
, ), (ld) Y-direction address register, 12) is the processing circuit, (31 is the image memo IJ when reduced to 1/n (n-4 in the example shown), (3a) is the X-direction address register, (3b) is the Y direction address register, (41 is the controller, (5: is the acquisition address counter,
(6) is a read address counter. Further, W indicates a write control signal.

Assume that each image memory mountain is composed of n×n memory blocks arranged in M blocks in the X direction and N blocks in the Y direction, and l(0°1.2...i
,...M-1)'iX direction block address, j(0
, 1, 2, . . . J, . . . N-1) are the Y-direction block addresses. Since one block of the image memory mountain corresponds to one hit of image memory (3), (i, j
) is the address for accessing the F9th bit of image memory (31).

Therefore, when the address counter (5) outputs the address (i, j)k, this is given to the image memory fall as a block address, and the (i, j) block in the image memory (1) is selected. 9
Since there is n n x n bit memory in one block, if n = 4, the read address counter is (00, C11, 02, 03, 10, 11, 12
,13,20,21゜22 ,23 ,30 ,31
, 32, 33) are sequentially output, and 16 (generally n×n) data in the (i, j) block are read out and temporarily stored in the processing circuit (2). be done. For example, if 8 or more dots out of 16 bits in one block are logic "1", logic "1" is output to the processing circuits i, ;I, and logic "0" is output otherwise. At the time when the output from the processing circuit (2) is inputted to the image memory (31), the controller (41 is a write control signal W).
The output of the processing circuit (21) is sent to the image memory (3).
) is written to the address (i, j) position, and when this writing is completed, the convolution address counter (5) becomes the address (i+1).
．． j) Output k and image memo January 1) (i+L,
The majority logic of the 16 bits of the image memory (+) block is written to the image memory (31 addresses (i + L J)).
1) to μ x 1/4 (generally ld 1/n x 1/n
) is created as an image memory (3) reduced in size.

When the image memo IJ [31 is read out and displayed on a CRT table, an image display scaled to % x rabbit is obtained.

Since the conventional device operates as described above, it is necessary to extract 1xl bits from the image memory (in order to write one bit of 31), and the read nxl bits must be removed. For n hits, for example, majority decision processing is not required, so there is a drawback that a lot of processing time is required.

[Invention Shelf 1 Required] This invention was made to eliminate the drawbacks of the conventional products as described above.
An image memory having a storage capacity r of 1.2 mm is assumed to be an array of M columns and N rows of rectangular memory blocks of n×n blocks, and each block is assigned a block address (i, j)'il''. Intra-block address (0, 1 in the X direction)
, -n -1, the Y direction is 0°1, . . . n-1, and when n=4, (00)', (01).

(02), (03), (10), (it), (12),
(13), (20), (21), (22).

(23)', (30), (3] ), (32), (33
), and the bits of the same block address in each block are arranged in order of block address to form n×n groups of image memories, and the data of the original image memory is converted into images of n×n groups. Distributed in memory! ! By providing an image memory of 12 times, the time required for displaying a reduced image can be reduced by -2.

[Embodiments of the invention]

Embodiments of this invention will be described below.

2 and 2'31 are diagrams showing a method of configuring an image memory according to the present invention.
The block address (ir
j) r (ill, j) t (ir r il
l).

(ir1.J+1), the curve A indicated by the dotted line in the figure represents the upper left part of the characters shown in Figure 1 (1), and the curve A shown in Figure 2 (with diagonal lines at) The small rectangles represent bits that store logic "1", and the hollow squares represent bits that store logic "0".

FIG. 2(b) is a diagram showing the intra-block address of one block composed of 4×4 bits. If this block is a block with block address (i, j), then the intra-block address (0, U ), the bits (0, 1) are logic "0" and all other bits are logic "1", as shown in Figure 3.2 (a).

The image memory of FIG. 1 (1), a part of which is shown in Section 2 1 (a), is distributed in the manner shown in FIG. 3 to form memory groups n Create n items. That is, in Figure 3, (0,
0), (0,1), (0,2),...(1,0)
.

The rectangles indicated by (1, 1), (1, 2), etc. each indicate the group address of the memory group, and each group has MXN bits of memory, and the group address (' l J ) (' -Or 1 + l +
...Pi, ...M-1; j=0.1, 2. ...J,
...The bit at position N-1 is the logic of the corresponding bit of the original block address (Fig. 2 (bl)) of the 4 x 4 bits of the original block address (i, j). The intra-group address position (i,
j). For example, in Figure 2 (al's block address (i + j) + (ill, j)
Corresponding to the group address (0,0), (,0,
1) , (0,2) ,...(1,0) ,
The bit of address (1+, r) + (ir1.j) in the group of (1,1), (1,2)... is roll.

r 01 J, r 11 J...r 11 j
, r 11 J , r 11 J... can be seen from FIG. 2(a).

When the above-described distributed arrangement is performed, the first image memory shown in FIG. 1 (the contents of 11 is the image memory Uoo shown in FIG. 4) (referred to as the image memory -A-2), Fig. 4 is a block diagram showing an embodiment of the present invention, in which the IHJ- symbols in Fig. 1 indicate the same or corresponding parts, (100) is an image memory used in this invention;
100a) is an address register in the group in the X direction, (
]00b) U In-group address register in the Y direction, (HJOC) is the group address register in the X direction,
(]00d) indicates the group address register in the Y direction, (7) is the control circuit, and j81 is the address conversion circuit. To write data in a specific block therein, address conversion circuit (8) to group address register (100c), (100
d) It is clear from the method of creating the image memory (100) shown in FIGS. The address signal (i, , +) which is the output of the address conversion circuit (8)
The intra-group address register (HlOa), (
100b) The data read from the image memory (100) by applying V is transferred to the address (i) of the image memory (31).
, j) Just put it in the position.

Further, it is also easy to create a pattern memory in which the data of the counting group of the image memo IJ (100) is redistributed (]) and expanded in the image memory (3).

Figure 5 is a diagram showing the rearrangement of the image memory in the case of enlarged display, in which the memory contents of 4 adjacent groups of image memo IJ (1,00) are rearranged in % increments at the upper right. The image memory (200) stores the expanded pattern.
0) group addresses (1,1), (1,2).

The shaded portions of the four groups (2, 1) and (2, 2) are read out and rearranged in the image memory (200).

In this case, for the output (i, j) of the write address register (5) for the image memo IJ (200), if i is an odd number, it is set to (100c), and if i is an even number, it is set to (100c).
00c), and if J is an odd number, set 2i to (10
0d) is set to 1, and if J is an even number, the row (1ooa)
Set 2 to switch each group, (100a
) is (M+ i )/2, (100b) is j/2
The address conversion circuit 81 may perform address conversion so as to supply the following.

That is, in any case, in order to write to the MXN-bit image memory, it is sufficient to read only the MXN bits, so it is not necessary to read the MnxNn bits as in the case shown in FIG. 1, which shortens the processing time. I can do it.

Furthermore, in the case of Fig. 1, the writing speed to the image memory (3) is different from the reading speed of the image memory (1), so it is necessary to display the image on the CRT using the entire image memory (3). , FIG. 4, and FIG. 5, the reading speed of the image memory (100) and the image memo IJ! 3
1, the convolution speed to (200) is the same, so
Data read from the image memory (100) can be displayed on the CRT as is.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to shorten the time required for PgT to convert the display magnification on a CRT, and the operator's waiting time is shortened, thereby improving work efficiency. , FIG.
The figure is a block diagram showing one embodiment of the present invention, and FIG. 5 is an explanatory diagram showing rearrangement of the image memory in the case of enlarged display.

(1)...first image memory, (ioo)...
Second Ij-Silmo IJ, f31, (200
)... Display image memory, (51... Write address counter, (7)... Control device, (81... Address conversion circuit.

In addition, the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a display magnification conversion method for converting the display magnification of an image displayed on a cathode ray tube display device, information corresponding to each pixel of an image displayed at the maximum magnification on the cathode ray tube display device is a display magnification of the image displayed on the cathode ray tube display device. When the number of memory elements in the first image memory stored in the address positions corresponding to the display positions on the screen is Mn in the X direction and Nn in the Y direction (where M, N, and n are respectively An array of n memory elements in the X direction and n memory elements in the Y direction is considered to be one block, and the first image memory is regarded as an array of M blocks in the X direction and N blocks in the Y direction. An intra-block address is determined for the memory element within the block, a block address is determined for the arrangement of blocks, and for each block address, the memory contents of one memory element with the same intra-block address are collected and arranged in the order of the block address. By arranging M pieces in the X direction, Y
creating a second image memory in which groups of N memory elements are arranged in n×n groups in the order of addresses within the block; storage contents of one group of the second image memory; is read out and displayed on the cathode ray tube display device, or the second
A plurality of consecutive groups of image memories in the
A display magnification conversion method comprising the step of alternately reading out k groups in a direction and displaying them on the cathode ray tube display device.