JPS61258534A - Digital signal demodulator - Google Patents

Abstract

PURPOSE:To bring the titled demodulator quickly to a locking state in a short time with a signal reproduced after a non-signal period elapses by using each error signal so as to control the error signal of a phase comparison circuit in a phase locked loop and making selectively any signal or both signals effective. CONSTITUTION:A detection window pulse PW generated by a detection window pulse generating circuit DWC is given to the phase locked loop PLL having a phase comparison circuit PC and a voltage controlled oscillator VCO as a comparison wave. The 1st frequency comparison circuit FCCa and the 2nd frequency comparison circuit FCCb measure a specific pulse period in pulses generated by the 1st and 2nd pulse sources SSGa, SSGb by using a bit clock signal Pc as the measuring reference pulse. The relation of T1>T2 exists in the periods T1, T2, and an error signal generating circuit ESG generates the 1st error signal by using the 1st signal Ssa and the 3rd signal Ssb and generates the 2nd error signal by using the 2nd signal Ssa and the 4th signal SIb. The error signals are fed to the phase comparison circuit in the phase locked loop PLL and used to control the frequency of the bit clock signal Pc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a method for converting a digital signal modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal into a demodulated signal. The present invention relates to a digital signal demodulation device, and particularly to a digital signal demodulation device that can perform demodulation operations smoothly even in the case of intermittent signals on the time axis.

(Prior Art) It is well known that when recording and transmitting digital signals, the digital signals are modulated by a modulation method selected from among various modulation methods.

A bit clock signal is required when demodulating the demodulated signal, but depending on the modulation method, the phase information of the bit clock may only be included in the demodulated signal intermittently.

By the way, when generating the bit clock signal required for demodulation from the demodulated signal of a digital signal that only intermittently contains the phase information of the bit clock signal as described above, the phase-locked - The fact that a bit clock signal cannot be obtained by using a loop can be easily understood from the fact that the phase information of the bit clock signal is only intermittently present in the demodulated signal.

Therefore, conventionally, for example, in a compact disc playback device, in order to obtain a bit clock signal for demodulating an EFM signal, 2lT during the pulse of the longest period of the EFM signal and 3T during the pulse of the shortest period of the EFM signal are used.
is measured using a bit clock signal oscillated by a voltage controlled oscillator, and the oscillation frequency of the voltage controlled oscillator is automatically controlled according to the measurement result to automatically change the period of the bit clock signal. However, in this existing proposal, pulses ri2l1. I was trying to measure T and the pulse width of 3 pulses with the shortest period, so (,)
There was a problem that the formation was 41 G'&.

In order to resolve the above-mentioned problems, the applicant company previously proposed in Japanese Patent Application No. 59-62849 a modulation method consisting of a periodic signal that intermittently contains phase information of a bit clock signal. A modulated digital signal is used as a demodulated signal, and the time position of either the rising edge or the falling edge of the waveform in the demodulated signal, or both time positions, is set in advance to be shorter than the period of the bit clock signal described above. means for generating a detection window pulse having a predetermined pulse width; and means for applying the detection window pulse as a comparison wave to a phase-locked loop comprising a phase comparator circuit and a voltage controlled oscillator; One of the two pulses, the bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop and the pulse generated by a separately provided pulse source, is used as a reference pulse for measurement. When the period of the other pulse of both of the pulses described above is counted using the reference pulse described above, and the measured value is N, then the period of the other pulse of both of the pulses described above is means for generating a first signal when a measured value N when counting the period of the other pulse is equal to or less than a minimum value N1 determined in correspondence with an allowable change range of the oscillation frequency in the voltage controlled oscillator; With the reference pulse for measurement mentioned above,
If the measured value N when counting the period of the other pulse of both of the above-mentioned pulses is equal to or greater than the maximum value N2 determined corresponding to the permissible change range of the oscillation frequency in the voltage controlled oscillator, the second means for generating an error signal using the first signal and second signal; and means for generating an error signal using the first signal and second signal;
We have proposed a bit clock signal generator for a digital signal demodulator comprising means for controlling the error signal of a phase comparison circuit in a locked loop, and have achieved some results by implementing it.

(Problem to be Solved by the Invention) However, in the previously proposed digital demodulator described above, when the signal to be demodulated has a relatively long no-signal period, the time axis is If the phase-locked loop loses lock during a no-signal period in the case of a signal that is intermittent above, a signal that reappears after the said no-signal period causes the phase-locked loop to become locked. The problem was that it took a long time for this to occur, which could cause disturbances in the demodulated signal.

Figure 2 shows an example of signal arrangement on the time axis that may cause the above-mentioned problem. For example, as shown in the third figure, an example of a signal generated by two magnetic heads Ha and Hb provided at 180-degree symmetrical positions (positions with a central angle of 180 degrees) around the rotating cylinder RD. , 90 to the rotary cylinder RD.
Wrapping angle in degrees (r in Figure 2 indicates the radius at the boundary position of the range where the periphery of the rotating cylinder RD and the magnetic tape plate are in contact, and O indicates the center of the rotating cylinder RD) This figure shows the signals obtained when the signals recorded on the magnetic tape wound on the magnetic tape are reproduced from the magnetic tape by the two magnetic heads Ha and Wb described above.

Now, as mentioned above, the winding angle of the magnetic tape version with the winding number around the rotary cylinder RD is smaller than the center angle of the two magnetic heads Ha, l (b) attached around the rotary cylinder RD. When the length of the sliding contact area between the magnetic head and the magnetic tape plate is shortened, (a) the wear of the magnetic head is reduced, and (b) the friction between the magnetic tape plate and the rotating cylinder surface is reduced. This has the advantage of making it easier to run the magnetic tape at high speed and perform cueing by reproducing information signals at high speed. The diameter can be made smaller,
Many advantages can be obtained, such as being able to shorten the length of the rotating cylinder in the generatrix direction and simplifying the magnetic tape loading mechanism. magnetic heads Ha, l
When the winding angle of the magnetic tape MT wound around the rotating cylinder RD is smaller than the central angle of lb, the signal reproduced from the magnetic tape MT will naturally be interrupted on the time axis. Since the signal is in a state where signal periods and no-signal periods are arranged alternately on a time glaze, it is difficult to supply such a signal to the already proposed digital signal demodulator. , during the no-signal period, the phase
When the locked loop loses lock, it takes a long time for the phase-locked loop to be brought into lock by a signal that reappears after the aforementioned no-signal period has elapsed, thereby causing disturbances in the demodulated signal. , this problem may occur.

(Means for Solving the Problems) The present invention provides for demodulating a digital signal that has been modulated according to a modulation method such as a signal that intermittently includes phase information of a P1-clock signal. Detection of a signal having a predetermined pulse width shorter than the pulse 2l of the bit clock signal described above from one or both of the time positions of the rising edge and the falling edge of the waveform in the demodulated signal. means for generating a window pulse;
means for applying the detection window pulse as a comparison wave to a phase-locked loop configured to include a phase comparison circuit and a voltage controlled oscillator; and a first pulse source that generates a first pulse having a period of T1. and the period T2 is the first
a second pulse source that generates a second pulse with a relationship of T2<TI with respect to the period T1 of the first pulse generated by the pulse source; and voltage control in the phase-locked loop described above. a first measuring means for measuring the period T1 of the first pulse generated by the first pulse source, using the bit clock signal obtained from the oscillator as a reference pulse for measurement; a second measuring means for measuring a period T2 of a second pulse generated by the second pulse source, using a bit clock signal obtained from a voltage controlled oscillator in the loop as a reference pulse for measurement; When the period T1 of the first pulse generated by the first pulse source is counted using the reference pulse described above and the measured value is N1, the measured value N1 is the first oscillation frequency in the voltage controlled oscillator. A first signal is generated when the measured value N1 is equal to or less than a minimum value Nls determined corresponding to the permissible change range of the oscillation frequency, and the first signal is generated when the measured value N1 corresponds to the first permissible change range of the oscillation frequency. Means for generating a second signal when the predetermined maximum value N1l or more, and measurement when counting the period T2 of the second pulse generated by the second pulse source with the reference pulse described above. When the value is N2, the oscillation frequency is set to have a larger frequency change rate than the frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. A third signal is generated when the measured value N2 is smaller than the minimum value N2s determined by Jt corresponding to the second allowable change range, and the measured value N2 is the oscillation frequency in the voltage controlled oscillator. means for generating a fourth signal when the maximum value N2l is greater than or equal to a second allowable variation range of the second permissible change range; means for obtaining an error signal; and means for obtaining a second error signal using the second signal and the fourth signal;
A digital signal demodulator comprising a bit clock signal generator comprising means for controlling the error signal of the phase comparison circuit in the phase-locked loop according to each of the error signals, and phase information of the bit clock signal. The demodulated signal is a digital signal that is modulated according to a modulation method that consists of a signal that intermittently contains From the time position of
The detection window pulse includes means for generating a detection window pulse having a predetermined pulse width shorter than the pulse width of the bit clock signal, a phase comparison circuit for generating the detection window pulse, and a voltage controlled oscillator. phase locked
A means for providing a comparison wave to the loop and a first wave whose period is TI.
a first pulse source that generates a pulse, and a period T2 of the first pulse generated by the first pulse source described above;
1, a second pulse source that generates a second pulse with a relationship of T2 < T1 and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above are used as a reference for measurement. A first measuring means for measuring the period T1 of the first pulse generated by the first pulse source described above as a pulse, and a P1-clock obtained from the voltage controlled oscillator in the phase-locked loop described above. a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source, using the signal as a reference pulse for measurement; When the measured value when the period TI of one pulse is counted using the above-mentioned reference pulse is set as N1, the measured value N
1 is less than or equal to the minimum value Nls determined in correspondence with the first permissible variation range of the oscillation frequency in the voltage controlled oscillator, the first signal is generated, and the measured value N1 is
means for generating a second signal when the oscillation frequency is equal to or greater than a maximum value N1l determined corresponding to the first permissible variation range of the oscillation frequency; and a second signal generated by the second pulse source described above; When the measured value when counting the period T2 of the pulse with the reference pulse described above is N2, compared to the frequency change rate in the first allowable change range described above set for the oscillation frequency of the voltage controlled oscillator. The minimum value N2s is determined in correspondence with the second allowable change range of the oscillation frequency, which is set to have a large frequency change rate.
A third signal is generated when the measured value N2 is smaller than , and the 61-degree value N2 is a maximum value determined corresponding to a second allowable change range of the oscillation frequency in the voltage controlled oscillator. means for generating a fourth signal when N2l or more; means for obtaining a first error signal from the first signal and third signal; and means for generating the first error signal from the second signal and the fourth signal. means for controlling the error signal of the phase comparison circuit in the phase-locked loop according to each of the above-mentioned error signals; The present invention provides a digital signal demodulation device comprising a bit clock signal generation device comprising means for selectively invalidating one or both of the signals.

(Example) Hereinafter, the specific contents of the digital signal demodulation device of the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram for explaining the configuration principle and operating principle of the digital signal demodulation device of the present invention. In FIG. This is an input terminal for a demodulated signal that is a digital signal that is modulated according to a modulation method such as a signal that intermittently includes phase information of a clock signal, and the demodulated signal that is supplied to the input terminal 1 is It is applied to the detection window pulse generation circuit DIIIC.

In the following description, a demodulated signal is a digital signal modulated according to a modulation method such as a periodic signal that intermittently includes phase information of a bit clock signal.
It is said that the demodulated signal is a digital signal that is modulated according to a modulation method that is constituted by a signal having a pulse width that is an integral multiple of a predetermined range of the pulse IJ of the bit clock signal.

In the above-described detection window pulse generation circuit DWC, from the time position of either the rising edge or the falling edge of the waveform of the demodulated signal input thereto, or from the time position of both,
A detection window pulse P having a predetermined pulse duration Tw shorter than the pulse duration T of the bit clock signal Pc described above.
In the embodiment described later in which W is generated, the detection window pulse Pw described above is one of the pulses of the bit clock signal Pc.
/2 pulse) is generated by the above-mentioned detection window pulse generation circuit DWC, and the ft detection window pulse PW is generated by the phase comparator circuit pc and the voltage controlled oscillator vC.
It is applied as a comparison wave to a phase-locked loop PLL configured to include O.

FCC is a frequency comparison circuit FCC, and this frequency comparison circuit FCC is composed of a first frequency comparison circuit FCCa and a second frequency port circuit FCCb. The frequency comparison circuit FCCb is supplied with the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop PLL described above.

The first frequency comparison circuit FCCa and the second frequency comparison circuit FCCb in the frequency comparison circuit FCC use the bit clock signal Pc obtained from the voltage controlled oscillator vCO in the phase-locked loop PLL.
As a reference pulse for measurement, a separately provided first pulse is used. Second
The period of a specific one of the pulses generated by the pulse sources 5SGa and 5SGb is measured.

That is, in the first frequency comparison circuit FCCa,
The first pulse source 5SGa uses the bit clock signal Pc obtained from the voltage controlled oscillator vCO in the phase-locked loop PLL as a reference pulse for measurement.
The second frequency comparator circuit FCCb uses the bit clock signal Pc obtained from the voltage controlled oscillator VCO in the phase-locked loop PLL for measurement. As a reference pulse, the period T2 of the pulse generated by the second pulse source 5SGb is measured. Then, the period T of the pulse Jl generated by the first pulse source 5SGa described above is
1 and the period T2 of the pulses generated by the second pulse source 5SGb described above are T], )T2 as shown in FIGS. 4(a) and (b). I'm here.

In the first frequency comparison circuit FCCa, the voltage controlled oscillator v in the phase-locked loop PLL is
outputting a first signal S1s a when the frequency of the bit clock signal Pc outputted from the CO becomes lower than its first allowed frequency change - 20 = the lowest frequency value in the range; The above mentioned phases
When the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the locked loop PLL becomes higher than the highest frequency value in its first allowed frequency variation range, the second signal It is designed to output SΩa.

Further, the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop PLL is within the first allowed frequency change range set for the oscillation frequency of the voltage controlled oscillator. Output the third signal Ssb when the oscillation frequency, which is set to have a larger frequency change rate than the frequency change rate in the second permissible frequency change range, becomes lower than the lowest frequency value in the second allowable frequency change range. Furthermore, the frequency of the bit clock signal Pc output from the voltage controlled oscillation 1vco in the phase-locked loop PLI described above is higher than the highest frequency value in the second allowed frequency variation range described above. When the signal becomes high, a fourth signal SQb is output.

A first signal Ssa and a second signal SΩa output from the first frequency comparison circuit FCCa, and a third signal Ssb output from the second frequency comparison circuit FCCb.
, the fourth signal sub means that in the error signal generation circuit ESC, the first error signal is generated by the above-described first signal Ssa and the third signal Ssb, and the second signal 5fla and the fourth signal A second error signal is generated by the signal SQb, and the error signal is supplied to a phase comparison circuit in the phase-locked loop PLL and used to control the frequency of the bit clock signal Pc.

As described above, in the digital signal demodulation device of the present invention, the frequency comparison circuit FCC includes the first frequency comparison circuit FCC.
In the first frequency comparison circuit FCCa, the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop PI is used as a reference for measurement. As a pulse, the period T1 of the pulse generated from the first pulse gSSGa is measured, and the second frequency comparison circuit F
CCb is output from the voltage controlled oscillator vCO in the phase-locked loop PLL.

The period T2 of the pulse generated from the second pulse source 5SGb is measured using the input bit clock signal Pc as a reference pulse for measurement, and the period T2 of the pulse generated from the second pulse source 5SGb is measured.
By I, T2, the phase-locked loop PLL
A signal is output when the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the voltage control oscillator vCO is out of the respective allowable frequency range, and an error signal is generated by the signal, thereby forming a phase-locked loop. The period of the bit clock signal Pc output from the voltage controlled oscillator vCO in the PLL is controlled, and the first pulse source 5SGa whose frequency is compared in the first frequency comparison circuit FCCa described above is
The period T1 of the pulses generated by the second pulse source 5SGa and the period T2 of the pulses generated by the second pulse source 5SGa are
As shown in (a) and (b) of the figure, Tl )T
2, and the phase-locked loop P set in the first frequency comparison circuit FCCa
The oscillation frequency of the voltage-controlled oscillator vCO in the phase-locked loop PLL set by the frequency comparator circuit FCCb in (ii) For example, if the rate of change in frequency within the allowable range of change is greater, the input signal being supplied to the phase-locked loop circle 4L may be interrupted, causing the phase-locked loop PLL to lock from the locked state. The voltage controlled oscillator vCO is not in the state
Even if the frequency of the P1 to clock signal Pc output from the phase-locked loop P1
□L can be locked in a short time.

This point will be explained with reference to FIG. 4 as follows. That is, (a) in FIG. 4 shows the first frequency comparator circuit F.
The output pulse of a is shown in the first pulse source SS, which is the target of frequency comparison in CCa, and (b) in FIG. 4 is the target of frequency comparison in the second frequency comparison circuit FCCb. Second pulse g S S G
(b) shows the output pulse of FIG.
The above-mentioned 1. Second frequency comparison circuit FCCa, F
A reference pulse (P1-clock signal Pc obtained as an output pulse from the voltage-controlled oscillator vCO in the phase-locked loop PLL) used to measure the period of the output pulse from CCb is shown.

The period T1 of the output pulse of the first pulse source 5SGa, which is the target of frequency comparison in the first frequency comparison circuit FCCa, and the second pulse source 5scb, which is the target of frequency comparison in the second frequency comparison circuit FCCb. As is clear from <a) and (b) in FIG. 4, the period T2 of the output pulse of
a first permissible change range α of the frequency of the PIT 1 to TARLOCK signal Pc output from the voltage controlled oscillator vCO of the phase-locked loop PLL, which is set in connection with the frequency comparison operation in the frequency comparison circuit FCCa; Phase-locked loop P L L set in connection with the frequency comparison operation in the second out-of-frequency range gFCcb
The second permissible variation range β of the frequency of the P1-clock signal Pc output from the voltage controlled oscillator VCO in the phase-locked loop PLI is defined as The rate of change in frequency in the second permissible change range β of the oscillation frequency of the voltage-controlled oscillator vCO in the phase-locked loop circle L is higher than the rate of change in the frequency in the second permissible change range α in the phase-locked loop circle L. It is set to be large.

So, Phase Locked Loop PI! If the oscillation frequency of the voltage controlled oscillator VCO in , deviates significantly, the second pulse source 5S used for frequency comparison
The output signal from the second frequency comparator circuit FCCb, which is generated by frequency comparison using the short period T2 output pulse from Gb, and the output signal from the first pulse source 5SGa used for frequency comparison. The phase-locked loop circle is The phase-locked loop PLL can be locked for a short time, and the phase-locked loop PLL is always locked by the error signal generated by the output signal from the first frequency comparator circuit FCCa in response to a slight deviation in frequency. It can be maintained in a state.

Next, various embodiments of the digital signal demodulation device of the present invention will be described. 5 and 6 are block diagrams showing various embodiments of the digital signal demodulation device of the present invention, and in FIGS. 5 and 6, 1 is an input terminal of the demodulated signal, , is an input terminal for a demodulated signal by a digital signal modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal, and the demodulated signal supplied to this input terminal 1. is applied to the detection window pulse generation circuit DWC.

In the above-mentioned detection window pulse generation circuit DIdC, the pulse rllT of the above-mentioned bit clock signal Pc is shorter than the pulse rllT of the bit clock signal Pc from one or both of the time positions of the rising edge and the falling edge of the waveform of the signal input thereto. A detection window pulse Pw having a predetermined pulse il T w is generated. In the following embodiment, the detection window pulse Pw described above is 1/2 of the period of the bit clock signal Pc.
is shown with a pulse width of .

The detection window pulse PW generated by the detection window pulse generation circuit DWC described above is a phase-locked pulse generator composed of a phase comparator circuit pc and a voltage controlled oscillator vCO.
It is applied as a comparison wave to the input terminal 10 of the loop PLL.

In FIG. 5 and FIG. 6, FCC is a frequency comparison circuit F'CC configured with a first frequency comparison circuit FCCa and a second frequency comparison circuit FCCb, and an input terminal of the frequency comparison circuit FCC. 2, the voltage controlled oscillator VC in the phase-locked loop PLL described above.
(A clock signal Pc as shown in FIG. 4(c) outputted from l is supplied to pin 1. In the frequency comparator circuit FCC in FIGS. 5 and 6 described above,
5SGa is a first pulse source, 5SGb is a second pulse source, and the first pulse source 5SGa and the second pulse source 5SGb are configured to include, for example, a crystal oscillator, The pulse source 5SGa outputs a pulse with a constant period T1 and supplies it to the counter CTA, and
The second pulse source 5SGb outputs a pulse with a constant period T2 and supplies it to the counter CTB.

First frequency comparison circuit F in frequency comparison circuit FCC
In CCa, the above-mentioned phase-locked loop PL
(c
) as a reference pulse for measurement, the first pulse source 5 described above
The measured value when the period T1 of the pulse generated by SGa is counted using the reference pulse Pc for measurement described above is N1.
Then, the measurement value N1 obtained by counting the period TI of the pulse generated by the first pulse source 5SGa using the reference pulse Pc for measurement is the first oscillation frequency in the voltage controlled oscillator. The first signal Ssa is generated when the minimum value N]s is less than or equal to the minimum value N]s determined corresponding to the permissible variation range α of When the measured value N1 when counting the period TI of the pulses generated by the pulse source 5SGa of No. 1 is greater than or equal to the maximum value N1l determined in correspondence with the permissible change range α of the oscillation frequency in the voltage controlled oscillator. Then, the second signal SQa is generated.

In the second frequency comparison circuit FCCb in the frequency comparison circuit 1'CC, the above-mentioned phase-locked loop P
'I' obtained from the voltage controlled oscillator vCO in L L
The bit clock signal P as shown in (c) of I
When c is the reference pulse for measurement, and the measurement value when the period T2 of the pulse generated by the second pulse source 5SGb is counted by the reference pulse Pc for measurement is set as N2, The reference pulse P for measurement mentioned above
The H1 measurement value N2 when counting the period T2 of the pulses generated by the second pulse source 5SGb described above in c. The third signal Ssb is generated when the minimum value N2s is equal to or less than the minimum value N2s, and the pulse period T2 generated by the second pulse 2Hsscb is changed to The fourth signal SCb is generated when the measured value gN2 from .

For counter CTA, phase locked loop PL
The pulse source 5SG uses the bit clock signal Pc generated by the voltage controlled oscillator vCO in L as a reference pulse for measurement.
By measuring the period T1 of the pulses generated by the first pulse source 5SGa, the count value N1 obtained in correspondence with the period T1 of the pulses generated by the first pulse source 5SGa is transferred to the first pulse source 5SGa via the latch circuit LCA. It is applied to the numerical comparator COMI and the second numerical comparator C0M2.

In counter CTB, phase locked loop PL
By measuring the period T2 of the pulse generated by the second pulse source 5scb using the bit clock signal Pc generated by the voltage controlled oscillator vCO in L as a reference pulse for measurement, the pulse generated by the pulse source 5SGb described above is measured. The count value N2 obtained in correspondence with the period T2 of the pulse is applied to the third numerical comparator C0M3 and the fourth numerical comparator C0M4 via the latch circuit LCB.

In order to measure the number of bit clock signal pulses Pc given to the counter CTA by using the period Tl of the pulse outputted from the first pulse source 5SGa as the workpiece number pulse, the first pulse source 5SGa is The counter CTA may be cleared at each rising edge of the pulse output from the 5SGa.

As a result, the count value N at the counter 6 A mentioned above
1 corresponds to the cycle of the bit clock signal pulse Pc described above, and the count value N2 in the counter CTB described above also corresponds to the cycle of the clock signal pulse Pc described above. It has become a thing.

The latch circuit ① described above, CA is the counter CTA described above.
The first pulse marked 1'If is given as a clear pulse to ．． It is applied to the second numerical comparator COMI, C0M2.

Further, the latch circuit LCB described above is connected to the counter C described above.
By supplying the rising edge of the pulse output from the second pulse source 5SGb, which is used as a clear pulse to TB, as a latch signal, the count value N2 at that point is Numerical comparator C0M3
．． Give to C0M4.

The first numerical comparator C02l1, which is supplied with the count value Nl of the counter CTA corresponding to the period of the bit clock signal Pc described above, is supplied with a numerical value Nls as a threshold value, and The second numerical comparator C0M2, which is supplied with the count value N1, is supplied with a numerical value N1l as a threshold value.

Further, the third numerical comparator C0M3, which is supplied with the count value N2 of the counter CTB corresponding to the period of the bit clock signal Pc described above, is supplied with the numerical value N2s as a threshold value, and The fourth numerical comparator C0M4, which is supplied with the numerical value N2, is supplied with the numerical value N2l as a threshold value.

The numerical value Nls given as the threshold value is a count value corresponding to the longest period in the first permissible variation range of the period of the clock signal pulse Pc, and the numerical value Nls is a count value corresponding to the maximum period of the period of the clock signal pulse Pc. This is the count value corresponding to the shortest period in the first permissible variation range of the period of the tarok signal pulse Pc.

Further, the numerical value N2s given as the threshold value is a count value corresponding to the longest cycle in the second allowable variation range of the cycle of the bit clock signal pulse Pc, and the numerical value N2s
2l is a count value corresponding to the shortest cycle in the second permissible variation range of the cycle of the P1-clock signal pulse Pc.

Now, the count value N1 in the counter CTA mentioned above is N
l<N1. In the case of s, that is, when the period of the bit clock signal pulse Pc becomes longer than the limit value of the first permissible change range, the first numerical comparator CO from the old system outputs the first signal by a positive pulse. Ssa is output, and the count value N1 of the counter CTA is N1l (if Nl,
That is, when the period of the bit clock signal Pc becomes shorter than the limit value of the first allowable variation range, the second numerical comparator C0M2 outputs the second signal S with a positive pulse.
Qa is output.

Moreover, the count value N2 in the counter CTB mentioned above is
When N2<N2s, that is, when the period of the bit clock signal pulse Pc becomes longer than the limit value of the second allowable variation range, the third numerical comparator C0M3 outputs a third pulse with a positive pulse. On the other hand, when the count value N2 of the counter CTB is N2l < N2, that is, when the period of the bit clock signal Pc becomes shorter than the limit value of the second allowable variation range, the signal Ssb is output. 4
A fourth signal SΩb with a positive pulse is output from the numerical comparator CO.

The first signal Ssa output from the first numerical comparator circuit CON1 is applied to the fixed contact a of the changeover switch SWI, and the fixed contact a of the changeover switch Sυ1 is connected to a low level via a resistor. L is given nine. Therefore, when the movable contact C of the changeover switch SWI is switched to the fixed contact a side, the first numerical comparison circuit C
The first signal Ssa output from 1 to O is connected to the NOR circuit N via the fixed contact a and the movable contact C of the changeover switch SWI.
Oold is supplied as one of its inputs. The other input of the NOR circuit NO is the third numerical comparison circuit C0M provided in the second frequency comparison circuit FCCb.
A third signal Ssb output from 3 is provided.

Further, the second signal 5fla outputted from the second numerical comparison circuit C0M2 is applied to the fixed contact a of the changeover switch SW2, and is also applied to the changeover switch 5li12.
A low level L is applied to the fixed contact of the circuit through a resistor. Therefore, when the movable contact C of the changeover switch SW2 is switched to the fixed contact a side, the second signal SQa output from the second numerical comparison circuit C0M2 is the same as the fixed contact C of the changeover switch SW2 and the movable contact C. is supplied to the OR circuit ORI as one input thereof.

The other input of the OR circuit ORI is supplied with the fourth signal SQb output from the fourth numerical comparison circuit C0M4 provided in the second frequency comparison circuit FCCb.

In the frequency comparison port=36-path FCC shown in FIG. 5, the output signal S from the NOR circuit NO old
1 is sent to the input terminal 5 of the error signal generation circuit ESG via the output terminal 3, and the second signal S2 outputted from the OR circuit ORI is sent to the error signal generation circuit ESC via the output terminal 4. On the other hand, in the frequency comparator circuit FCC indicated by 9 in FIG. Generation circuit ESGI
It is also supplied to the input terminal 5 of the above-mentioned OR circuit OR
, 1 are supplied via an output terminal 4 to an input terminal 6 of a second error signal generating circuit ESC2.

When the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop PLL is normal, the first frequency comparison circuit F described above
The frequency comparison circuit FCC, which includes CCa and the second frequency comparison circuit FCCb, operates as follows. That is, bit 1 to clock signal P output from the voltage controlled oscillator vCO in the phase-locked loop PLI.
If the frequency of c is normal, the first to fourth numerical comparators CO old to C0M in the frequency comparison circuit FCC
The output from 4 is low level, and the NOR circuit NO.
The output from the old is high-resolution / L / Tonari, OR circuit OR
Since the output of 1 becomes low level, the output terminal 3 of the frequency comparator circuit FCC becomes high level, and the output terminal 4 becomes low level.

In this state, the high level first signal sent from the output terminal 3 of the frequency comparison circuit FCC is supplied to the input terminal 5, and the output terminal 4 of the frequency comparison circuit FCC is supplied to the input terminal 5.
In the error signal generating circuit ESC in the embodiment shown in the fifth figure, in which the low-level second signal sent from As a result, a signal at an intermediate level between the high level first signal and the low level second signal supplied to the input terminal is sent to its output terminal 9.

Bit clock signal Pc output from the voltage controlled generator VCO in the phase-locked loop PLL
If the frequency deviates from a predetermined allowable variation range, the first frequency ratio axis ':J'rFCCa in the frequency comparison circuit FCC and the second frequency comparison circuit FCC
b and the first to fourth numerical comparators COMI to C0M
The level state of the output signal from 4 changes as will be described later depending on the frequency shift of the bit clock signal Pc. The first . The second signal is connected to resistors 100, 101 . , 7.8, the level of the signal output to the output terminal 9 via the analog adder circuit of the resistor network consisting of the bit clock signal Pc depends on the frequency deviation of the bit clock signal Pc. The signal level is different from the signal level when the frequency is normal.

Now, in the above-mentioned error signal generation circuit ESC shown in FIG. As mentioned above, the second signal s2 is connected to the resistor 10.
0, 101, and 7.8 by an analog adder circuit of a resistor network, and outputs an error signal Se from an output terminal 9 to a phase comparator circuit P in a phase-locked loop PLL.
It is supplied to input terminal 12 of C.

The error signal Se generated by the error signal generation circuit ESC described above is connected to the phase locked loop P described above.
A bit clock signal Pc generated from a voltage controlled oscillator vCO in a phase-locked loop PLL is supplied to the input terminal 12 of the phase comparator circuit pc in LI,
The frequency of . When the frequency is out of the second allowed frequency change range, the phase comparator circuit PC in the phase-locked loop PLL has its input terminal 1.
2, the error signal in the phase comparison circuit PC is controlled by the error signal Se supplied to the phase comparator circuit PC, and the phase-locked loop PLL is quickly brought into a state of phase synchronization.

That is, when the frequency of the bit clock signal Pc is normal, the first signal applied from the frequency comparison circuit FCC to the input terminal 5 of the error signal generation circuit ESG is at a high level, and the frequency comparison circuit FCC from the second input terminal 6 of the error signal generation circuit ESG.
Since the signal P is at low level, the bit clock signal P
If the frequency of c is normal, the error signal generation circuit ESC
In this case, no error signal is generated, and in this case, the signal sent to the output terminal 9 of the error signal generation circuit ESC is at a level intermediate between the high level and the low level, as described above.

Therefore, when the frequency of the bit clock signal Pc reaches the normal 6, the error signal generation circuit 1ESG changes to the phase comparison circuit P.
The error signal of the phase comparison circuit pc is not changed by the signal supplied to the input terminal 12 of the phase comparison circuit pc.

Next, the frequency of the bit clock signal Pc becomes higher than in the normal case (the period of P1-clock (i39 Pc becomes shorter than in the normal case), and the above frequency ratio has an error from the circuit FCC. When the second signal applied to the input terminal 6 of the signal generation circuit IESG becomes high level, even in this state, the second signal applied from the frequency comparison circuit FCC to the input terminal 5 of the error signal generation circuit IESG becomes high level. Since the level of the signal 1 is at a high level similar to the level of the signal 1'j when the frequency of the bit clock signal Pc is normal,
When the frequency of c becomes higher than the above-mentioned allowable frequency range, it is sent to the output terminal 9 of the error signal generation circuit ESC (the signal ij becomes a high level signal, and in this case, the error signal generation circuit The phase comparator circuit PC is controlled by the signal supplied from the circuit ESC to the input terminal 12 of the phase comparator circuit PC.
The error signal of P is varied and the phase-locked loop P
The frequency of the bit clock signal Pc generated from the voltage controlled oscillator vCO in L L is rapidly lowered to a frequency within the above-mentioned permissible frequency range.

Then, the frequency of the clock signal Pc becomes lower than that in the normal case (the period of the bit clock signal Pc becomes longer than that in the normal case), and the frequency of the error signal generating circuit ESC is output from the frequency comparison circuit FCC. When the first signal applied to the human input Ω element 5 becomes low level, even in this state, the second signal applied from the frequency comparison circuit FCC to the input terminal 6 of the error signal generation circuit ESC is The level is low, similar to the signal level when the frequency of the bit clock signal Pc described above is normal, so when the frequency of the bit clock signal Pc becomes low beyond the permissible frequency range described above. In this case, the signal sent to the output terminal 9 of the error signal generation circuit ESC becomes a low level signal, and in this case, the phase comparison is performed by the signal supplied from the error signal generation circuit ESC to the input terminal 12 of the phase comparison circuit PC. The error signal of the circuit PC is changed so that the frequency of the bit clock signal Pc generated from the voltage controlled oscillator vCO in the phase-locked loop PLL rapidly becomes a frequency within the above-mentioned permissible frequency range. Ru.

Next, in the first error signal generating circuit ESGi shown in S'J 6 L], the first signal S1 supplied to its input terminal 5 is passed through the inverter INV to the first shifter 1. - The second signal S2 supplied to the register SRI and also supplied to the input terminal 6 of the second error signal generating circuit ESC2 is applied to the second shift register SRI.
given to R2. The first point mentioned above. Each of the second shift 1 registers SRI and SR2 is connected to the frequency comparison circuit FC described above.
The first section provided in C. a second pulse source 5SGA,
The same pulses as those given to counters CTA and CTB and latch circuits LCA and LCB are supplied as clock signals from SSG[3. And the above-mentioned 1. Each of the second shift registers SRI, 52l2 takes in the information given to the data terminal at the time when a clock is supplied to it and shifts it by one step.

The three outputs Q1 to Q3 in the first shift register SRI are given to a NAND circuit NAND, and the three outputs Q1 to Q3 output to the second shift register SRI.
Since the two outputs are given to the AND circuit AND,
The output side of the NAND circuit NAND in the first error signal generation circuit ESGI has a low level only when the three outputs of Q1 to Q3 in the first shift -44 register S old become high level. A signal is output to the output side of the AND circuit AND in the second error signal generating circuit HSG2 only when the three outputs Q1 to Q3 in the second shift register SR2 are all at high level. A high level signal is output.

A resistor 43°44 is connected to the output side of the NAND circuit NAND provided in the first error signal generating circuit ESGI.
Further, one end of each of resistors 45 and 46 is connected to the output side of the second error signal generating circuit ESC2. The high level voltage H in the logic circuit is connected to the other ends of the resistors 43 and 45 described above, and the other ends of the resistors 44 and 46 described above are connected to each other and the output terminal 9 is connected thereto. There is.

Therefore, in the first error signal generation circuit ESGI having the above-described configuration, the first shift register SRI
The first error signal is not generated unless all three outputs of Q1 to Q3 are at high level. Further, in the second error signal generation circuit H5G2 having the above-described configuration, the second shift l-register SR
The second error signal is not generated unless all three outputs of each of Q1 to Q3 in 2 are at a high level.

That is, the first. From the second error signal generation circuits ESGI and 1EsG2, a predetermined period -L (in the illustrated embodiment, it is a period corresponding to three taroks added to shift 1 to registers, but the predetermined period can be set arbitrarily). It goes without saying that the first and second error signals are generated only when the error signals are generated over a period of time (needless to say). Even if a dropout occurs in the demodulated signal, the frequency comparator circuit FCC does not respond to the dropout, and therefore, frequency skipping does not occur.

In the apparatus of the embodiment shown in FIG. 6, if the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop circle 1 is normal, the NOR circuit No. The upper output is at a high level, and the output of the OR circuit on1 is at a low level, and the high level output from the NOR circuit N0RI is given to the first shift 1 to register through the inverter INV. Both the input to SR1 and the input to register SR2 to the second shift 1, to which the low level output from the OR circuit ORI is given, are at low level. The respective outputs of the second shift registers SRI and SR2 are all low level, and the NAND circuit N A N
The output of the AND circuit A N D becomes a high level, and the output of the AND circuit A N D becomes a low level. Second error signal generation circuit E
The output terminal 9 of SGI and ESC2 has a voltage intermediate between high level and low level.

Next, in the device shown in the embodiment of FIG.
When the frequency of the bit clock signal PC output from O becomes lower than the allowable change range (when the period of the bit clock signal Pc becomes longer than the allowable change range), the frequency comparison circuit FCC Noah circuit N0R
The output of I becomes low level, and the output of OR circuit ORI also becomes low level =47-.

Therefore, the first shift 1 register S old to which the low level output from the NOR circuit No is made high through the inverter FV maintains the input signal thereto at the high level for a predetermined period of time. In this state, all three outputs become high level.

On the other hand, in the state we are currently considering, the output from the second shift 1 register SR2 to which the low level output from the OR circuit ORI is given is low level.
All outputs from the shift 1 register SR2 become low level.

Therefore, the output of the NAND circuit NAND and the AND circuit A
Both the outputs of ND become low level, and a low level error signal is sent from the output terminal 9 of the first and second error signal generation circuits ESGI and ESG2 to the input terminal 12 of the phase comparison circuit XPrpc. 1st. The error signal of the phase comparator circuit pc is changed by the signal supplied from the output terminal 9 of the second error signal generation circuit uESG1, H2S2 to the input terminal 12 of the phase comparator circuit pc, and the error signal of the phase comparator circuit pc is changed.
8 = Voltage controlled oscillator vc in one locked loop PLL
The frequency of the pick-clock signal Pc generated from O is rapidly raised to the normal frequency.

Then, in the apparatus shown in the embodiment of FIG.
When the frequency of the bit clock signal Pc output from the voltage controlled oscillator vCO in the phase-locked loop circle 7I becomes higher than the allowable variation range (the period becomes shorter than the allowable variation range), Frequency ratio (receiving circuit FC
The output of the OR circuit ORI at C becomes high level,
Further, in the above state, the output of the NOR circuit N0RI is also at a high level.

Therefore, the output from the second shift register SR2 to which the high level output from the OR circuit OR1 is given is:
When the input signal thereto is held at a high level for a predetermined period, all three outputs become high level.

On the other hand, in the state under consideration, the high level output from the NOR circuit N0RI is made low level through the inverter INV and is applied to the first shift register SRI.
The output becomes low level.

Therefore, the output of the NAND circuit NAND and the AND circuit A
Nr) outputs both become high level, and the first and second outputs become high level.
error signal generation circuit ESGI, ESG2 output ring 9
A high l/bell error signal is sent to the input terminal 12 of the phase comparison circuit PC from the first . The error signal of the phase comparison circuit pc is changed by the signal supplied from the output terminal 9 of the second error signal generation circuit F, SGI, ESG2 to the input terminal 12 of the phase comparison circuit PC, and the phase locked loop t' LL is changed. The frequency of the bit clock signal Pc generated from the internal voltage controlled oscillator vCO is rapidly lowered to the normal frequency.

Now, the period of the pulse of period T1 generated from the first pulse source 5SGa is determined by the counter CTA of the first frequency comparison circuit FCCa in the frequency comparison circuit FCC, and the period of the pulse is determined by the phase-locked loop P1. Count value N1 obtained by counter CTA when measured using bit clock signal Pc output from voltage controlled oscillator vCO in phase-locked loop circle 7I in state fl'M where L is normally locked. is Min, and the numerical value N15 (Pip 1) set in the first numerical comparator COMI is set as Min.
~A numerical value set corresponding to the lower limit frequency in the first permissible change range of the frequency of the clock signal Pc...
- A value set corresponding to the longest period in the first permissible change range of the period of the bit clock signal PC)
and the numerical value N set in the second numerical comparator C0M2
1l (a numerical value set corresponding to the upper limit frequency in the first permissible change range of the frequency of the bit clock signal Pc...the shortest period in the first permissible change range of the period of the bit clock signal Pc) (a numerical value set correspondingly to N1.) is the aforementioned count value N1. ±1% value of n, that is, N15=N1nX0.99, N1ff=N
1nX 1.01, and the second
The period T2 generated from the pulse source 5SGb (however,
The pulse period of TI>T2) is determined by the frequency comparison circuit FCC.
When measured using the clock signal Pc output from the voltage controlled oscillator VCO in the phase-locked loop PLL in a state in which the phase-locked loop PLL is normally locked, the counter CTB of The count value N2 obtained by CTB is N2n
, the numerical value N25 set in the third numerical comparator C0M3 (the numerical value set corresponding to the lower limit frequency in the second allowable change range of the frequency of the bit clock signal Pc...bit clock signal The second period of Pc
(a numerical value set corresponding to the longest cycle in the allowable variation range of bit clock signal Pc) and a numerical value N2l set in the fourth numerical comparator C0M4 (a second allowable variation range of the frequency of bit clock signal Pc). A numerical value set corresponding to the upper limit frequency in the bit clock signal Pc (a numerical value set corresponding to the shortest period in the second allowable change range of the period of the bit clock signal Pc) is calculated according to the above-mentioned calculation method. Numeric value N2n
±5% of the value, i.e., N 2s = N 2nX
O,95,N2Q=N2nX1.05
For example, when an intermittent demodulated signal is demodulated by the digital signal demodulator of the present invention, the demodulated signal changes from a no-signal period to a signal-existing period. The operating state when the phase-locked loop PLL changes from the unlocked state to the locked state will be explained as follows.

In other words, if the demodulated signal to be demodulated by the digital signal demodulator has a signal period and a no-signal period aligned on the time axis as shown in FIG. Phase-locked loop PL in
The frequency (period) of the bit clock signal output from the L voltage controlled oscillator ■CO may deviate greatly from the normal value, but as mentioned above, the voltage control of the phase-locked loop PLL during the no-signal period. When the frequency (period) of the bit clock signal output from the oscillator vCO deviates significantly from the normal value, the frequency comparison circuit FC
The second frequency comparison circuit FCCb in C determines whether the frequency of the bit clock signal Pc deviates from the normal value by ±5% or more with respect to the pulse period T1 generated by the first pulse source 5SGa. Detecting and generating a signal during a short time corresponding to the period T2 of the pulses generated from the second pulse source 5scb having a period TI) T2,
Thereby, the error signal generated by the error signal generation circuit ESC operates to quickly bring the frequency of the bit clock signal Pc generated from the voltage controlled oscillator vCO in the phase-locked loop PLL close to the normal frequency, Further, the first frequency comparison circuit FCCa in the frequency comparison circuit FCC operates so that the frequency of the bit clock No. 943 Pc is within ±1% from the normal value, and the frequency comparison circuit FCC operates within a short time. In this case, the frequency of the bit clock signal Pc is kept within ±1% from the normal value.

As is clear from the above, the frequency comparison operation performed by the frequency comparison circuit FCC described above is based on the period generated by the first pulse source 5SGa. During the pulse period of Tl, is the number N1 of bit clock signals generated from the voltage controlled oscillator ■cO in the phase-locked loop circle L within the permissible range? This is done by determining whether the minimum value of the number N1Ω is smaller than s or larger than the maximum number N1Ω of the allowable range. The frequency comparison operation is performed by comparing the period T2 generated by the second pulse source 5SGb, which has a period T2 having a relationship of TI )T2 with respect to the period T1 of the pulse generated by the first pulse source 5SGa. Is the number N2 of bit clock signals generated from the voltage controlled oscillator vCO in the phase-locked loop PLL during UJ within the permissible range or the minimum number within the permissible range? Is it less than the number of values N2s, or is the maximum value within the allowable range?5'K<
This is done by determining whether the period TI of the pulses generated by the first pulse source 5SGa used for the frequency comparison operation in the first frequency comparison circuit FCCa is too large. If it is short, the frequency change may exceed the first allowable frequency range during lock-in of the phase-locked loop PLL or when the frequency of the bit clock signal fluctuates due to noise etc. A signal is output from the first frequency comparator circuit FCC, making the entire circuit operation unstable.
As for the pulses that are not generated by the first pulse source 5SGa used for the frequency comparison operation in the first frequency comparison circuit F CCa, the period T1 thereof is set to be long, and the count value during that long period is averaged as described above. A judgment is made as to whether or not the value exceeds ±1%.

Now, in order to adjust the device by changing the gain of the control loop in the bit clock signal generator of the digital signal demodulator, for example, in the embodiment shown in FIG. Circuit E
This can be carried out by changing the resistance values of the resistors 7, 8° 1.00, and 101 of the resistor network that constitutes the analog calculation circuit in the SC, but other adjustment means are shown in Fig. 12. As shown in FIG. Second frequency comparison circuit FCC
I, can be implemented by varying the pulse width of the output signal from FCC2 by means of a monostable multivibrator H, MM2. The NOR circuit N0RI and OR circuit ORI shown in FIG.
NOR circuit N0RI and OR circuit ORI shown in the figure
It shows.

FIG. 13 shows the first example in the embodiment shown in FIG. Second error signal generation circuit ESG1. The pulse width of the output signal from the NAND circuit NAND and the output signal from the AND circuit in ESC2 is determined by the monostable multivibrator MHI.
This is a configuration example in which the gain of one control loop is changed by changing it by , MM2, and the device is adjusted accordingly. -46, etc. indicate the NOR circuit N0RI, the OR circuit ORI, and the resistors 43-46 shown in FIG.

Next, a changeover switch SWI provided in the frequency comparison circuit FCC shown in FIGS. 5 and 6.

Sυ2 will be explained. When the demodulated signal to be demodulated in the digital signal demodulation circuit of the present invention is, for example, a reproduction signal from a magnetic recording TL reproduction device, the magnetic tape is rapidly run by fast forwarding or rewinding. Sometimes, the frequency of the demodulated signal deviates from the positive n frequency by a large +1].

Even if the antinode P1 signal is a signal other than the reproduced signal from the magnetic recording/reproducing device, when the frequency of the f'd tone signal deviates from the normal frequency to a certain degree, the first frequency comparator circuit in the frequency comparator circuit FCC In the second frequency comparator circuit FCC2 such as FCCI, the variation of the permissible frequency S(1)
It is easy to see that it is not possible to maintain an effective operation for the first frequency comparator circuit FCC, which has a narrow area.

Therefore, as shown in ^'lf, if the frequency of the demodulated signal is positive j
)′! If the frequency deviates by a large 1]1 from the frequency of
The frequency comparison operation of the frequency ratio 'r'> circuit FCCI is made to be unrelated to the frequency ratio 2l distribution g;'IFCC operation a1;, and the frequency comparison operation in the frequency ratio 0 circuit FCC is set to the allowed frequency. When the frequency of the bit clock signal falls within the permissible frequency variation range of the second frequency comparison circuit FCC2, In addition, the frequency comparison operation in the second frequency comparison circuit FCC2 performs stable operation without being disturbed by the excessive frequency comparison operation by the first frequency comparison circuit FCC, which has a narrow allowable frequency change range. In addition, the aforementioned changeover switch 5ljl, SW2
One or both of the movable contacts C may be switched to the fixed contact side.

In addition, in implementation, the above-mentioned second frequency comparison circuit F
By adding a third frequency comparison circuit FCCc, which has a wider permissible frequency change range than the permissible frequency change range in CCb, as shown in Fig. 14, the frequency of the bit clock signal can be further shifted by 2l. In this case, the frequency comparison operation may be performed only by the third frequency comparison circuit FCCc. In FIG. 14, Ss
c, SQc, etc. are the already mentioned signals Ssa, SQ a, S
This is a signal similar to sb, SD, b, etc.

FIG. 15 shows another configuration example of the configuration example shown in FIG. 12 already described in which the device is adjusted by changing the gain of one round of the control loop in the bit clock signal generation device of the digital signal demodulation device. , in this configuration example, M
MI, MM2. MM3. MM4 is a monostable multivibrator, SW3. Sυ4 is a changeover switch, and
The first frequency comparison circuit FCCa, the second frequency comparison circuit FCCb, the NOR circuit N0RI, the OR circuit OR1, etc. are the first frequency comparison circuit FCCa in FIG.

They correspond to the second frequency comparison circuit FCCb, the NOR circuit NOR1, and the OR circuit 0 old, respectively. 16(a) and (b) are the changeover switches 5Ii13. used in FIG. 15 described above. This shows an example of the configuration of SW/I.

Next, the configuration and operation of the phase comparison circuit PC in the phase locked loop PLL shown in FIGS. 5 and 6 will be explained. In the phase comparator circuit PC in the phase-locked loop circle 7L shown in FIGS. The detection window pulse P as shown in FIG. 7(a) generated in
The bit clock signal Pc generated by the voltage controlled oscillator vCO in the phase-locked loop PLL, for example as shown in FIG. 7(b), is supplied to the input terminal 2l. (Figure 7)
The bit clock signal Pc shown in b) is the voltage controlled oscillator vCO in the phase-locked loop PLL.
(This example shows a case where the bit clock signal Pc is generated with a regular period.)

The detection window pulse PW supplied to the input terminal 10 described above is supplied to the NAND circuit 14 as one input thereof, and is also supplied to the exclusive OR circuit 15 as one input thereof. Further, the bit clock signal -Pc supplied to the input terminal 2l is applied to the NAND circuit 14 as the other input thereof.

From the aforementioned NAND circuit 14 to which the detection window pulse Pw shown in FIG. 7(a) and the bit clock signal Pc shown in FIG. 7(b) are applied, the seventh
A pulse Pn as shown in FIG. is supplied as one input.

The pulse Pn shown in FIG. 7(c) output from the NAND circuit 14 is a detection window pulse in which the rising edge of the waveform is ahead of the falling edge of the waveform of the bit clock signal Pc. This is a pulse in which the rising edge of the waveform of Pw is a falling edge, and the falling edge of the waveform of the bit clock signal Pc is a rising edge.

The aforementioned pulse Pn is given to the l1li algebraic OR circuit 16 as one input thereof, and the other input of the exclusive OR circuit 16 is supplied with the high level voltage H in the logic circuit. The above exclusive OR circuit 16
On the output side of the pulse P shown in FIG.
Pulse Pnr with opposite polarity to n ((d) in Figure 7)
is output.

As mentioned above, the exclusive OR circuit 15 to which the nine detection window pulses PW supplied to the input terminal 10 and the pulses Pn output from the NAND circuit 14 are supplied as two inputs, as shown in FIG. Pulse Px as shown in (e)
That is, as shown in FIG. 7(b), the falling edge of the waveform is advanced with respect to the falling green waveform of the detection window pulse PW shown in FIG. 7(a). A pulse Px is output, in which the falling edge of the bit clock signal Pc as shown in FIG.

A resistor 10 is connected to the output side of the exclusive OR circuit 15 described above.
, 21 are connected, and the J
1. One end of each resistor 20.degree. 22 is connected to the output side of the algebraic OR circuit. A high level voltage I- in the logic circuit is connected to the other ends of the resistors 19 and 20 described above.
1 is connected, and the other ends of the resistors 21 and 22 described above are connected to each other at a connection point A.

One end of a noise reduction circuit 29 consisting of diodes 27 and 28 connected in parallel with opposite connection polarities is connected to the connection point A, and the other end of the noise reduction circuit 29 is connected to the connection point A. is connected to the inverting input terminal of operational amplifier 30.

Therefore, the pulse Px shown in FIG. 7(e) output from the exclusive OR circuit 15 and the pulse Px shown in FIG. 7(e) output from the exclusive OR circuit 16
The pulse Pnr as shown in FIG.
As a result of the addition by the analog adder circuit consisting of 2 and 2, the addition signal Pa as shown in FIG. 7(f) is outputted to the above-mentioned point A.

As mentioned above, the addition signal Pa appearing at point A exceeds the threshold voltage of the diodes 27 and 28 in the noise reduction circuit 29 when it is applied to the inverting input terminal of the operational amplifier 30 via the noise reduction circuit 29. Since only the signal is provided to the inverting input terminal of the operational amplifier 30,
The voltage controlled oscillator CO is controlled by the noise reduction circuit 29 described above.
The noise component of the control signal supplied to the control signal can be reduced.

The signal supplied to the inverting input terminal of the operational amplifier 30 is integrated by the operational amplifier 30 and is supplied from the output terminal I3 to the voltage controlled oscillator vCO as an oscillation frequency control voltage. , an exclusive OR circuit 1 is connected to the non-inverting input terminal of the operational amplifier 30 described above.
The output voltage of 7.18 is given as the voltage at the 0 point that is added by the analog adding circuit, and the operational amplifier 30 uses the voltage appearing at the 0 point as a threshold. Performs an integral operation on the signal supplied to the inverting input terminal.

That is, the aforementioned exclusive OR circuit 17 receives the voltage from the terminal 32 and the voltage from the terminal 32 as two input signals thereto.
The exclusive OR circuit 18 is supplied with the voltage from the terminal 32 and the high level voltage in the logic circuit as two input signals to the exclusive OR circuit 18. is given.

The voltage applied to the terminal 32 described above may be a high level voltage in the logic circuit, a low level voltage in the logic circuit, or the output voltage of the NAND circuit 14 described above.

The output side of the exclusive OR circuit 17 is connected to the high level voltage H in the logic circuit via a resistor 23 and to the 0 point via a resistor 25. The output side of the summation circuit 18 is connected to the high level voltage in the logic circuit via the resistor 24 and to the 0 point via the resistor 26, so that the exclusive logic can be realized as described above. Sum circuit 17.1
8 output voltages are added by an analog adder circuit to 0
The voltage at the point is applied to the non-inverting input terminal of the operational amplifier 30, and the operational amplifier 30 described above uses the voltage at the zero point applied to the non-inverting input terminal as a threshold.
It performs an integration operation on the signal supplied to the inverting input terminal of the inverter.

In FIG. 7, ■4 indicates a high-level voltage in the logic circuit, L indicates a low-level voltage in the logic circuit, and M indicates a high-level voltage in the logic circuit and a low-level voltage in the logic circuit. This is the voltage obtained as a result of adding these in an analog manner.

As can be seen by referring to the waveform diagrams shown in FIG. 7(a) to FIG. 7(f),
As shown in (dL(e)) of the seventh tel, the pulse Px outputted from the In this case, the resistor 34 and capacitor 33 are connected to the operational amplifier 3 made up of Hiroshi A.
The X'S result of the integral operation at 0 is O, and in this case, the signal level of the output signal from the phase comparator circuit pc maintains the voltage up to that level, so the phase comparator circuit pc
The voltage controlled oscillator vCO is not charged or discharged by the output signal from the oscillator vCO.

However, the detection window pulse P shown in FIG. 7(a)
The relative phase relationship between w and the bit clock signal Pc shown in FIG. 7(b) is shown in FIG. 7(a) and (b).
), the pulse Pnr shown in FIG. 7(d) increases by +41.
and the pulse width of the pulse clock signal PX shown in FIG. Accordingly, the voltage controlled oscillator vCO adjusts the relative phase relationship between the detection window pulse PW and the bit clock signal P'c as shown in FIG. 7(a).
, so that it is returned to the normal state shown in (b).
Its oscillation frequency is automatically controlled.

Note that a noise reduction circuit 37 is connected between the point B and the input terminal 12, and includes two diodes 3s and 36 connected with opposite polarities. The above-mentioned input terminal 12 has the above-mentioned first. second error signal generation circuit EsGx,
1st from asc2. Second error signal S le.

S2e is supplied.

FIG. 8 is a block diagram showing another example of the configuration of the phase comparison circuit PC. In FIG.
The same drawing numerals as those used in FIG. 7 are given. In addition, (,) to (e) in Fig. 9 show the operation of the phase comparator circuit pc shown in Fig. The explanatory waveform diagrams (a) to (e) in Figure 10 show the phases shown in Figure 8 when the voltage controlled oscillator ■CO is generating a bit clock signal with a cycle shorter than the normal cycle. It is a waveform diagram for explaining the operation of the comparator circuit PC, and furthermore, (a) to (e) of FIG.
) respectively show waveform diagrams for explaining the operation of the phase comparator circuit pc shown in FIG. 8 in a state where the voltage controlled oscillator vCO is generating a bit clock signal with a longer period than the normal period.

In FIG. 8, the detection window pulse Pw supplied to the input terminal 10 is supplied to the inverter 39 and also to the clear terminal of the D-type flip-flop 41. Further, the bit clock signal P'c supplied to the input terminal 2l is supplied to the inverter 38, and
It is also supplied to the clock terminal of the D-type flip-flop 41.

The output signal of the inverter 39 described above is supplied to the clock terminal of the D-type flip-flop 42, and the output signal of the inverter 38 described above is supplied to the clock terminal of the D-type flip-flop 42.
2 clear terminal and data terminal. In addition, the data terminal of the old D-type flip-flop mentioned above has
A high-level voltage H is applied to the logic circuit, and a resistor 20.
One end of each of the resistors 19 and 22 is connected to one terminal of the Q bar of the D-type flip-flop 42, and one end of each of the resistors 19 and 21 is connected to one terminal of the Q bar of the D-type flip-flop 42.

Furthermore, a low level voltage in the logic circuit is supplied to the clock terminal, data terminal, clear terminal, etc. of the D-type flip-flop 4o, and the Q terminal of the D-type flip-flop 40 is supplied with each of the resistors 24 and 26. A resistor 23 is connected to one end of the Q-bar of the D-type flip-flop 40.
．． 25 are connected at one end.

The other ends of the resistors 19, 20, 23.24 are connected to the high level voltage ()-1 in the logic circuit, and the other ends of the resistors 21.22 are connected to point A, The other ends of resistors 25 and 26 are connected to point C.

The above-mentioned point A is connected to the inverting input terminal of the operational amplifier 30 via the noise reduction circuit 29 consisting of two diodes 27°28 and the point B, and the above-mentioned point C is connected to the inverting input terminal of the operational amplifier 30. is connected to the non-inverting input terminal of A noise reduction circuit 37 consisting of two diodes 35 and 36 is connected between the above-mentioned point B and the input terminal 12. Between the output side and the inverting input terminal of the operational amplifier 30 described above, a series-connected seven circuit including a resistor 34 and a capacitor 33 is connected.

In a state where the bit clock signal Pc generated by the voltage controlled oscillator ■CO has a regular period, the phase comparator circuit pc shown in FIG. Perform the operations shown in a) to (,).

That is, in the waveform diagram shown in Figure 9, (,) in Figure 9
is the input terminal 10 in the phase comparator circuit PC shown in FIG.
is the detection window pulse Pw supplied to , and is the detection window pulse Pw supplied to (
b) is the pulse clock signal Pc supplied to the input terminal of the phase comparison circuit +) C shown in FIG. 8; circuit pc
Q of the D-type flip-flop 41 in <? FIG. 9(d) shows the output signal of the always low level state appearing on the g terminal, and furthermore, (d) of FIG.
9(e) shows the output signal of the above-mentioned D-type flip-flop in the phase comparator circuit PC shown in FIG. An output signal that is always at a low level that appears at the Q terminal of the D-type flip-flop 42 and an output signal that is always at a high level that appears at the Q terminal of the D-type flip-flop 42 are added by an analog adder circuit that includes resistors 21 and 22. Figure 8 shows the state of the output signal that appears at point A when the bit clock signal Pc generated by the voltage controlled oscillator vco has a regular period. In the phase comparator circuit PC shown in FIG.
Since the signal level is M as shown in (e) of the figure, no error signal is generated for vCO.

Next, while the voltage controlled oscillator vcO is generating the bit clock signal Pc with a period shorter than the normal period as shown in FIG. 10(b), At the Q terminal of the D-type flip-flop 41 of the phase comparison circuit pc shown in FIG. A in the phase comparator circuit PC shown in FIG. 8 in a state where a falling pulse appears at the falling edge of Pw and therefore the voltage controlled oscillator vCO is generating a bit clock signal Pc with a cycle shorter than the normal cycle.
At the point, the pulse shown in FIG. 10(c) appearing at the Q terminal of the D-type flip-flop 41 and the pulse shown in FIG.
The always high level H signal shown in d) is connected to the resistor 2.
The pulse shown in FIG. 10(e) added by the analog adder circuit consisting of 1.22 appears at point A.

The pulse shown in FIG. 10(e) described above is supplied to the inverting input terminal of the operational amplifier 3o via the noise reduction circuit 29. Furthermore, the non-inverting input terminal of the operational amplifier 30 is supplied with a voltage (logic circuit Since the operational amplifier 30 uses the voltage applied to the non-inverting input terminal as a threshold value, the operational amplifier 30 applies the voltage to the inverting input terminal using the voltage applied to the non-inverting input terminal as a threshold. The supplied voltage is integrated to generate an error signal, which is applied to the voltage controlled oscillator vCO via the output terminal 13. The voltage controlled oscillator vCO is automatically controlled so that its oscillation frequency is lowered by the error signal described above, and the bit clock signal generated by the voltage controlled oscillator vCO is returned to its normal cycle.

Now, in a state where the voltage controlled oscillator ■CO is generating a bit clock signal Pc with a period longer than the normal period as shown in FIG. 2l(b), the phase comparison circuit shown in FIG. As shown in FIG. 2l(d), the Q-bar terminal of the D-type flip-flop 42 of the PC has the following:
A pulse appears that falls at the falling edge of the detection window pulse Pw and rises at the rising edge of the bit clock signal Pc, and therefore the voltage controlled oscillator vCO is generating the bit clock signal Pc with a period longer than the normal period. At point A in the phase comparator circuit pc shown in FIG. 8 in this state, the pulse shown in FIG. The signal at the same signal level shown in FIG.
The 2nd l added by the analog adder circuit consisting of 2
The pulse shown in (,) in the figure appears at point A.

The pulse shown in FIG. 2l (e) described above is supplied to the inverting input terminal of the operational amplifier 30 via the noise reduction circuit 29. In addition, a voltage (logic circuit Since the operational amplifier 30 uses the voltage applied to the non-inverting input terminal as a threshold value, the operational amplifier 30 converts the voltage applied to the inverting input terminal to the voltage applied to the non-inverting input terminal. An error signal is generated by integrating the voltage supplied to the output terminal 13, and is applied to the voltage controlled oscillator VCO via the output terminal 13. The voltage controlled oscillator vCO is automatically controlled so that its oscillation frequency is increased by the above-mentioned error signal, and the bit clock signal generated by the voltage controlled oscillator vCO is returned to its normal cycle.

As mentioned above, when the period of the bit clock signal Pc generated by the voltage controlled oscillator ■CO of the phase-locked loop PLL is normal, the error signal generation circuit (fifth
Error signal generation circuit ESC in the figure, 1. Second
The output signal of the error signal generating circuits ESGI, ESG2) does not become a frequency error signal, and in this case, the signal supplied from the frequency comparator circuit FCC to the input terminal 12 of the phase comparator circuit PC also generates a signal from the phase comparator circuit. The pc error signal is not changed.

Next, when the period of the bit clock signal Pc generated by the voltage controlled oscillator vCO of the phase-locked loop PLL becomes shorter than in the normal case, the output signal of the error signal generation circuit described above is output from the logic circuit. is made into a high-level signal and is supplied to the input terminal 12 of the phase comparator circuit PC as a frequency error signal.
Since the voltage at point B in the phase comparison circuit PC is held at a high level in the logic circuit, the error signal of the phase comparison circuit PC is changed, and the oscillation frequency is transmitted from the phase comparison circuit PC to the voltage controlled oscillator vCO. By applying a control signal that rapidly reduces the oscillation frequency of the voltage controlled oscillator vCO, the period of the bit clock signal is brought to a normal value.

Contrary to the above, the bit clock signal P generated by the voltage controlled oscillator vCO of the phase-locked loop PLL
When the period of c becomes longer than in the normal case, the signals applied to the input terminals 5 and 6 of the error signal generation circuit ESC both become low level signals.

Therefore, the bit clock signal Pc generated by the voltage controlled oscillator ■CO of the phase-locked loop PLL
When the cycle of is longer than in the normal case, the output signal from the error signal generation circuit described above is made into a low level signal in the logic circuit, and it is sent as a frequency error signal to the input terminal of the phase comparator circuit tlc. By being supplied to I2, the voltages at eight points in the phase comparator circuit pc are held at a low level in the logic circuit, so the error signal of the phase comparator circuit pc is changed, and the voltages at the eight points in the phase comparator circuit pc are changed.
By applying a control signal to the voltage controlled oscillator vCO to rapidly increase its oscillation frequency by 1, the oscillation frequency of the voltage controlled oscillator VCO is rapidly increased by 1, thereby increasing the period of the bit clock signal. is set to a normal value.

(Effects) As is clear from the detailed explanation above, a single complete digital signal demodulator can be modulated according to a modulation method that is composed of a signal that intermittently includes phase information of a bit clock signal. The demodulated digital signal is a digital signal, and from the time position of either the rising edge or the falling edge of the waveform in the demodulated signal, or from both time positions, the pulse 1 of the clock signal is shorter than the pulse l of the clock signal. means for generating a detection window pulse having a predetermined pulse l]; and means for applying the detection window pulse as a comparison wave to a phase-locked loop comprising a phase comparison circuit and a voltage controlled oscillator. and the period is T
a first pulse source generating a first pulse of I and a period T;
2 is a second pulse source that generates a second pulse having a relationship of 'r2<T1 with respect to the period T1 of the first pulse generated by the first pulse source described above; A first measurement in which the period TI of the first pulse generated by the first pulse source described above is measured using a pitch-to-tallock signal obtained from a voltage controlled oscillator in a locked loop as a reference pulse for measurement. means and the above-mentioned phases.
The bit clock signal obtained from the voltage controlled oscillator in the locked loop is used as a pulse of nQ for measurement, and the period of the second pulse 'r' is generated by the second pulse source described above.
, 2, and the measured value when the period T1 of the first pulse generated by the first pulse source is changed by the reference pulse described above. When the measurement value N1 is equal to or smaller than the minimum value Nls determined in correspondence with the first permissible change range of the oscillation frequency in the voltage controlled oscillator, the first signal is generated, and the measurement described above is performed. means for generating a second signal when the value N1 is equal to or greater than a maximum value N1f1 determined corresponding to the first allowable change range of the oscillation frequency;
When the period T2 of the second pulse generated by the pulse source is counted using the reference pulse described above and the measured value is N2, the first value set for the oscillation frequency of the voltage controlled oscillator is The above-mentioned measured value N2 is higher than the minimum value N2s determined corresponding to the second permissible change range of the oscillation frequency, which is set to have a larger frequency change rate than the frequency change rate in the permissible change range.
A third signal is generated when the measured value N2 is small, and a third signal is generated when the measured value N2 is equal to or greater than the maximum value N2l determined corresponding to the second tolerance change range of the oscillation frequency in the voltage controlled oscillator. means for generating a first error signal using the first signal and third signal; and means for generating a second error signal using the second signal and fourth signal. and means for controlling the error signal of the phase comparator circuit in the phase-locked loop according to each of the error signals, and a bit clock. The demodulated signal is a digital signal that is modulated according to a modulation method such as a signal that intermittently contains phase information of the signal, and the time of either the rise or fall of the waveform in the demodulated signal means for generating a detection window pulse having a predetermined pulse width shorter than the pulse width of the bit clock signal from the position or both time positions; a first pulse source that generates a first pulse having a period of T1; and a first pulse source that generates a first pulse having a period of T2; For the period T1 of the first pulse generated, T2<
A second pulse source that generates a second pulse having a relationship of T1 and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above are used as reference pulses for measurement. a first measuring means for measuring the period T1 of the first pulse generated by the pulse source; and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above as a reference pulse for measurement. , a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source described above, and a period T1 of the first pulse generated by the first pulse source described above; When the measured value when counting with the reference pulse is N1, if the measured value N1 is less than the minimum value Nls determined corresponding to the first allowable change range of the oscillation frequency in the voltage controlled oscillator, the 1, and the measured value N1 is a maximum value N determined in correspondence with the first permissible change range of the oscillation frequency.
means for generating a second signal in the case of 1l or more, and a period 7 of the second pulse generated by the second pulse source described above;
When N2 is the measured value when UI T 2 is counted using the above-mentioned reference pulses, compared to the frequency change rate in the above-mentioned first allowable change range set for the oscillation frequency of the voltage-controlled oscillator. The above-mentioned total it'! is lower than the minimum value N2s determined corresponding to the second permissible change range of the oscillation frequency, which is set to have a large frequency change rate. A third signal is generated when the I value N2 is small, and the measurement 'If N2 is greater than or equal to the maximum value N2l determined corresponding to the second permissible change range of the oscillation frequency in the voltage controlled oscillator. means for generating a fourth signal in the above case; means for obtaining a first error signal by means of the first 4g signal and the third signal; means for obtaining the second error signal; means for controlling the error signal of the phase comparison circuit in the phase-locked loop by the respective error signals; and means for obtaining the first signal and the second signal. The digital signal demodulator of the present invention is a digital signal demodulator comprising a bit clock -83= signal generator comprising means for selectively disabling one or both of the signals. According to this, the signal to be demodulated is intermittent on the time axis with relatively long no-signal periods,
Even if the phase-locked loop becomes unlocked during a no-signal period, the phase-locked loop is quickly brought into lock within a short period of time by a signal that appears again after the no-signal period has elapsed. Therefore, according to the digital signal demodulation device of the present invention, the problems with the conventional digital signal demodulation device described above can be satisfactorily solved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration principle and operating principle of the digital signal demodulation device of the present invention, and FIG. An example of an intermittent signal, FIG. 3 is a plan view of the magnetic head portion of a rotating magnetic head type magnetic recording and reproducing device, and FIGS. 4 and 7, and FIGS. 9 to 2l are waveform diagrams for explanation. , FIGS. 5 and 6 are block diagrams of embodiments of the digital signal demodulator of the present invention, FIGS. 8 and 1, respectively.
2 to 16 are block diagrams of some components of the digital signal U adjustment device of the present invention. DuC...detection window pulse generation circuit, PLL...phase locked loop, PC...phase comparison circuit, v
CO...voltage controlled oscillator, FCC...frequency comparison circuit, FCCa...first frequency comparison circuit, FCCb...
...Second frequency comparison circuit, ESC...Error voltage generation circuit, ESGI...First error voltage generation circuit, H5G2
...Second error voltage generation circuit, SSG a...first
pulse source, SSG b...second pulse source, SWI
, SV2... 1st. Second selector switch, ^ ^
He he he he he he (j -OLJ
”t:I Φ (In!5JVQ
! '++lI+l ΔE Δ Procedural amendment (spontaneous) 1. Indication of the case 1985 Patent Application No. 99900 2. Name of the invention Digital signal demodulator 3. Person making the amendment Relationship with the case Patent Applicant Location Kanagawa 3-12 Moriya-cho, Kanayō-ku, Yokohama City, Prefecture Name (432) Victor Company of Japan Co., Ltd. 4, Agent Facsimile 03 (472) 2257-5, Date of amendment order (voluntary) (3) Attached drawings Figures 5 and 5 Figures 7, 13, and 16 are corrected as shown in the attached sheet. 7. Contents of amendment (1) The scope of claims will be amended as shown in the attached sheet. (2) Correct "pulse r2l" in line 10 of page 13 to "period". (3) Correct "Pulse Width" in the second line of page 16 to "Period". 7(4) Page 19, line 17'' “Correct the pulse “2l” to “period”. (5) Correct “Pulse Width” on page 19, line 20 to “Period T”. (6) Generated in page 20, line 19, rssGb” to rSSG
b (not shown in FIG. 1). (7) Page 23, line 12 [supplied pulse t2lT
Correct J to "period T". (9) Correct “period” in line 6 of page 29 to “r period T”. (10) Correct “signal pulse” in line 7 of page 33 to “signal”. (2l) Correct "signal pulse" in line 12 of page 33 to "signal". (12) Correct “signal pulse” in line 15 of page 33 to “signal”. (13) Correct "signal pulse" in the second line of page 35 to "signal". (14) Page 35, line 4 to line 5 of the same page ``Correct signal pulse j to ``signal''. (15) Correct “signal pulse” in line 8 of page 35 to “signal”. (16) Correct "signal pulse" from line 10 on page 35 to line 2l on the same page to "signal". (17) Correct "signal pulse" from line 14 to line 15 of page 35 to "signal". (N8) Correct “signal pulse” in line 5 of page 36 to “signal”. (19) Page 58, line 12, “NOR circuit NORM, OR circuit OR1” is changed to “NAND circuit NAND, AND circuit AND
Correct to J. (20) Correct the first line of page 80 to "Pulse period is January". Correct the figure as shown in the attached sheet. ``Claim ■: A demodulated signal is a digital signal that is modulated according to a modulation method such as a signal that intermittently includes phase information of a clock signal, and the demodulated signal is means for generating a detection window pulse having a predetermined pulse 1 shorter than 1q + 0 of the bit clock signal from one or both of the rising and falling points of the waveform; a means for applying the detection window pulse as a comparison wave to a phase-locked loop comprising a phase comparator circuit and a voltage controlled oscillator; and a first means for generating a first pulse having a period of T1. With respect to the pulse source and the period T1 of the first pulse generated by the first pulse source whose period T2 is as described above,
Calculate the clock signal obtained from the second pulse source that generates the second pulse with the relationship T2<TI and the voltage controlled oscillator in the phase-locked loop described above. A first measurement = 3 means for measuring the period T1 of the first pulse generated by the first pulse source as a reference pulse for 1III, and voltage control in the phase-locked loop described above. a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source using the bit clock signal obtained from the oscillator as a reference pulse for measurement; When the measured value when counting the period T1 of the first pulse generated by the source with the above-mentioned reference pulse is N1, the measured value N1 is the first allowable change range of the oscillation frequency in the voltage controlled oscillator. A first signal is generated when the measured value N1 is equal to or less than a minimum value Nls determined corresponding to the above, and a maximum value determined corresponding to the first allowable change range of the oscillation frequency. A means for generating a second signal in the case of N10 or more, and a measured value when the cycle T2 of the second pulse generated by the second pulse source described above is run from 1 to 1 with the reference pulse described above is N2 When the oscillation frequency of the voltage controlled oscillator is set to have a second rate of change in frequency that is larger than the rate of change in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. A third signal is generated when the measured value N2 is smaller than the minimum value N2s determined corresponding to the allowable change range, and the measured value N2 is the second signal of the oscillation frequency in the voltage controlled oscillator. means for generating a fourth signal when the maximum value N2D is greater than or equal to a maximum value N2D determined in correspondence with an allowable variation range; and means for obtaining a first error signal from the first signal and the third signal. , means for obtaining a second error signal using the second signal and fourth signal, and means for obtaining the phase-locked signal using the above-mentioned error signals.
A digital signal demodulator 2 comprising a bit clock signal generator comprising means for controlling an error signal of a phase comparator circuit in a loop; A digital signal that has been modulated according to the modulation method is used as a demodulated signal, and the above-mentioned p+-tallock signal is calculated from the time position of either the rising edge or the falling edge of the waveform in the demodulated signal, or from both time positions. means for generating a detection window pulse having a predetermined pulse 2l shorter than normal, and comparing said detection window pulse to a phase locked loop comprising a phase comparator circuit and a voltage controlled oscillator; a first pulse source that generates a first pulse having a period T1; and a period T2 for the period T1 of the first pulse generated by the first pulse source described above; A second pulse source that generates a second pulse having a relationship of a first measuring means for measuring the period TI of the first pulse generated by the first pulse source, and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop as a reference for measurement. a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source, and a first pulse generated by the first pulse source;
The period T1 of the pulse is set to 1 with the reference pulse described above.
The first signal is output when the measured value N1 is equal to or less than the minimum value N1s determined corresponding to the first allowable change range of the oscillation frequency in the voltage controlled oscillator. means for generating a second signal and generating a second signal when the measured value N1 is equal to or greater than a maximum value N1l determined corresponding to the first allowable variation range of the oscillation frequency; When the period T2 of the second pulse generated by the second pulse source is set to the above-mentioned reference pulse and the total value of 42l is set as N2, the above-mentioned oscillation frequency set for the voltage controlled oscillator is 1st
The frequency change rate is set to have a frequency change rate larger than the frequency change rate within the allowable change range of the oscillation frequency. When the measured H1 value N2 is small, the third
and when the HI measurement value N2 is equal to or greater than the maximum value N2a determined in correspondence with the second allowable change range of the oscillation frequency in the voltage controlled oscillator, a fourth signal is generated.
means for generating the first signal and the third signal;
means for obtaining a first error signal by means of the above-described second signal and the fourth signal; and means for obtaining the above-mentioned phase-locked loop by each of the above-mentioned error signals. A bit clock signal comprising means for controlling an error signal of a phase comparator circuit therein, and means for selectively disabling one or both of the first signal and second signal. "Digital signal demodulator equipped with a generator"

Claims (1)

[Claims] 1. A demodulated signal is a digital signal that is modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal, and the rise and fall of the waveform in the demodulated signal is determined. or one time position,
Alternatively, means for generating a detection window pulse having a predetermined pulse width shorter than the pulse width of the bit clock signal from both time positions, and a phase comparison circuit and a voltage controlled oscillator to generate the detection window pulse. means for providing a comparison wave to a phase-locked loop comprising: a first pulse for generating a first pulse having a period T1;
, and the period T2 is T2<T1 for the period T1 of the first pulse generated by the above-described first pulse source.
A second pulse source that generates a second pulse having a relationship of A first measuring means for measuring the period T1 of the first pulse generated by the pulse source, and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above as a reference pulse for measurement, a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source described above; and a period T1 of the first pulse generated by the first pulse source described above;
When N1 is the measured value when counted using the above-mentioned reference pulse, the measured value N1 is less than or equal to the minimum value N1s determined corresponding to the first allowable change range of the oscillation frequency in the voltage controlled oscillator. when the first signal is generated, and the measured value N1 is a maximum value N1l determined corresponding to the first permissible variation range of the oscillation frequency.
In the above case, the means for generating the second signal and the measured value when counting the period T2 of the second pulse generated by the above-mentioned second pulse source with the above-mentioned reference pulse are N
2, the second oscillation frequency is set to have a larger frequency change rate than the frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. Generates a third signal when the measured value N2 is smaller than the minimum value N2s determined corresponding to the allowable change range of
The measured value N2 is a maximum value N determined in correspondence with a second permissible change range of the oscillation frequency in the voltage controlled oscillator.
means for generating a fourth signal when the signal is equal to or greater than 2l; means for obtaining a first error signal from the first signal and third signal; and means for generating a first error signal from the first signal and the third signal; and means for controlling the error signal of the phase comparison circuit in the phase-locked loop according to each of the above-mentioned error signals. The demodulator 2 uses a digital signal modulated according to a modulation method such as a signal that intermittently includes phase information of a bit clock signal as a demodulated signal, and calculates the rise and fall of the waveform in the demodulated signal. the time position of either
Alternatively, means for generating a detection window pulse having a predetermined pulse width shorter than the pulse width of the bit clock signal from both time positions, and a phase comparison circuit and a voltage controlled oscillator to generate the detection window pulse. means for providing a comparison wave to a phase-locked loop comprising: a first pulse for generating a first pulse having a period T1;
, and the period T2 is T2<T1 for the period T1 of the first pulse generated by the above-described first pulse source.
A second pulse source that generates a second pulse having a relationship of A first measuring means for measuring the period T1 of the first pulse generated by the pulse source, and a bit clock signal obtained from the voltage controlled oscillator in the phase-locked loop described above as a reference pulse for measurement, a second measuring means for measuring the period T2 of the second pulse generated by the second pulse source described above; and a period T1 of the first pulse generated by the first pulse source described above;
When N1 is the measured value when counted using the above-mentioned reference pulse, the measured value N1 is less than or equal to the minimum value N1s determined corresponding to the first allowable change range of the oscillation frequency in the voltage controlled oscillator. when the first signal is generated, and the measured value N1 is a maximum value N1l determined corresponding to the first permissible variation range of the oscillation frequency.
In the above case, the means for generating the second signal and the measured value when counting the period T2 of the second pulse generated by the above-mentioned second pulse source with the above-mentioned reference pulse are N
2, the second oscillation frequency is set to have a larger frequency change rate than the frequency change rate in the first allowable change range set for the oscillation frequency of the voltage controlled oscillator. The above-mentioned measured value N2 is lower than the minimum value N2s determined corresponding to the allowable change range.
is small, and a third signal is generated when the measured value N2 is a maximum value N2l determined corresponding to a second allowable change range of the oscillation frequency in the voltage controlled oscillator.
Means for generating a fourth signal in the above case, means for obtaining a first error signal by the above-mentioned first signal and third signal, and means for obtaining the first error signal by the above-mentioned second signal and fourth signal. means for obtaining a second error signal; means for controlling the error signal of the phase comparison circuit in the phase-locked loop according to each of the error signals; and means for controlling the error signal of the phase comparison circuit in the phase-locked loop; A digital signal demodulator comprising a bit clock signal generator comprising means for selectively invalidating one or both signals.